1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 #ifndef _SFC_COMMON_EFSYS_H
11 #define _SFC_COMMON_EFSYS_H
15 #include <rte_spinlock.h>
16 #include <rte_byteorder.h>
17 #include <rte_debug.h>
18 #include <rte_memzone.h>
19 #include <rte_memory.h>
20 #include <rte_memcpy.h>
21 #include <rte_cycles.h>
22 #include <rte_prefetch.h>
23 #include <rte_common.h>
24 #include <rte_malloc.h>
28 #include "sfc_debug.h"
35 #define EFSYS_HAS_UINT64 1
36 #define EFSYS_USE_UINT64 1
37 #define EFSYS_HAS_SSE2_M128 1
39 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
40 #define EFSYS_IS_BIG_ENDIAN 1
41 #define EFSYS_IS_LITTLE_ENDIAN 0
42 #elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
43 #define EFSYS_IS_BIG_ENDIAN 0
44 #define EFSYS_IS_LITTLE_ENDIAN 1
46 #error "Cannot determine system endianness"
48 #include "efx_types.h"
51 typedef bool boolean_t;
61 * RTE_MAX() and RTE_MIN() cannot be used since braced-group within
62 * expression allowed only inside a function, but MAX() is used as
63 * a number of elements in array.
66 #define MAX(v1, v2) ((v1) > (v2) ? (v1) : (v2))
69 #define MIN(v1, v2) ((v1) < (v2) ? (v1) : (v2))
72 /* There are macros for alignment in DPDK, but we need to make a proper
73 * correspondence here, if we want to re-use them at all
76 #define IS_P2ALIGNED(v, a) ((((uintptr_t)(v)) & ((uintptr_t)(a) - 1)) == 0)
80 #define P2ROUNDUP(x, align) (-(-(x) & -(align)))
84 #define P2ALIGN(_x, _a) ((_x) & -(_a))
88 #define ISP2(x) rte_is_power_of_2(x)
91 #define ENOTACTIVE ENOTCONN
94 prefetch_read_many(const volatile void *addr)
100 prefetch_read_once(const volatile void *addr)
102 rte_prefetch_non_temporal(addr);
105 /* Code inclusion options */
108 #define EFSYS_OPT_NAMES 1
110 /* Disable SFN5xxx/SFN6xxx since it requires specific support in the PMD */
111 #define EFSYS_OPT_SIENA 0
112 /* Enable SFN7xxx support */
113 #define EFSYS_OPT_HUNTINGTON 1
114 /* Enable SFN8xxx support */
115 #define EFSYS_OPT_MEDFORD 1
116 /* Enable SFN2xxx support */
117 #define EFSYS_OPT_MEDFORD2 1
118 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
119 #define EFSYS_OPT_CHECK_REG 1
121 #define EFSYS_OPT_CHECK_REG 0
124 /* MCDI is required for SFN7xxx and SFN8xx */
125 #define EFSYS_OPT_MCDI 1
126 #define EFSYS_OPT_MCDI_LOGGING 1
127 #define EFSYS_OPT_MCDI_PROXY_AUTH 1
129 #define EFSYS_OPT_MAC_STATS 1
131 #define EFSYS_OPT_LOOPBACK 1
133 #define EFSYS_OPT_MON_MCDI 0
134 #define EFSYS_OPT_MON_STATS 0
136 #define EFSYS_OPT_PHY_STATS 0
137 #define EFSYS_OPT_BIST 0
138 #define EFSYS_OPT_PHY_LED_CONTROL 0
139 #define EFSYS_OPT_PHY_FLAGS 0
141 #define EFSYS_OPT_VPD 0
142 #define EFSYS_OPT_NVRAM 0
143 #define EFSYS_OPT_BOOTCFG 0
144 #define EFSYS_OPT_IMAGE_LAYOUT 0
146 #define EFSYS_OPT_DIAG 0
147 #define EFSYS_OPT_RX_SCALE 1
148 #define EFSYS_OPT_QSTATS 0
149 /* Filters support is required for SFN7xxx and SFN8xx */
150 #define EFSYS_OPT_FILTER 1
151 #define EFSYS_OPT_RX_SCATTER 0
153 #define EFSYS_OPT_EV_PREFETCH 0
155 #define EFSYS_OPT_DECODE_INTR_FATAL 0
157 #define EFSYS_OPT_LICENSING 0
159 #define EFSYS_OPT_ALLOW_UNCONFIGURED_NIC 0
161 #define EFSYS_OPT_RX_PACKED_STREAM 0
163 #define EFSYS_OPT_RX_ES_SUPER_BUFFER 1
165 #define EFSYS_OPT_TUNNEL 1
167 #define EFSYS_OPT_FW_SUBVARIANT_AWARE 1
169 #define EFSYS_OPT_EVB 0
173 typedef struct __efsys_identifier_s efsys_identifier_t;
176 #define EFSYS_PROBE(_name) \
179 #define EFSYS_PROBE1(_name, _type1, _arg1) \
182 #define EFSYS_PROBE2(_name, _type1, _arg1, _type2, _arg2) \
185 #define EFSYS_PROBE3(_name, _type1, _arg1, _type2, _arg2, \
189 #define EFSYS_PROBE4(_name, _type1, _arg1, _type2, _arg2, \
190 _type3, _arg3, _type4, _arg4) \
193 #define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \
194 _type3, _arg3, _type4, _arg4, _type5, _arg5) \
197 #define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \
198 _type3, _arg3, _type4, _arg4, _type5, _arg5, \
202 #define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \
203 _type3, _arg3, _type4, _arg4, _type5, _arg5, \
204 _type6, _arg6, _type7, _arg7) \
210 typedef rte_iova_t efsys_dma_addr_t;
212 typedef struct efsys_mem_s {
213 const struct rte_memzone *esm_mz;
215 * Ideally it should have volatile qualifier to denote that
216 * the memory may be updated by someone else. However, it adds
217 * qualifier discard warnings when the pointer or its derivative
218 * is passed to memset() or rte_mov16().
219 * So, skip the qualifier here, but make sure that it is added
220 * below in access macros.
223 efsys_dma_addr_t esm_addr;
227 #define EFSYS_MEM_ZERO(_esmp, _size) \
229 (void)memset((void *)(_esmp)->esm_base, 0, (_size)); \
231 _NOTE(CONSTANTCONDITION); \
234 #define EFSYS_MEM_READD(_esmp, _offset, _edp) \
236 volatile uint8_t *_base = (_esmp)->esm_base; \
237 volatile uint32_t *_addr; \
239 _NOTE(CONSTANTCONDITION); \
240 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_dword_t))); \
242 _addr = (volatile uint32_t *)(_base + (_offset)); \
243 (_edp)->ed_u32[0] = _addr[0]; \
245 EFSYS_PROBE2(mem_readl, unsigned int, (_offset), \
246 uint32_t, (_edp)->ed_u32[0]); \
248 _NOTE(CONSTANTCONDITION); \
251 #define EFSYS_MEM_READQ(_esmp, _offset, _eqp) \
253 volatile uint8_t *_base = (_esmp)->esm_base; \
254 volatile uint64_t *_addr; \
256 _NOTE(CONSTANTCONDITION); \
257 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_qword_t))); \
259 _addr = (volatile uint64_t *)(_base + (_offset)); \
260 (_eqp)->eq_u64[0] = _addr[0]; \
262 EFSYS_PROBE3(mem_readq, unsigned int, (_offset), \
263 uint32_t, (_eqp)->eq_u32[1], \
264 uint32_t, (_eqp)->eq_u32[0]); \
266 _NOTE(CONSTANTCONDITION); \
269 #define EFSYS_MEM_READO(_esmp, _offset, _eop) \
271 volatile uint8_t *_base = (_esmp)->esm_base; \
272 volatile __m128i *_addr; \
274 _NOTE(CONSTANTCONDITION); \
275 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_oword_t))); \
277 _addr = (volatile __m128i *)(_base + (_offset)); \
278 (_eop)->eo_u128[0] = _addr[0]; \
280 EFSYS_PROBE5(mem_reado, unsigned int, (_offset), \
281 uint32_t, (_eop)->eo_u32[3], \
282 uint32_t, (_eop)->eo_u32[2], \
283 uint32_t, (_eop)->eo_u32[1], \
284 uint32_t, (_eop)->eo_u32[0]); \
286 _NOTE(CONSTANTCONDITION); \
290 #define EFSYS_MEM_WRITED(_esmp, _offset, _edp) \
292 volatile uint8_t *_base = (_esmp)->esm_base; \
293 volatile uint32_t *_addr; \
295 _NOTE(CONSTANTCONDITION); \
296 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_dword_t))); \
298 EFSYS_PROBE2(mem_writed, unsigned int, (_offset), \
299 uint32_t, (_edp)->ed_u32[0]); \
301 _addr = (volatile uint32_t *)(_base + (_offset)); \
302 _addr[0] = (_edp)->ed_u32[0]; \
304 _NOTE(CONSTANTCONDITION); \
307 #define EFSYS_MEM_WRITEQ(_esmp, _offset, _eqp) \
309 volatile uint8_t *_base = (_esmp)->esm_base; \
310 volatile uint64_t *_addr; \
312 _NOTE(CONSTANTCONDITION); \
313 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_qword_t))); \
315 EFSYS_PROBE3(mem_writeq, unsigned int, (_offset), \
316 uint32_t, (_eqp)->eq_u32[1], \
317 uint32_t, (_eqp)->eq_u32[0]); \
319 _addr = (volatile uint64_t *)(_base + (_offset)); \
320 _addr[0] = (_eqp)->eq_u64[0]; \
322 _NOTE(CONSTANTCONDITION); \
325 #define EFSYS_MEM_WRITEO(_esmp, _offset, _eop) \
327 volatile uint8_t *_base = (_esmp)->esm_base; \
328 volatile __m128i *_addr; \
330 _NOTE(CONSTANTCONDITION); \
331 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_oword_t))); \
334 EFSYS_PROBE5(mem_writeo, unsigned int, (_offset), \
335 uint32_t, (_eop)->eo_u32[3], \
336 uint32_t, (_eop)->eo_u32[2], \
337 uint32_t, (_eop)->eo_u32[1], \
338 uint32_t, (_eop)->eo_u32[0]); \
340 _addr = (volatile __m128i *)(_base + (_offset)); \
341 _addr[0] = (_eop)->eo_u128[0]; \
343 _NOTE(CONSTANTCONDITION); \
347 #define EFSYS_MEM_SIZE(_esmp) \
348 ((_esmp)->esm_mz->len)
350 #define EFSYS_MEM_ADDR(_esmp) \
353 #define EFSYS_MEM_IS_NULL(_esmp) \
354 ((_esmp)->esm_base == NULL)
356 #define EFSYS_MEM_PREFETCH(_esmp, _offset) \
358 volatile uint8_t *_base = (_esmp)->esm_base; \
360 rte_prefetch0(_base + (_offset)); \
366 typedef struct efsys_bar_s {
367 rte_spinlock_t esb_lock;
369 struct rte_pci_device *esb_dev;
371 * Ideally it should have volatile qualifier to denote that
372 * the memory may be updated by someone else. However, it adds
373 * qualifier discard warnings when the pointer or its derivative
374 * is passed to memset() or rte_mov16().
375 * So, skip the qualifier here, but make sure that it is added
376 * below in access macros.
381 #define SFC_BAR_LOCK_INIT(_esbp, _ifname) \
383 rte_spinlock_init(&(_esbp)->esb_lock); \
384 _NOTE(CONSTANTCONDITION); \
386 #define SFC_BAR_LOCK_DESTROY(_esbp) ((void)0)
387 #define SFC_BAR_LOCK(_esbp) rte_spinlock_lock(&(_esbp)->esb_lock)
388 #define SFC_BAR_UNLOCK(_esbp) rte_spinlock_unlock(&(_esbp)->esb_lock)
390 #define EFSYS_BAR_READD(_esbp, _offset, _edp, _lock) \
392 volatile uint8_t *_base = (_esbp)->esb_base; \
393 volatile uint32_t *_addr; \
395 _NOTE(CONSTANTCONDITION); \
396 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_dword_t))); \
397 _NOTE(CONSTANTCONDITION); \
399 SFC_BAR_LOCK(_esbp); \
401 _addr = (volatile uint32_t *)(_base + (_offset)); \
403 (_edp)->ed_u32[0] = rte_read32_relaxed(_addr); \
405 EFSYS_PROBE2(bar_readd, unsigned int, (_offset), \
406 uint32_t, (_edp)->ed_u32[0]); \
408 _NOTE(CONSTANTCONDITION); \
410 SFC_BAR_UNLOCK(_esbp); \
411 _NOTE(CONSTANTCONDITION); \
414 #define EFSYS_BAR_READQ(_esbp, _offset, _eqp) \
416 volatile uint8_t *_base = (_esbp)->esb_base; \
417 volatile uint64_t *_addr; \
419 _NOTE(CONSTANTCONDITION); \
420 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_qword_t))); \
422 SFC_BAR_LOCK(_esbp); \
424 _addr = (volatile uint64_t *)(_base + (_offset)); \
426 (_eqp)->eq_u64[0] = rte_read64_relaxed(_addr); \
428 EFSYS_PROBE3(bar_readq, unsigned int, (_offset), \
429 uint32_t, (_eqp)->eq_u32[1], \
430 uint32_t, (_eqp)->eq_u32[0]); \
432 SFC_BAR_UNLOCK(_esbp); \
433 _NOTE(CONSTANTCONDITION); \
436 #define EFSYS_BAR_READO(_esbp, _offset, _eop, _lock) \
438 volatile uint8_t *_base = (_esbp)->esb_base; \
439 volatile __m128i *_addr; \
441 _NOTE(CONSTANTCONDITION); \
442 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_oword_t))); \
444 _NOTE(CONSTANTCONDITION); \
446 SFC_BAR_LOCK(_esbp); \
448 _addr = (volatile __m128i *)(_base + (_offset)); \
450 /* There is no rte_read128_relaxed() yet */ \
451 (_eop)->eo_u128[0] = _addr[0]; \
453 EFSYS_PROBE5(bar_reado, unsigned int, (_offset), \
454 uint32_t, (_eop)->eo_u32[3], \
455 uint32_t, (_eop)->eo_u32[2], \
456 uint32_t, (_eop)->eo_u32[1], \
457 uint32_t, (_eop)->eo_u32[0]); \
459 _NOTE(CONSTANTCONDITION); \
461 SFC_BAR_UNLOCK(_esbp); \
462 _NOTE(CONSTANTCONDITION); \
466 #define EFSYS_BAR_WRITED(_esbp, _offset, _edp, _lock) \
468 volatile uint8_t *_base = (_esbp)->esb_base; \
469 volatile uint32_t *_addr; \
471 _NOTE(CONSTANTCONDITION); \
472 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_dword_t))); \
474 _NOTE(CONSTANTCONDITION); \
476 SFC_BAR_LOCK(_esbp); \
478 EFSYS_PROBE2(bar_writed, unsigned int, (_offset), \
479 uint32_t, (_edp)->ed_u32[0]); \
481 _addr = (volatile uint32_t *)(_base + (_offset)); \
482 rte_write32_relaxed((_edp)->ed_u32[0], _addr); \
485 _NOTE(CONSTANTCONDITION); \
487 SFC_BAR_UNLOCK(_esbp); \
488 _NOTE(CONSTANTCONDITION); \
491 #define EFSYS_BAR_WRITEQ(_esbp, _offset, _eqp) \
493 volatile uint8_t *_base = (_esbp)->esb_base; \
494 volatile uint64_t *_addr; \
496 _NOTE(CONSTANTCONDITION); \
497 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_qword_t))); \
499 SFC_BAR_LOCK(_esbp); \
501 EFSYS_PROBE3(bar_writeq, unsigned int, (_offset), \
502 uint32_t, (_eqp)->eq_u32[1], \
503 uint32_t, (_eqp)->eq_u32[0]); \
505 _addr = (volatile uint64_t *)(_base + (_offset)); \
506 rte_write64_relaxed((_eqp)->eq_u64[0], _addr); \
509 SFC_BAR_UNLOCK(_esbp); \
510 _NOTE(CONSTANTCONDITION); \
514 * Guarantees 64bit aligned 64bit writes to write combined BAR mapping
515 * (required by PIO hardware).
517 * Neither VFIO, nor UIO, nor NIC UIO (on FreeBSD) support
518 * write-combined memory mapped to user-land, so just abort if used.
520 #define EFSYS_BAR_WC_WRITEQ(_esbp, _offset, _eqp) \
522 rte_panic("Write-combined BAR access not supported"); \
525 #define EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock) \
527 volatile uint8_t *_base = (_esbp)->esb_base; \
528 volatile __m128i *_addr; \
530 _NOTE(CONSTANTCONDITION); \
531 SFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_oword_t))); \
533 _NOTE(CONSTANTCONDITION); \
535 SFC_BAR_LOCK(_esbp); \
537 EFSYS_PROBE5(bar_writeo, unsigned int, (_offset), \
538 uint32_t, (_eop)->eo_u32[3], \
539 uint32_t, (_eop)->eo_u32[2], \
540 uint32_t, (_eop)->eo_u32[1], \
541 uint32_t, (_eop)->eo_u32[0]); \
543 _addr = (volatile __m128i *)(_base + (_offset)); \
544 /* There is no rte_write128_relaxed() yet */ \
545 _addr[0] = (_eop)->eo_u128[0]; \
548 _NOTE(CONSTANTCONDITION); \
550 SFC_BAR_UNLOCK(_esbp); \
551 _NOTE(CONSTANTCONDITION); \
554 /* Use the standard octo-word write for doorbell writes */
555 #define EFSYS_BAR_DOORBELL_WRITEO(_esbp, _offset, _eop) \
557 EFSYS_BAR_WRITEO((_esbp), (_offset), (_eop), B_FALSE); \
558 _NOTE(CONSTANTCONDITION); \
563 #define EFSYS_SPIN(_us) \
566 _NOTE(CONSTANTCONDITION); \
569 #define EFSYS_SLEEP EFSYS_SPIN
573 #define EFSYS_MEM_READ_BARRIER() rte_rmb()
574 #define EFSYS_PIO_WRITE_BARRIER() rte_io_wmb()
579 * DPDK does not provide any DMA syncing API, and no PMD drivers
580 * have any traces of explicit DMA syncing.
581 * DMA mapping is assumed to be coherent.
584 #define EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size) ((void)0)
586 /* Just avoid store and compiler (impliciltly) reordering */
587 #define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) rte_wmb()
591 typedef uint64_t efsys_timestamp_t;
593 #define EFSYS_TIMESTAMP(_usp) \
595 *(_usp) = rte_get_timer_cycles() * 1000000 / \
596 rte_get_timer_hz(); \
597 _NOTE(CONSTANTCONDITION); \
602 #define EFSYS_KMEM_ALLOC(_esip, _size, _p) \
605 (_p) = rte_zmalloc("sfc", (_size), 0); \
606 _NOTE(CONSTANTCONDITION); \
609 #define EFSYS_KMEM_FREE(_esip, _size, _p) \
614 _NOTE(CONSTANTCONDITION); \
619 typedef rte_spinlock_t efsys_lock_t;
621 #define SFC_EFSYS_LOCK_INIT(_eslp, _ifname, _label) \
622 rte_spinlock_init((_eslp))
623 #define SFC_EFSYS_LOCK_DESTROY(_eslp) ((void)0)
624 #define SFC_EFSYS_LOCK(_eslp) \
625 rte_spinlock_lock((_eslp))
626 #define SFC_EFSYS_UNLOCK(_eslp) \
627 rte_spinlock_unlock((_eslp))
628 #define SFC_EFSYS_LOCK_ASSERT_OWNED(_eslp) \
629 SFC_ASSERT(rte_spinlock_is_locked((_eslp)))
631 typedef int efsys_lock_state_t;
633 #define EFSYS_LOCK_MAGIC 0x000010c4
635 #define EFSYS_LOCK(_lockp, _state) \
637 SFC_EFSYS_LOCK(_lockp); \
638 (_state) = EFSYS_LOCK_MAGIC; \
639 _NOTE(CONSTANTCONDITION); \
642 #define EFSYS_UNLOCK(_lockp, _state) \
644 SFC_ASSERT((_state) == EFSYS_LOCK_MAGIC); \
645 SFC_EFSYS_UNLOCK(_lockp); \
646 _NOTE(CONSTANTCONDITION); \
651 typedef uint64_t efsys_stat_t;
653 #define EFSYS_STAT_INCR(_knp, _delta) \
655 *(_knp) += (_delta); \
656 _NOTE(CONSTANTCONDITION); \
659 #define EFSYS_STAT_DECR(_knp, _delta) \
661 *(_knp) -= (_delta); \
662 _NOTE(CONSTANTCONDITION); \
665 #define EFSYS_STAT_SET(_knp, _val) \
668 _NOTE(CONSTANTCONDITION); \
671 #define EFSYS_STAT_SET_QWORD(_knp, _valp) \
673 *(_knp) = rte_le_to_cpu_64((_valp)->eq_u64[0]); \
674 _NOTE(CONSTANTCONDITION); \
677 #define EFSYS_STAT_SET_DWORD(_knp, _valp) \
679 *(_knp) = rte_le_to_cpu_32((_valp)->ed_u32[0]); \
680 _NOTE(CONSTANTCONDITION); \
683 #define EFSYS_STAT_INCR_QWORD(_knp, _valp) \
685 *(_knp) += rte_le_to_cpu_64((_valp)->eq_u64[0]); \
686 _NOTE(CONSTANTCONDITION); \
689 #define EFSYS_STAT_SUBR_QWORD(_knp, _valp) \
691 *(_knp) -= rte_le_to_cpu_64((_valp)->eq_u64[0]); \
692 _NOTE(CONSTANTCONDITION); \
697 #if EFSYS_OPT_DECODE_INTR_FATAL
698 #define EFSYS_ERR(_esip, _code, _dword0, _dword1) \
701 SFC_GENERIC_LOG(ERR, "FATAL ERROR #%u (0x%08x%08x)", \
702 (_code), (_dword0), (_dword1)); \
703 _NOTE(CONSTANTCONDITION); \
709 /* RTE_VERIFY from DPDK treats expressions with % operator incorrectly,
710 * so we re-implement it here
712 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
713 #define EFSYS_ASSERT(_exp) \
715 if (unlikely(!(_exp))) \
716 rte_panic("line %d\tassert \"%s\" failed\n", \
717 __LINE__, (#_exp)); \
720 #define EFSYS_ASSERT(_exp) (void)(_exp)
723 #define EFSYS_ASSERT3(_x, _op, _y, _t) EFSYS_ASSERT((_t)(_x) _op (_t)(_y))
725 #define EFSYS_ASSERT3U(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uint64_t)
726 #define EFSYS_ASSERT3S(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, int64_t)
727 #define EFSYS_ASSERT3P(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uintptr_t)
731 #define EFSYS_HAS_ROTL_DWORD 0
737 #endif /* _SFC_COMMON_EFSYS_H */