2 * Copyright (c) 2016 Solarflare Communications Inc.
5 * This software was jointly developed between OKTET Labs (under contract
6 * for Solarflare) and Solarflare Communications, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
27 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <rte_errno.h>
45 sfc_dma_alloc(const struct sfc_adapter *sa, const char *name, uint16_t id,
46 size_t len, int socket_id, efsys_mem_t *esmp)
48 const struct rte_memzone *mz;
50 sfc_log_init(sa, "name=%s id=%u len=%lu socket_id=%d",
51 name, id, len, socket_id);
53 mz = rte_eth_dma_zone_reserve(sa->eth_dev, name, id, len,
54 sysconf(_SC_PAGESIZE), socket_id);
56 sfc_err(sa, "cannot reserve DMA zone for %s:%u %#x@%d: %s",
57 name, (unsigned int)id, (unsigned int)len, socket_id,
58 rte_strerror(rte_errno));
62 esmp->esm_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
63 if (esmp->esm_addr == RTE_BAD_PHYS_ADDR) {
64 (void)rte_memzone_free(mz);
69 esmp->esm_base = mz->addr;
75 sfc_dma_free(const struct sfc_adapter *sa, efsys_mem_t *esmp)
79 sfc_log_init(sa, "name=%s", esmp->esm_mz->name);
81 rc = rte_memzone_free(esmp->esm_mz);
83 sfc_err(sa, "rte_memzone_free(() failed: %d", rc);
85 memset(esmp, 0, sizeof(*esmp));
89 sfc_phy_cap_from_link_speeds(uint32_t speeds)
91 uint32_t phy_caps = 0;
93 if (~speeds & ETH_LINK_SPEED_FIXED) {
94 phy_caps |= (1 << EFX_PHY_CAP_AN);
96 * If no speeds are specified in the mask, any supported
99 if (speeds == ETH_LINK_SPEED_AUTONEG)
101 (1 << EFX_PHY_CAP_1000FDX) |
102 (1 << EFX_PHY_CAP_10000FDX) |
103 (1 << EFX_PHY_CAP_40000FDX);
105 if (speeds & ETH_LINK_SPEED_1G)
106 phy_caps |= (1 << EFX_PHY_CAP_1000FDX);
107 if (speeds & ETH_LINK_SPEED_10G)
108 phy_caps |= (1 << EFX_PHY_CAP_10000FDX);
109 if (speeds & ETH_LINK_SPEED_40G)
110 phy_caps |= (1 << EFX_PHY_CAP_40000FDX);
116 * Check requested device level configuration.
117 * Receive and transmit configuration is checked in corresponding
121 sfc_check_conf(struct sfc_adapter *sa)
123 const struct rte_eth_conf *conf = &sa->eth_dev->data->dev_conf;
126 sa->port.phy_adv_cap =
127 sfc_phy_cap_from_link_speeds(conf->link_speeds) &
128 sa->port.phy_adv_cap_mask;
129 if ((sa->port.phy_adv_cap & ~(1 << EFX_PHY_CAP_AN)) == 0) {
130 sfc_err(sa, "No link speeds from mask %#x are supported",
135 if (conf->lpbk_mode != 0) {
136 sfc_err(sa, "Loopback not supported");
140 if (conf->dcb_capability_en != 0) {
141 sfc_err(sa, "Priority-based flow control not supported");
145 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
146 sfc_err(sa, "Flow Director not supported");
150 if ((conf->intr_conf.lsc != 0) &&
151 (sa->intr.type != EFX_INTR_LINE) &&
152 (sa->intr.type != EFX_INTR_MESSAGE)) {
153 sfc_err(sa, "Link status change interrupt not supported");
157 if (conf->intr_conf.rxq != 0) {
158 sfc_err(sa, "Receive queue interrupt not supported");
166 * Find out maximum number of receive and transmit queues which could be
169 * NIC is kept initialized on success to allow other modules acquire
170 * defaults and capabilities.
173 sfc_estimate_resource_limits(struct sfc_adapter *sa)
175 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
176 efx_drv_limits_t limits;
178 uint32_t evq_allocated;
179 uint32_t rxq_allocated;
180 uint32_t txq_allocated;
182 memset(&limits, 0, sizeof(limits));
184 /* Request at least one Rx and Tx queue */
185 limits.edl_min_rxq_count = 1;
186 limits.edl_min_txq_count = 1;
187 /* Management event queue plus event queue for each Tx and Rx queue */
188 limits.edl_min_evq_count =
189 1 + limits.edl_min_rxq_count + limits.edl_min_txq_count;
191 /* Divide by number of functions to guarantee that all functions
192 * will get promised resources
194 /* FIXME Divide by number of functions (not 2) below */
195 limits.edl_max_evq_count = encp->enc_evq_limit / 2;
196 SFC_ASSERT(limits.edl_max_evq_count >= limits.edl_min_rxq_count);
198 /* Split equally between receive and transmit */
199 limits.edl_max_rxq_count =
200 MIN(encp->enc_rxq_limit, (limits.edl_max_evq_count - 1) / 2);
201 SFC_ASSERT(limits.edl_max_rxq_count >= limits.edl_min_rxq_count);
203 limits.edl_max_txq_count =
204 MIN(encp->enc_txq_limit,
205 limits.edl_max_evq_count - 1 - limits.edl_max_rxq_count);
208 limits.edl_max_txq_count =
209 MIN(limits.edl_max_txq_count,
210 encp->enc_fw_assisted_tso_v2_n_contexts /
211 encp->enc_hw_pf_count);
213 SFC_ASSERT(limits.edl_max_txq_count >= limits.edl_min_rxq_count);
215 /* Configure the minimum required resources needed for the
216 * driver to operate, and the maximum desired resources that the
217 * driver is capable of using.
219 efx_nic_set_drv_limits(sa->nic, &limits);
221 sfc_log_init(sa, "init nic");
222 rc = efx_nic_init(sa->nic);
226 /* Find resource dimensions assigned by firmware to this function */
227 rc = efx_nic_get_vi_pool(sa->nic, &evq_allocated, &rxq_allocated,
230 goto fail_get_vi_pool;
232 /* It still may allocate more than maximum, ensure limit */
233 evq_allocated = MIN(evq_allocated, limits.edl_max_evq_count);
234 rxq_allocated = MIN(rxq_allocated, limits.edl_max_rxq_count);
235 txq_allocated = MIN(txq_allocated, limits.edl_max_txq_count);
237 /* Subtract management EVQ not used for traffic */
238 SFC_ASSERT(evq_allocated > 0);
241 /* Right now we use separate EVQ for Rx and Tx */
242 sa->rxq_max = MIN(rxq_allocated, evq_allocated / 2);
243 sa->txq_max = MIN(txq_allocated, evq_allocated - sa->rxq_max);
245 /* Keep NIC initialized */
250 efx_nic_fini(sa->nic);
255 sfc_set_drv_limits(struct sfc_adapter *sa)
257 const struct rte_eth_dev_data *data = sa->eth_dev->data;
258 efx_drv_limits_t lim;
260 memset(&lim, 0, sizeof(lim));
262 /* Limits are strict since take into account initial estimation */
263 lim.edl_min_evq_count = lim.edl_max_evq_count =
264 1 + data->nb_rx_queues + data->nb_tx_queues;
265 lim.edl_min_rxq_count = lim.edl_max_rxq_count = data->nb_rx_queues;
266 lim.edl_min_txq_count = lim.edl_max_txq_count = data->nb_tx_queues;
268 return efx_nic_set_drv_limits(sa->nic, &lim);
272 sfc_start(struct sfc_adapter *sa)
276 sfc_log_init(sa, "entry");
278 SFC_ASSERT(sfc_adapter_is_locked(sa));
281 case SFC_ADAPTER_CONFIGURED:
283 case SFC_ADAPTER_STARTED:
284 sfc_info(sa, "already started");
291 sa->state = SFC_ADAPTER_STARTING;
293 sfc_log_init(sa, "set resource limits");
294 rc = sfc_set_drv_limits(sa);
296 goto fail_set_drv_limits;
298 sfc_log_init(sa, "init nic");
299 rc = efx_nic_init(sa->nic);
303 rc = sfc_intr_start(sa);
305 goto fail_intr_start;
307 rc = sfc_ev_start(sa);
311 rc = sfc_port_start(sa);
313 goto fail_port_start;
315 rc = sfc_rx_start(sa);
319 rc = sfc_tx_start(sa);
323 sa->state = SFC_ADAPTER_STARTED;
324 sfc_log_init(sa, "done");
340 efx_nic_fini(sa->nic);
344 sa->state = SFC_ADAPTER_CONFIGURED;
346 sfc_log_init(sa, "failed %d", rc);
351 sfc_stop(struct sfc_adapter *sa)
353 sfc_log_init(sa, "entry");
355 SFC_ASSERT(sfc_adapter_is_locked(sa));
358 case SFC_ADAPTER_STARTED:
360 case SFC_ADAPTER_CONFIGURED:
361 sfc_info(sa, "already stopped");
364 sfc_err(sa, "stop in unexpected state %u", sa->state);
369 sa->state = SFC_ADAPTER_STOPPING;
376 efx_nic_fini(sa->nic);
378 sa->state = SFC_ADAPTER_CONFIGURED;
379 sfc_log_init(sa, "done");
383 sfc_configure(struct sfc_adapter *sa)
387 sfc_log_init(sa, "entry");
389 SFC_ASSERT(sfc_adapter_is_locked(sa));
391 SFC_ASSERT(sa->state == SFC_ADAPTER_INITIALIZED);
392 sa->state = SFC_ADAPTER_CONFIGURING;
394 rc = sfc_check_conf(sa);
396 goto fail_check_conf;
398 rc = sfc_intr_init(sa);
402 rc = sfc_ev_init(sa);
406 rc = sfc_port_init(sa);
410 rc = sfc_rx_init(sa);
414 rc = sfc_tx_init(sa);
418 sa->state = SFC_ADAPTER_CONFIGURED;
419 sfc_log_init(sa, "done");
436 sa->state = SFC_ADAPTER_INITIALIZED;
437 sfc_log_init(sa, "failed %d", rc);
442 sfc_close(struct sfc_adapter *sa)
444 sfc_log_init(sa, "entry");
446 SFC_ASSERT(sfc_adapter_is_locked(sa));
448 SFC_ASSERT(sa->state == SFC_ADAPTER_CONFIGURED);
449 sa->state = SFC_ADAPTER_CLOSING;
457 sa->state = SFC_ADAPTER_INITIALIZED;
458 sfc_log_init(sa, "done");
462 sfc_mem_bar_init(struct sfc_adapter *sa)
464 struct rte_eth_dev *eth_dev = sa->eth_dev;
465 struct rte_pci_device *pci_dev = SFC_DEV_TO_PCI(eth_dev);
466 efsys_bar_t *ebp = &sa->mem_bar;
468 struct rte_mem_resource *res;
470 for (i = 0; i < RTE_DIM(pci_dev->mem_resource); i++) {
471 res = &pci_dev->mem_resource[i];
472 if ((res->len != 0) && (res->phys_addr != 0)) {
473 /* Found first memory BAR */
474 SFC_BAR_LOCK_INIT(ebp, eth_dev->data->name);
476 ebp->esb_dev = pci_dev;
477 ebp->esb_base = res->addr;
486 sfc_mem_bar_fini(struct sfc_adapter *sa)
488 efsys_bar_t *ebp = &sa->mem_bar;
490 SFC_BAR_LOCK_DESTROY(ebp);
491 memset(ebp, 0, sizeof(*ebp));
494 #if EFSYS_OPT_RX_SCALE
496 * A fixed RSS key which has a property of being symmetric
497 * (symmetrical flows are distributed to the same CPU)
498 * and also known to give a uniform distribution
499 * (a good distribution of traffic between different CPUs)
501 static const uint8_t default_rss_key[SFC_RSS_KEY_SIZE] = {
502 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
503 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
504 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
505 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
506 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
511 sfc_set_rss_defaults(struct sfc_adapter *sa)
513 #if EFSYS_OPT_RX_SCALE
516 rc = efx_intr_init(sa->nic, sa->intr.type, NULL);
520 rc = efx_ev_init(sa->nic);
524 rc = efx_rx_init(sa->nic);
528 rc = efx_rx_scale_support_get(sa->nic, &sa->rss_support);
530 goto fail_scale_support_get;
532 rc = efx_rx_hash_support_get(sa->nic, &sa->hash_support);
534 goto fail_hash_support_get;
536 efx_rx_fini(sa->nic);
537 efx_ev_fini(sa->nic);
538 efx_intr_fini(sa->nic);
540 sa->rss_hash_types = sfc_rte_to_efx_hash_type(SFC_RSS_OFFLOADS);
542 rte_memcpy(sa->rss_key, default_rss_key, sizeof(sa->rss_key));
546 fail_hash_support_get:
547 fail_scale_support_get:
549 efx_ev_fini(sa->nic);
552 efx_intr_fini(sa->nic);
562 sfc_attach(struct sfc_adapter *sa)
564 struct rte_pci_device *pci_dev = SFC_DEV_TO_PCI(sa->eth_dev);
565 const efx_nic_cfg_t *encp;
569 sfc_log_init(sa, "entry");
571 SFC_ASSERT(sfc_adapter_is_locked(sa));
573 sa->socket_id = rte_socket_id();
575 sfc_log_init(sa, "init mem bar");
576 rc = sfc_mem_bar_init(sa);
578 goto fail_mem_bar_init;
580 sfc_log_init(sa, "get family");
581 rc = efx_family(pci_dev->id.vendor_id, pci_dev->id.device_id,
585 sfc_log_init(sa, "family is %u", sa->family);
587 sfc_log_init(sa, "create nic");
588 rte_spinlock_init(&sa->nic_lock);
589 rc = efx_nic_create(sa->family, (efsys_identifier_t *)sa,
590 &sa->mem_bar, &sa->nic_lock, &enp);
592 goto fail_nic_create;
595 rc = sfc_mcdi_init(sa);
599 sfc_log_init(sa, "probe nic");
600 rc = efx_nic_probe(enp);
604 efx_mcdi_new_epoch(enp);
606 sfc_log_init(sa, "reset nic");
607 rc = efx_nic_reset(enp);
611 encp = efx_nic_cfg_get(sa->nic);
613 sa->tso = encp->enc_fw_assisted_tso_v2_enabled;
615 sfc_warn(sa, "TSO support isn't available on this adapter");
617 sfc_log_init(sa, "estimate resource limits");
618 rc = sfc_estimate_resource_limits(sa);
620 goto fail_estimate_rsrc_limits;
622 sa->txq_max_entries = encp->enc_txq_max_ndescs;
623 SFC_ASSERT(rte_is_power_of_2(sa->txq_max_entries));
625 rc = sfc_intr_attach(sa);
627 goto fail_intr_attach;
629 efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_PERM,
630 &sa->port.phy_adv_cap_mask);
632 rc = sfc_set_rss_defaults(sa);
634 goto fail_set_rss_defaults;
636 sfc_log_init(sa, "fini nic");
639 sa->state = SFC_ADAPTER_INITIALIZED;
641 sfc_log_init(sa, "done");
644 fail_set_rss_defaults:
648 efx_nic_fini(sa->nic);
650 fail_estimate_rsrc_limits:
652 sfc_log_init(sa, "unprobe nic");
653 efx_nic_unprobe(enp);
659 sfc_log_init(sa, "destroy nic");
661 efx_nic_destroy(enp);
665 sfc_mem_bar_fini(sa);
668 sfc_log_init(sa, "failed %d", rc);
673 sfc_detach(struct sfc_adapter *sa)
675 efx_nic_t *enp = sa->nic;
677 sfc_log_init(sa, "entry");
679 SFC_ASSERT(sfc_adapter_is_locked(sa));
683 sfc_log_init(sa, "unprobe nic");
684 efx_nic_unprobe(enp);
688 sfc_log_init(sa, "destroy nic");
690 efx_nic_destroy(enp);
692 sfc_mem_bar_fini(sa);
694 sa->state = SFC_ADAPTER_UNINITIALIZED;