2 * Copyright (c) 2016 Solarflare Communications Inc.
5 * This software was jointly developed between OKTET Labs (under contract
6 * for Solarflare) and Solarflare Communications, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
27 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <rte_errno.h>
45 sfc_dma_alloc(const struct sfc_adapter *sa, const char *name, uint16_t id,
46 size_t len, int socket_id, efsys_mem_t *esmp)
48 const struct rte_memzone *mz;
50 sfc_log_init(sa, "name=%s id=%u len=%lu socket_id=%d",
51 name, id, len, socket_id);
53 mz = rte_eth_dma_zone_reserve(sa->eth_dev, name, id, len,
54 sysconf(_SC_PAGESIZE), socket_id);
56 sfc_err(sa, "cannot reserve DMA zone for %s:%u %#x@%d: %s",
57 name, (unsigned int)id, (unsigned int)len, socket_id,
58 rte_strerror(rte_errno));
62 esmp->esm_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
63 if (esmp->esm_addr == RTE_BAD_PHYS_ADDR) {
64 (void)rte_memzone_free(mz);
69 esmp->esm_base = mz->addr;
75 sfc_dma_free(const struct sfc_adapter *sa, efsys_mem_t *esmp)
79 sfc_log_init(sa, "name=%s", esmp->esm_mz->name);
81 rc = rte_memzone_free(esmp->esm_mz);
83 sfc_err(sa, "rte_memzone_free(() failed: %d", rc);
85 memset(esmp, 0, sizeof(*esmp));
89 sfc_phy_cap_from_link_speeds(uint32_t speeds)
91 uint32_t phy_caps = 0;
93 if (~speeds & ETH_LINK_SPEED_FIXED) {
94 phy_caps |= (1 << EFX_PHY_CAP_AN);
96 * If no speeds are specified in the mask, any supported
99 if (speeds == ETH_LINK_SPEED_AUTONEG)
101 (1 << EFX_PHY_CAP_1000FDX) |
102 (1 << EFX_PHY_CAP_10000FDX) |
103 (1 << EFX_PHY_CAP_40000FDX);
105 if (speeds & ETH_LINK_SPEED_1G)
106 phy_caps |= (1 << EFX_PHY_CAP_1000FDX);
107 if (speeds & ETH_LINK_SPEED_10G)
108 phy_caps |= (1 << EFX_PHY_CAP_10000FDX);
109 if (speeds & ETH_LINK_SPEED_40G)
110 phy_caps |= (1 << EFX_PHY_CAP_40000FDX);
116 * Check requested device level configuration.
117 * Receive and transmit configuration is checked in corresponding
121 sfc_check_conf(struct sfc_adapter *sa)
123 const struct rte_eth_conf *conf = &sa->eth_dev->data->dev_conf;
126 sa->port.phy_adv_cap =
127 sfc_phy_cap_from_link_speeds(conf->link_speeds) &
128 sa->port.phy_adv_cap_mask;
129 if ((sa->port.phy_adv_cap & ~(1 << EFX_PHY_CAP_AN)) == 0) {
130 sfc_err(sa, "No link speeds from mask %#x are supported",
135 if (conf->lpbk_mode != 0) {
136 sfc_err(sa, "Loopback not supported");
140 if (conf->dcb_capability_en != 0) {
141 sfc_err(sa, "Priority-based flow control not supported");
145 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
146 sfc_err(sa, "Flow Director not supported");
150 if ((conf->intr_conf.lsc != 0) &&
151 (sa->intr.type != EFX_INTR_LINE) &&
152 (sa->intr.type != EFX_INTR_MESSAGE)) {
153 sfc_err(sa, "Link status change interrupt not supported");
157 if (conf->intr_conf.rxq != 0) {
158 sfc_err(sa, "Receive queue interrupt not supported");
166 * Find out maximum number of receive and transmit queues which could be
169 * NIC is kept initialized on success to allow other modules acquire
170 * defaults and capabilities.
173 sfc_estimate_resource_limits(struct sfc_adapter *sa)
175 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
176 efx_drv_limits_t limits;
178 uint32_t evq_allocated;
179 uint32_t rxq_allocated;
180 uint32_t txq_allocated;
182 memset(&limits, 0, sizeof(limits));
184 /* Request at least one Rx and Tx queue */
185 limits.edl_min_rxq_count = 1;
186 limits.edl_min_txq_count = 1;
187 /* Management event queue plus event queue for each Tx and Rx queue */
188 limits.edl_min_evq_count =
189 1 + limits.edl_min_rxq_count + limits.edl_min_txq_count;
191 /* Divide by number of functions to guarantee that all functions
192 * will get promised resources
194 /* FIXME Divide by number of functions (not 2) below */
195 limits.edl_max_evq_count = encp->enc_evq_limit / 2;
196 SFC_ASSERT(limits.edl_max_evq_count >= limits.edl_min_rxq_count);
198 /* Split equally between receive and transmit */
199 limits.edl_max_rxq_count =
200 MIN(encp->enc_rxq_limit, (limits.edl_max_evq_count - 1) / 2);
201 SFC_ASSERT(limits.edl_max_rxq_count >= limits.edl_min_rxq_count);
203 limits.edl_max_txq_count =
204 MIN(encp->enc_txq_limit,
205 limits.edl_max_evq_count - 1 - limits.edl_max_rxq_count);
206 SFC_ASSERT(limits.edl_max_txq_count >= limits.edl_min_rxq_count);
208 /* Configure the minimum required resources needed for the
209 * driver to operate, and the maximum desired resources that the
210 * driver is capable of using.
212 efx_nic_set_drv_limits(sa->nic, &limits);
214 sfc_log_init(sa, "init nic");
215 rc = efx_nic_init(sa->nic);
219 /* Find resource dimensions assigned by firmware to this function */
220 rc = efx_nic_get_vi_pool(sa->nic, &evq_allocated, &rxq_allocated,
223 goto fail_get_vi_pool;
225 /* It still may allocate more than maximum, ensure limit */
226 evq_allocated = MIN(evq_allocated, limits.edl_max_evq_count);
227 rxq_allocated = MIN(rxq_allocated, limits.edl_max_rxq_count);
228 txq_allocated = MIN(txq_allocated, limits.edl_max_txq_count);
230 /* Subtract management EVQ not used for traffic */
231 SFC_ASSERT(evq_allocated > 0);
234 /* Right now we use separate EVQ for Rx and Tx */
235 sa->rxq_max = MIN(rxq_allocated, evq_allocated / 2);
236 sa->txq_max = MIN(txq_allocated, evq_allocated - sa->rxq_max);
238 /* Keep NIC initialized */
243 efx_nic_fini(sa->nic);
248 sfc_set_drv_limits(struct sfc_adapter *sa)
250 const struct rte_eth_dev_data *data = sa->eth_dev->data;
251 efx_drv_limits_t lim;
253 memset(&lim, 0, sizeof(lim));
255 /* Limits are strict since take into account initial estimation */
256 lim.edl_min_evq_count = lim.edl_max_evq_count =
257 1 + data->nb_rx_queues + data->nb_tx_queues;
258 lim.edl_min_rxq_count = lim.edl_max_rxq_count = data->nb_rx_queues;
259 lim.edl_min_txq_count = lim.edl_max_txq_count = data->nb_tx_queues;
261 return efx_nic_set_drv_limits(sa->nic, &lim);
265 sfc_start(struct sfc_adapter *sa)
269 sfc_log_init(sa, "entry");
271 SFC_ASSERT(sfc_adapter_is_locked(sa));
274 case SFC_ADAPTER_CONFIGURED:
276 case SFC_ADAPTER_STARTED:
277 sfc_info(sa, "already started");
284 sa->state = SFC_ADAPTER_STARTING;
286 sfc_log_init(sa, "set resource limits");
287 rc = sfc_set_drv_limits(sa);
289 goto fail_set_drv_limits;
291 sfc_log_init(sa, "init nic");
292 rc = efx_nic_init(sa->nic);
296 rc = sfc_intr_start(sa);
298 goto fail_intr_start;
300 rc = sfc_ev_start(sa);
304 rc = sfc_port_start(sa);
306 goto fail_port_start;
308 rc = sfc_rx_start(sa);
312 rc = sfc_tx_start(sa);
316 sa->state = SFC_ADAPTER_STARTED;
317 sfc_log_init(sa, "done");
333 efx_nic_fini(sa->nic);
337 sa->state = SFC_ADAPTER_CONFIGURED;
339 sfc_log_init(sa, "failed %d", rc);
344 sfc_stop(struct sfc_adapter *sa)
346 sfc_log_init(sa, "entry");
348 SFC_ASSERT(sfc_adapter_is_locked(sa));
351 case SFC_ADAPTER_STARTED:
353 case SFC_ADAPTER_CONFIGURED:
354 sfc_info(sa, "already stopped");
357 sfc_err(sa, "stop in unexpected state %u", sa->state);
362 sa->state = SFC_ADAPTER_STOPPING;
369 efx_nic_fini(sa->nic);
371 sa->state = SFC_ADAPTER_CONFIGURED;
372 sfc_log_init(sa, "done");
376 sfc_configure(struct sfc_adapter *sa)
380 sfc_log_init(sa, "entry");
382 SFC_ASSERT(sfc_adapter_is_locked(sa));
384 SFC_ASSERT(sa->state == SFC_ADAPTER_INITIALIZED);
385 sa->state = SFC_ADAPTER_CONFIGURING;
387 rc = sfc_check_conf(sa);
389 goto fail_check_conf;
391 rc = sfc_intr_init(sa);
395 rc = sfc_ev_init(sa);
399 rc = sfc_port_init(sa);
403 rc = sfc_rx_init(sa);
407 rc = sfc_tx_init(sa);
411 sa->state = SFC_ADAPTER_CONFIGURED;
412 sfc_log_init(sa, "done");
429 sa->state = SFC_ADAPTER_INITIALIZED;
430 sfc_log_init(sa, "failed %d", rc);
435 sfc_close(struct sfc_adapter *sa)
437 sfc_log_init(sa, "entry");
439 SFC_ASSERT(sfc_adapter_is_locked(sa));
441 SFC_ASSERT(sa->state == SFC_ADAPTER_CONFIGURED);
442 sa->state = SFC_ADAPTER_CLOSING;
450 sa->state = SFC_ADAPTER_INITIALIZED;
451 sfc_log_init(sa, "done");
455 sfc_mem_bar_init(struct sfc_adapter *sa)
457 struct rte_eth_dev *eth_dev = sa->eth_dev;
458 struct rte_pci_device *pci_dev = SFC_DEV_TO_PCI(eth_dev);
459 efsys_bar_t *ebp = &sa->mem_bar;
461 struct rte_mem_resource *res;
463 for (i = 0; i < RTE_DIM(pci_dev->mem_resource); i++) {
464 res = &pci_dev->mem_resource[i];
465 if ((res->len != 0) && (res->phys_addr != 0)) {
466 /* Found first memory BAR */
467 SFC_BAR_LOCK_INIT(ebp, eth_dev->data->name);
469 ebp->esb_dev = pci_dev;
470 ebp->esb_base = res->addr;
479 sfc_mem_bar_fini(struct sfc_adapter *sa)
481 efsys_bar_t *ebp = &sa->mem_bar;
483 SFC_BAR_LOCK_DESTROY(ebp);
484 memset(ebp, 0, sizeof(*ebp));
487 #if EFSYS_OPT_RX_SCALE
489 * A fixed RSS key which has a property of being symmetric
490 * (symmetrical flows are distributed to the same CPU)
491 * and also known to give a uniform distribution
492 * (a good distribution of traffic between different CPUs)
494 static const uint8_t default_rss_key[SFC_RSS_KEY_SIZE] = {
495 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
496 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
497 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
498 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
499 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
504 sfc_set_rss_defaults(struct sfc_adapter *sa)
506 #if EFSYS_OPT_RX_SCALE
509 rc = efx_intr_init(sa->nic, sa->intr.type, NULL);
513 rc = efx_ev_init(sa->nic);
517 rc = efx_rx_init(sa->nic);
521 rc = efx_rx_scale_support_get(sa->nic, &sa->rss_support);
523 goto fail_scale_support_get;
525 rc = efx_rx_hash_support_get(sa->nic, &sa->hash_support);
527 goto fail_hash_support_get;
529 efx_rx_fini(sa->nic);
530 efx_ev_fini(sa->nic);
531 efx_intr_fini(sa->nic);
533 sa->rss_hash_types = sfc_rte_to_efx_hash_type(SFC_RSS_OFFLOADS);
535 rte_memcpy(sa->rss_key, default_rss_key, sizeof(sa->rss_key));
539 fail_hash_support_get:
540 fail_scale_support_get:
542 efx_ev_fini(sa->nic);
545 efx_intr_fini(sa->nic);
555 sfc_attach(struct sfc_adapter *sa)
557 struct rte_pci_device *pci_dev = SFC_DEV_TO_PCI(sa->eth_dev);
558 const efx_nic_cfg_t *encp;
562 sfc_log_init(sa, "entry");
564 SFC_ASSERT(sfc_adapter_is_locked(sa));
566 sa->socket_id = rte_socket_id();
568 sfc_log_init(sa, "init mem bar");
569 rc = sfc_mem_bar_init(sa);
571 goto fail_mem_bar_init;
573 sfc_log_init(sa, "get family");
574 rc = efx_family(pci_dev->id.vendor_id, pci_dev->id.device_id,
578 sfc_log_init(sa, "family is %u", sa->family);
580 sfc_log_init(sa, "create nic");
581 rte_spinlock_init(&sa->nic_lock);
582 rc = efx_nic_create(sa->family, (efsys_identifier_t *)sa,
583 &sa->mem_bar, &sa->nic_lock, &enp);
585 goto fail_nic_create;
588 rc = sfc_mcdi_init(sa);
592 sfc_log_init(sa, "probe nic");
593 rc = efx_nic_probe(enp);
597 efx_mcdi_new_epoch(enp);
599 sfc_log_init(sa, "reset nic");
600 rc = efx_nic_reset(enp);
604 sfc_log_init(sa, "estimate resource limits");
605 rc = sfc_estimate_resource_limits(sa);
607 goto fail_estimate_rsrc_limits;
609 encp = efx_nic_cfg_get(sa->nic);
610 sa->txq_max_entries = encp->enc_txq_max_ndescs;
611 SFC_ASSERT(rte_is_power_of_2(sa->txq_max_entries));
613 rc = sfc_intr_attach(sa);
615 goto fail_intr_attach;
617 efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_PERM,
618 &sa->port.phy_adv_cap_mask);
620 rc = sfc_set_rss_defaults(sa);
622 goto fail_set_rss_defaults;
624 sfc_log_init(sa, "fini nic");
627 sa->state = SFC_ADAPTER_INITIALIZED;
629 sfc_log_init(sa, "done");
632 fail_set_rss_defaults:
636 efx_nic_fini(sa->nic);
638 fail_estimate_rsrc_limits:
640 sfc_log_init(sa, "unprobe nic");
641 efx_nic_unprobe(enp);
647 sfc_log_init(sa, "destroy nic");
649 efx_nic_destroy(enp);
653 sfc_mem_bar_fini(sa);
656 sfc_log_init(sa, "failed %d", rc);
661 sfc_detach(struct sfc_adapter *sa)
663 efx_nic_t *enp = sa->nic;
665 sfc_log_init(sa, "entry");
667 SFC_ASSERT(sfc_adapter_is_locked(sa));
671 sfc_log_init(sa, "unprobe nic");
672 efx_nic_unprobe(enp);
676 sfc_log_init(sa, "destroy nic");
678 efx_nic_destroy(enp);
680 sfc_mem_bar_fini(sa);
682 sa->state = SFC_ADAPTER_UNINITIALIZED;