1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2016-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
13 #include <rte_errno.h>
14 #include <rte_alarm.h>
19 #include "sfc_debug.h"
23 #include "sfc_mae_counter.h"
25 #include "sfc_kvargs.h"
26 #include "sfc_tweak.h"
30 sfc_dma_alloc(const struct sfc_adapter *sa, const char *name, uint16_t id,
31 size_t len, int socket_id, efsys_mem_t *esmp)
33 const struct rte_memzone *mz;
35 sfc_log_init(sa, "name=%s id=%u len=%zu socket_id=%d",
36 name, id, len, socket_id);
38 mz = rte_eth_dma_zone_reserve(sa->eth_dev, name, id, len,
39 sysconf(_SC_PAGESIZE), socket_id);
41 sfc_err(sa, "cannot reserve DMA zone for %s:%u %#x@%d: %s",
42 name, (unsigned int)id, (unsigned int)len, socket_id,
43 rte_strerror(rte_errno));
47 esmp->esm_addr = mz->iova;
48 if (esmp->esm_addr == RTE_BAD_IOVA) {
49 (void)rte_memzone_free(mz);
54 esmp->esm_base = mz->addr;
57 "DMA name=%s id=%u len=%lu socket_id=%d => virt=%p iova=%lx",
58 name, id, len, socket_id, esmp->esm_base,
59 (unsigned long)esmp->esm_addr);
65 sfc_dma_free(const struct sfc_adapter *sa, efsys_mem_t *esmp)
69 sfc_log_init(sa, "name=%s", esmp->esm_mz->name);
71 rc = rte_memzone_free(esmp->esm_mz);
73 sfc_err(sa, "rte_memzone_free(() failed: %d", rc);
75 memset(esmp, 0, sizeof(*esmp));
79 sfc_phy_cap_from_link_speeds(uint32_t speeds)
81 uint32_t phy_caps = 0;
83 if (~speeds & ETH_LINK_SPEED_FIXED) {
84 phy_caps |= (1 << EFX_PHY_CAP_AN);
86 * If no speeds are specified in the mask, any supported
89 if (speeds == ETH_LINK_SPEED_AUTONEG)
91 (1 << EFX_PHY_CAP_1000FDX) |
92 (1 << EFX_PHY_CAP_10000FDX) |
93 (1 << EFX_PHY_CAP_25000FDX) |
94 (1 << EFX_PHY_CAP_40000FDX) |
95 (1 << EFX_PHY_CAP_50000FDX) |
96 (1 << EFX_PHY_CAP_100000FDX);
98 if (speeds & ETH_LINK_SPEED_1G)
99 phy_caps |= (1 << EFX_PHY_CAP_1000FDX);
100 if (speeds & ETH_LINK_SPEED_10G)
101 phy_caps |= (1 << EFX_PHY_CAP_10000FDX);
102 if (speeds & ETH_LINK_SPEED_25G)
103 phy_caps |= (1 << EFX_PHY_CAP_25000FDX);
104 if (speeds & ETH_LINK_SPEED_40G)
105 phy_caps |= (1 << EFX_PHY_CAP_40000FDX);
106 if (speeds & ETH_LINK_SPEED_50G)
107 phy_caps |= (1 << EFX_PHY_CAP_50000FDX);
108 if (speeds & ETH_LINK_SPEED_100G)
109 phy_caps |= (1 << EFX_PHY_CAP_100000FDX);
115 * Check requested device level configuration.
116 * Receive and transmit configuration is checked in corresponding
120 sfc_check_conf(struct sfc_adapter *sa)
122 const struct rte_eth_conf *conf = &sa->eth_dev->data->dev_conf;
125 sa->port.phy_adv_cap =
126 sfc_phy_cap_from_link_speeds(conf->link_speeds) &
127 sa->port.phy_adv_cap_mask;
128 if ((sa->port.phy_adv_cap & ~(1 << EFX_PHY_CAP_AN)) == 0) {
129 sfc_err(sa, "No link speeds from mask %#x are supported",
134 #if !EFSYS_OPT_LOOPBACK
135 if (conf->lpbk_mode != 0) {
136 sfc_err(sa, "Loopback not supported");
141 if (conf->dcb_capability_en != 0) {
142 sfc_err(sa, "Priority-based flow control not supported");
146 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
147 sfc_err(sa, "Flow Director not supported");
151 if ((conf->intr_conf.lsc != 0) &&
152 (sa->intr.type != EFX_INTR_LINE) &&
153 (sa->intr.type != EFX_INTR_MESSAGE)) {
154 sfc_err(sa, "Link status change interrupt not supported");
158 if (conf->intr_conf.rxq != 0 &&
159 (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_INTR) == 0) {
160 sfc_err(sa, "Receive queue interrupt not supported");
168 * Find out maximum number of receive and transmit queues which could be
171 * NIC is kept initialized on success to allow other modules acquire
172 * defaults and capabilities.
175 sfc_estimate_resource_limits(struct sfc_adapter *sa)
177 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
178 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
179 efx_drv_limits_t limits;
181 uint32_t evq_allocated;
182 uint32_t rxq_allocated;
183 uint32_t txq_allocated;
185 memset(&limits, 0, sizeof(limits));
187 /* Request at least one Rx and Tx queue */
188 limits.edl_min_rxq_count = 1;
189 limits.edl_min_txq_count = 1;
190 /* Management event queue plus event queue for each Tx and Rx queue */
191 limits.edl_min_evq_count =
192 1 + limits.edl_min_rxq_count + limits.edl_min_txq_count;
194 /* Divide by number of functions to guarantee that all functions
195 * will get promised resources
197 /* FIXME Divide by number of functions (not 2) below */
198 limits.edl_max_evq_count = encp->enc_evq_limit / 2;
199 SFC_ASSERT(limits.edl_max_evq_count >= limits.edl_min_rxq_count);
201 /* Split equally between receive and transmit */
202 limits.edl_max_rxq_count =
203 MIN(encp->enc_rxq_limit, (limits.edl_max_evq_count - 1) / 2);
204 SFC_ASSERT(limits.edl_max_rxq_count >= limits.edl_min_rxq_count);
206 limits.edl_max_txq_count =
207 MIN(encp->enc_txq_limit,
208 limits.edl_max_evq_count - 1 - limits.edl_max_rxq_count);
210 if (sa->tso && encp->enc_fw_assisted_tso_v2_enabled)
211 limits.edl_max_txq_count =
212 MIN(limits.edl_max_txq_count,
213 encp->enc_fw_assisted_tso_v2_n_contexts /
214 encp->enc_hw_pf_count);
216 SFC_ASSERT(limits.edl_max_txq_count >= limits.edl_min_rxq_count);
218 /* Configure the minimum required resources needed for the
219 * driver to operate, and the maximum desired resources that the
220 * driver is capable of using.
222 efx_nic_set_drv_limits(sa->nic, &limits);
224 sfc_log_init(sa, "init nic");
225 rc = efx_nic_init(sa->nic);
229 /* Find resource dimensions assigned by firmware to this function */
230 rc = efx_nic_get_vi_pool(sa->nic, &evq_allocated, &rxq_allocated,
233 goto fail_get_vi_pool;
235 /* It still may allocate more than maximum, ensure limit */
236 evq_allocated = MIN(evq_allocated, limits.edl_max_evq_count);
237 rxq_allocated = MIN(rxq_allocated, limits.edl_max_rxq_count);
238 txq_allocated = MIN(txq_allocated, limits.edl_max_txq_count);
241 * Subtract management EVQ not used for traffic
242 * The resource allocation strategy is as follows:
243 * - one EVQ for management
244 * - one EVQ for each ethdev RXQ
245 * - one EVQ for each ethdev TXQ
246 * - one EVQ and one RXQ for optional MAE counters.
248 if (evq_allocated == 0) {
249 sfc_err(sa, "count of allocated EvQ is 0");
251 goto fail_allocate_evq;
256 * Reserve absolutely required minimum.
257 * Right now we use separate EVQ for Rx and Tx.
259 if (rxq_allocated > 0 && evq_allocated > 0) {
264 if (txq_allocated > 0 && evq_allocated > 0) {
270 if (sfc_mae_counter_rxq_required(sa) &&
271 rxq_allocated > 0 && evq_allocated > 0) {
274 sas->counters_rxq_allocated = true;
276 sas->counters_rxq_allocated = false;
279 /* Add remaining allocated queues */
280 sa->rxq_max += MIN(rxq_allocated, evq_allocated / 2);
281 sa->txq_max += MIN(txq_allocated, evq_allocated - sa->rxq_max);
283 /* Keep NIC initialized */
288 efx_nic_fini(sa->nic);
294 sfc_set_drv_limits(struct sfc_adapter *sa)
296 const struct rte_eth_dev_data *data = sa->eth_dev->data;
297 uint32_t rxq_reserved = sfc_nb_reserved_rxq(sfc_sa2shared(sa));
298 efx_drv_limits_t lim;
300 memset(&lim, 0, sizeof(lim));
303 * Limits are strict since take into account initial estimation.
304 * Resource allocation stategy is described in
305 * sfc_estimate_resource_limits().
307 lim.edl_min_evq_count = lim.edl_max_evq_count =
308 1 + data->nb_rx_queues + data->nb_tx_queues + rxq_reserved;
309 lim.edl_min_rxq_count = lim.edl_max_rxq_count =
310 data->nb_rx_queues + rxq_reserved;
311 lim.edl_min_txq_count = lim.edl_max_txq_count = data->nb_tx_queues;
313 return efx_nic_set_drv_limits(sa->nic, &lim);
317 sfc_set_fw_subvariant(struct sfc_adapter *sa)
319 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
320 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
321 uint64_t tx_offloads = sa->eth_dev->data->dev_conf.txmode.offloads;
322 unsigned int txq_index;
323 efx_nic_fw_subvariant_t req_fw_subvariant;
324 efx_nic_fw_subvariant_t cur_fw_subvariant;
327 if (!encp->enc_fw_subvariant_no_tx_csum_supported) {
328 sfc_info(sa, "no-Tx-checksum subvariant not supported");
332 for (txq_index = 0; txq_index < sas->txq_count; ++txq_index) {
333 struct sfc_txq_info *txq_info = &sas->txq_info[txq_index];
335 if (txq_info->state & SFC_TXQ_INITIALIZED)
336 tx_offloads |= txq_info->offloads;
339 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
340 DEV_TX_OFFLOAD_TCP_CKSUM |
341 DEV_TX_OFFLOAD_UDP_CKSUM |
342 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM))
343 req_fw_subvariant = EFX_NIC_FW_SUBVARIANT_DEFAULT;
345 req_fw_subvariant = EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM;
347 rc = efx_nic_get_fw_subvariant(sa->nic, &cur_fw_subvariant);
349 sfc_err(sa, "failed to get FW subvariant: %d", rc);
352 sfc_info(sa, "FW subvariant is %u vs required %u",
353 cur_fw_subvariant, req_fw_subvariant);
355 if (cur_fw_subvariant == req_fw_subvariant)
358 rc = efx_nic_set_fw_subvariant(sa->nic, req_fw_subvariant);
360 sfc_err(sa, "failed to set FW subvariant %u: %d",
361 req_fw_subvariant, rc);
364 sfc_info(sa, "FW subvariant set to %u", req_fw_subvariant);
370 sfc_try_start(struct sfc_adapter *sa)
372 const efx_nic_cfg_t *encp;
375 sfc_log_init(sa, "entry");
377 SFC_ASSERT(sfc_adapter_is_locked(sa));
378 SFC_ASSERT(sa->state == SFC_ADAPTER_STARTING);
380 sfc_log_init(sa, "set FW subvariant");
381 rc = sfc_set_fw_subvariant(sa);
383 goto fail_set_fw_subvariant;
385 sfc_log_init(sa, "set resource limits");
386 rc = sfc_set_drv_limits(sa);
388 goto fail_set_drv_limits;
390 sfc_log_init(sa, "init nic");
391 rc = efx_nic_init(sa->nic);
395 encp = efx_nic_cfg_get(sa->nic);
398 * Refresh (since it may change on NIC reset/restart) a copy of
399 * supported tunnel encapsulations in shared memory to be used
400 * on supported Rx packet type classes get.
402 sa->priv.shared->tunnel_encaps =
403 encp->enc_tunnel_encapsulations_supported;
405 if (encp->enc_tunnel_encapsulations_supported != 0) {
406 sfc_log_init(sa, "apply tunnel config");
407 rc = efx_tunnel_reconfigure(sa->nic);
409 goto fail_tunnel_reconfigure;
412 rc = sfc_intr_start(sa);
414 goto fail_intr_start;
416 rc = sfc_ev_start(sa);
420 rc = sfc_port_start(sa);
422 goto fail_port_start;
424 rc = sfc_rx_start(sa);
428 rc = sfc_tx_start(sa);
432 rc = sfc_flow_start(sa);
434 goto fail_flows_insert;
436 sfc_log_init(sa, "done");
455 fail_tunnel_reconfigure:
456 efx_nic_fini(sa->nic);
460 fail_set_fw_subvariant:
461 sfc_log_init(sa, "failed %d", rc);
466 sfc_start(struct sfc_adapter *sa)
468 unsigned int start_tries = 3;
471 sfc_log_init(sa, "entry");
473 SFC_ASSERT(sfc_adapter_is_locked(sa));
476 case SFC_ADAPTER_CONFIGURED:
478 case SFC_ADAPTER_STARTED:
479 sfc_notice(sa, "already started");
486 sa->state = SFC_ADAPTER_STARTING;
491 * FIXME Try to recreate vSwitch on start retry.
492 * vSwitch is absent after MC reboot like events and
493 * we should recreate it. May be we need proper
494 * indication instead of guessing.
497 sfc_sriov_vswitch_destroy(sa);
498 rc = sfc_sriov_vswitch_create(sa);
500 goto fail_sriov_vswitch_create;
502 rc = sfc_try_start(sa);
503 } while ((--start_tries > 0) &&
504 (rc == EIO || rc == EAGAIN || rc == ENOENT || rc == EINVAL));
509 sa->state = SFC_ADAPTER_STARTED;
510 sfc_log_init(sa, "done");
514 fail_sriov_vswitch_create:
515 sa->state = SFC_ADAPTER_CONFIGURED;
517 sfc_log_init(sa, "failed %d", rc);
522 sfc_stop(struct sfc_adapter *sa)
524 sfc_log_init(sa, "entry");
526 SFC_ASSERT(sfc_adapter_is_locked(sa));
529 case SFC_ADAPTER_STARTED:
531 case SFC_ADAPTER_CONFIGURED:
532 sfc_notice(sa, "already stopped");
535 sfc_err(sa, "stop in unexpected state %u", sa->state);
540 sa->state = SFC_ADAPTER_STOPPING;
548 efx_nic_fini(sa->nic);
550 sa->state = SFC_ADAPTER_CONFIGURED;
551 sfc_log_init(sa, "done");
555 sfc_restart(struct sfc_adapter *sa)
559 SFC_ASSERT(sfc_adapter_is_locked(sa));
561 if (sa->state != SFC_ADAPTER_STARTED)
568 sfc_err(sa, "restart failed");
574 sfc_restart_if_required(void *arg)
576 struct sfc_adapter *sa = arg;
578 /* If restart is scheduled, clear the flag and do it */
579 if (rte_atomic32_cmpset((volatile uint32_t *)&sa->restart_required,
581 sfc_adapter_lock(sa);
582 if (sa->state == SFC_ADAPTER_STARTED)
583 (void)sfc_restart(sa);
584 sfc_adapter_unlock(sa);
589 sfc_schedule_restart(struct sfc_adapter *sa)
593 /* Schedule restart alarm if it is not scheduled yet */
594 if (!rte_atomic32_test_and_set(&sa->restart_required))
597 rc = rte_eal_alarm_set(1, sfc_restart_if_required, sa);
599 sfc_warn(sa, "alarms are not supported, restart is pending");
601 sfc_err(sa, "cannot arm restart alarm (rc=%d)", rc);
603 sfc_notice(sa, "restart scheduled");
607 sfc_configure(struct sfc_adapter *sa)
611 sfc_log_init(sa, "entry");
613 SFC_ASSERT(sfc_adapter_is_locked(sa));
615 SFC_ASSERT(sa->state == SFC_ADAPTER_INITIALIZED ||
616 sa->state == SFC_ADAPTER_CONFIGURED);
617 sa->state = SFC_ADAPTER_CONFIGURING;
619 rc = sfc_check_conf(sa);
621 goto fail_check_conf;
623 rc = sfc_intr_configure(sa);
625 goto fail_intr_configure;
627 rc = sfc_port_configure(sa);
629 goto fail_port_configure;
631 rc = sfc_rx_configure(sa);
633 goto fail_rx_configure;
635 rc = sfc_tx_configure(sa);
637 goto fail_tx_configure;
639 sa->state = SFC_ADAPTER_CONFIGURED;
640 sfc_log_init(sa, "done");
654 sa->state = SFC_ADAPTER_INITIALIZED;
655 sfc_log_init(sa, "failed %d", rc);
660 sfc_close(struct sfc_adapter *sa)
662 sfc_log_init(sa, "entry");
664 SFC_ASSERT(sfc_adapter_is_locked(sa));
666 SFC_ASSERT(sa->state == SFC_ADAPTER_CONFIGURED);
667 sa->state = SFC_ADAPTER_CLOSING;
674 sa->state = SFC_ADAPTER_INITIALIZED;
675 sfc_log_init(sa, "done");
679 sfc_mem_bar_init(struct sfc_adapter *sa, const efx_bar_region_t *mem_ebrp)
681 struct rte_eth_dev *eth_dev = sa->eth_dev;
682 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
683 efsys_bar_t *ebp = &sa->mem_bar;
684 struct rte_mem_resource *res =
685 &pci_dev->mem_resource[mem_ebrp->ebr_index];
687 SFC_BAR_LOCK_INIT(ebp, eth_dev->data->name);
688 ebp->esb_rid = mem_ebrp->ebr_index;
689 ebp->esb_dev = pci_dev;
690 ebp->esb_base = res->addr;
692 sa->fcw_offset = mem_ebrp->ebr_offset;
698 sfc_mem_bar_fini(struct sfc_adapter *sa)
700 efsys_bar_t *ebp = &sa->mem_bar;
702 SFC_BAR_LOCK_DESTROY(ebp);
703 memset(ebp, 0, sizeof(*ebp));
707 * A fixed RSS key which has a property of being symmetric
708 * (symmetrical flows are distributed to the same CPU)
709 * and also known to give a uniform distribution
710 * (a good distribution of traffic between different CPUs)
712 static const uint8_t default_rss_key[EFX_RSS_KEY_SIZE] = {
713 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
714 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
715 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
716 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
717 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
721 sfc_rss_attach(struct sfc_adapter *sa)
723 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
726 rc = efx_intr_init(sa->nic, sa->intr.type, NULL);
730 rc = efx_ev_init(sa->nic);
734 rc = efx_rx_init(sa->nic);
738 rc = efx_rx_scale_default_support_get(sa->nic, &rss->context_type);
740 goto fail_scale_support_get;
742 rc = efx_rx_hash_default_support_get(sa->nic, &rss->hash_support);
744 goto fail_hash_support_get;
746 rc = sfc_rx_hash_init(sa);
748 goto fail_rx_hash_init;
750 efx_rx_fini(sa->nic);
751 efx_ev_fini(sa->nic);
752 efx_intr_fini(sa->nic);
754 rte_memcpy(rss->key, default_rss_key, sizeof(rss->key));
755 rss->dummy_rss_context = EFX_RSS_CONTEXT_DEFAULT;
760 fail_hash_support_get:
761 fail_scale_support_get:
762 efx_rx_fini(sa->nic);
765 efx_ev_fini(sa->nic);
768 efx_intr_fini(sa->nic);
775 sfc_rss_detach(struct sfc_adapter *sa)
777 sfc_rx_hash_fini(sa);
781 sfc_attach(struct sfc_adapter *sa)
783 const efx_nic_cfg_t *encp;
784 efx_nic_t *enp = sa->nic;
787 sfc_log_init(sa, "entry");
789 SFC_ASSERT(sfc_adapter_is_locked(sa));
791 efx_mcdi_new_epoch(enp);
793 sfc_log_init(sa, "reset nic");
794 rc = efx_nic_reset(enp);
798 rc = sfc_sriov_attach(sa);
800 goto fail_sriov_attach;
803 * Probed NIC is sufficient for tunnel init.
804 * Initialize tunnel support to be able to use libefx
805 * efx_tunnel_config_udp_{add,remove}() in any state and
806 * efx_tunnel_reconfigure() on start up.
808 rc = efx_tunnel_init(enp);
810 goto fail_tunnel_init;
812 encp = efx_nic_cfg_get(sa->nic);
815 * Make a copy of supported tunnel encapsulations in shared
816 * memory to be used on supported Rx packet type classes get.
818 sa->priv.shared->tunnel_encaps =
819 encp->enc_tunnel_encapsulations_supported;
821 if (sfc_dp_tx_offload_capa(sa->priv.dp_tx) & DEV_TX_OFFLOAD_TCP_TSO) {
822 sa->tso = encp->enc_fw_assisted_tso_v2_enabled ||
823 encp->enc_tso_v3_enabled;
825 sfc_info(sa, "TSO support isn't available on this adapter");
829 (sfc_dp_tx_offload_capa(sa->priv.dp_tx) &
830 (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
831 DEV_TX_OFFLOAD_GENEVE_TNL_TSO)) != 0) {
832 sa->tso_encap = encp->enc_fw_assisted_tso_v2_encap_enabled ||
833 encp->enc_tso_v3_enabled;
835 sfc_info(sa, "Encapsulated TSO support isn't available on this adapter");
838 sfc_log_init(sa, "estimate resource limits");
839 rc = sfc_estimate_resource_limits(sa);
841 goto fail_estimate_rsrc_limits;
843 sa->evq_max_entries = encp->enc_evq_max_nevs;
844 SFC_ASSERT(rte_is_power_of_2(sa->evq_max_entries));
846 sa->evq_min_entries = encp->enc_evq_min_nevs;
847 SFC_ASSERT(rte_is_power_of_2(sa->evq_min_entries));
849 sa->rxq_max_entries = encp->enc_rxq_max_ndescs;
850 SFC_ASSERT(rte_is_power_of_2(sa->rxq_max_entries));
852 sa->rxq_min_entries = encp->enc_rxq_min_ndescs;
853 SFC_ASSERT(rte_is_power_of_2(sa->rxq_min_entries));
855 sa->txq_max_entries = encp->enc_txq_max_ndescs;
856 SFC_ASSERT(rte_is_power_of_2(sa->txq_max_entries));
858 sa->txq_min_entries = encp->enc_txq_min_ndescs;
859 SFC_ASSERT(rte_is_power_of_2(sa->txq_min_entries));
861 rc = sfc_intr_attach(sa);
863 goto fail_intr_attach;
865 rc = sfc_ev_attach(sa);
869 rc = sfc_port_attach(sa);
871 goto fail_port_attach;
873 rc = sfc_rss_attach(sa);
875 goto fail_rss_attach;
877 rc = sfc_filter_attach(sa);
879 goto fail_filter_attach;
881 rc = sfc_mae_counter_rxq_attach(sa);
883 goto fail_mae_counter_rxq_attach;
885 rc = sfc_mae_attach(sa);
887 goto fail_mae_attach;
889 sfc_log_init(sa, "fini nic");
895 * Create vSwitch to be able to use VFs when PF is not started yet
896 * as DPDK port. VFs should be able to talk to each other even
899 rc = sfc_sriov_vswitch_create(sa);
901 goto fail_sriov_vswitch_create;
903 sa->state = SFC_ADAPTER_INITIALIZED;
905 sfc_log_init(sa, "done");
908 fail_sriov_vswitch_create:
913 sfc_mae_counter_rxq_detach(sa);
915 fail_mae_counter_rxq_attach:
916 sfc_filter_detach(sa);
931 efx_nic_fini(sa->nic);
933 fail_estimate_rsrc_limits:
935 efx_tunnel_fini(sa->nic);
936 sfc_sriov_detach(sa);
941 sfc_log_init(sa, "failed %d", rc);
946 sfc_detach(struct sfc_adapter *sa)
948 sfc_log_init(sa, "entry");
950 SFC_ASSERT(sfc_adapter_is_locked(sa));
952 sfc_sriov_vswitch_destroy(sa);
957 sfc_mae_counter_rxq_detach(sa);
958 sfc_filter_detach(sa);
963 efx_tunnel_fini(sa->nic);
964 sfc_sriov_detach(sa);
966 sa->state = SFC_ADAPTER_UNINITIALIZED;
970 sfc_kvarg_fv_variant_handler(__rte_unused const char *key,
971 const char *value_str, void *opaque)
973 uint32_t *value = opaque;
975 if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_DONT_CARE) == 0)
976 *value = EFX_FW_VARIANT_DONT_CARE;
977 else if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_FULL_FEATURED) == 0)
978 *value = EFX_FW_VARIANT_FULL_FEATURED;
979 else if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_LOW_LATENCY) == 0)
980 *value = EFX_FW_VARIANT_LOW_LATENCY;
981 else if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_PACKED_STREAM) == 0)
982 *value = EFX_FW_VARIANT_PACKED_STREAM;
983 else if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_DPDK) == 0)
984 *value = EFX_FW_VARIANT_DPDK;
992 sfc_get_fw_variant(struct sfc_adapter *sa, efx_fw_variant_t *efv)
994 efx_nic_fw_info_t enfi;
997 rc = efx_nic_get_fw_version(sa->nic, &enfi);
1000 else if (!enfi.enfi_dpcpu_fw_ids_valid)
1004 * Firmware variant can be uniquely identified by the RxDPCPU
1007 switch (enfi.enfi_rx_dpcpu_fw_id) {
1008 case EFX_RXDP_FULL_FEATURED_FW_ID:
1009 *efv = EFX_FW_VARIANT_FULL_FEATURED;
1012 case EFX_RXDP_LOW_LATENCY_FW_ID:
1013 *efv = EFX_FW_VARIANT_LOW_LATENCY;
1016 case EFX_RXDP_PACKED_STREAM_FW_ID:
1017 *efv = EFX_FW_VARIANT_PACKED_STREAM;
1020 case EFX_RXDP_DPDK_FW_ID:
1021 *efv = EFX_FW_VARIANT_DPDK;
1026 * Other firmware variants are not considered, since they are
1027 * not supported in the device parameters
1029 *efv = EFX_FW_VARIANT_DONT_CARE;
1037 sfc_fw_variant2str(efx_fw_variant_t efv)
1040 case EFX_RXDP_FULL_FEATURED_FW_ID:
1041 return SFC_KVARG_FW_VARIANT_FULL_FEATURED;
1042 case EFX_RXDP_LOW_LATENCY_FW_ID:
1043 return SFC_KVARG_FW_VARIANT_LOW_LATENCY;
1044 case EFX_RXDP_PACKED_STREAM_FW_ID:
1045 return SFC_KVARG_FW_VARIANT_PACKED_STREAM;
1046 case EFX_RXDP_DPDK_FW_ID:
1047 return SFC_KVARG_FW_VARIANT_DPDK;
1054 sfc_kvarg_rxd_wait_timeout_ns(struct sfc_adapter *sa)
1059 value = SFC_RXD_WAIT_TIMEOUT_NS_DEF;
1061 rc = sfc_kvargs_process(sa, SFC_KVARG_RXD_WAIT_TIMEOUT_NS,
1062 sfc_kvarg_long_handler, &value);
1067 (unsigned long)value > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
1068 sfc_err(sa, "wrong '" SFC_KVARG_RXD_WAIT_TIMEOUT_NS "' "
1069 "was set (%ld);", value);
1070 sfc_err(sa, "it must not be less than 0 or greater than %u",
1071 EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX);
1075 sa->rxd_wait_timeout_ns = value;
1080 sfc_nic_probe(struct sfc_adapter *sa)
1082 efx_nic_t *enp = sa->nic;
1083 efx_fw_variant_t preferred_efv;
1084 efx_fw_variant_t efv;
1087 preferred_efv = EFX_FW_VARIANT_DONT_CARE;
1088 rc = sfc_kvargs_process(sa, SFC_KVARG_FW_VARIANT,
1089 sfc_kvarg_fv_variant_handler,
1092 sfc_err(sa, "invalid %s parameter value", SFC_KVARG_FW_VARIANT);
1096 rc = sfc_kvarg_rxd_wait_timeout_ns(sa);
1100 rc = efx_nic_probe(enp, preferred_efv);
1102 /* Unprivileged functions cannot set FW variant */
1103 rc = efx_nic_probe(enp, EFX_FW_VARIANT_DONT_CARE);
1108 rc = sfc_get_fw_variant(sa, &efv);
1109 if (rc == ENOTSUP) {
1110 sfc_warn(sa, "FW variant can not be obtained");
1116 /* Check that firmware variant was changed to the requested one */
1117 if (preferred_efv != EFX_FW_VARIANT_DONT_CARE && preferred_efv != efv) {
1118 sfc_warn(sa, "FW variant has not changed to the requested %s",
1119 sfc_fw_variant2str(preferred_efv));
1122 sfc_notice(sa, "running FW variant is %s", sfc_fw_variant2str(efv));
1128 sfc_probe(struct sfc_adapter *sa)
1130 efx_bar_region_t mem_ebrp;
1131 struct rte_eth_dev *eth_dev = sa->eth_dev;
1132 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1136 sfc_log_init(sa, "entry");
1138 SFC_ASSERT(sfc_adapter_is_locked(sa));
1140 sa->socket_id = rte_socket_id();
1141 rte_atomic32_init(&sa->restart_required);
1143 sfc_log_init(sa, "get family");
1144 rc = sfc_efx_family(pci_dev, &mem_ebrp, &sa->family);
1149 "family is %u, membar is %u, function control window offset is %lu",
1150 sa->family, mem_ebrp.ebr_index, mem_ebrp.ebr_offset);
1152 sfc_log_init(sa, "init mem bar");
1153 rc = sfc_mem_bar_init(sa, &mem_ebrp);
1155 goto fail_mem_bar_init;
1157 sfc_log_init(sa, "create nic");
1158 rte_spinlock_init(&sa->nic_lock);
1159 rc = efx_nic_create(sa->family, (efsys_identifier_t *)sa,
1160 &sa->mem_bar, mem_ebrp.ebr_offset,
1161 &sa->nic_lock, &enp);
1163 goto fail_nic_create;
1166 rc = sfc_mcdi_init(sa);
1168 goto fail_mcdi_init;
1170 sfc_log_init(sa, "probe nic");
1171 rc = sfc_nic_probe(sa);
1173 goto fail_nic_probe;
1175 sfc_log_init(sa, "done");
1182 sfc_log_init(sa, "destroy nic");
1184 efx_nic_destroy(enp);
1187 sfc_mem_bar_fini(sa);
1191 sfc_log_init(sa, "failed %d", rc);
1196 sfc_unprobe(struct sfc_adapter *sa)
1198 efx_nic_t *enp = sa->nic;
1200 sfc_log_init(sa, "entry");
1202 SFC_ASSERT(sfc_adapter_is_locked(sa));
1204 sfc_log_init(sa, "unprobe nic");
1205 efx_nic_unprobe(enp);
1210 * Make sure there is no pending alarm to restart since we are
1211 * going to free device private which is passed as the callback
1212 * opaque data. A new alarm cannot be scheduled since MCDI is
1215 rte_eal_alarm_cancel(sfc_restart_if_required, sa);
1217 sfc_log_init(sa, "destroy nic");
1219 efx_nic_destroy(enp);
1221 sfc_mem_bar_fini(sa);
1224 sa->state = SFC_ADAPTER_UNINITIALIZED;
1228 sfc_register_logtype(const struct rte_pci_addr *pci_addr,
1229 const char *lt_prefix_str, uint32_t ll_default)
1231 size_t lt_prefix_str_size = strlen(lt_prefix_str);
1232 size_t lt_str_size_max;
1233 char *lt_str = NULL;
1236 if (SIZE_MAX - PCI_PRI_STR_SIZE - 1 > lt_prefix_str_size) {
1237 ++lt_prefix_str_size; /* Reserve space for prefix separator */
1238 lt_str_size_max = lt_prefix_str_size + PCI_PRI_STR_SIZE + 1;
1240 return sfc_logtype_driver;
1243 lt_str = rte_zmalloc("logtype_str", lt_str_size_max, 0);
1245 return sfc_logtype_driver;
1247 strncpy(lt_str, lt_prefix_str, lt_prefix_str_size);
1248 lt_str[lt_prefix_str_size - 1] = '.';
1249 rte_pci_device_name(pci_addr, lt_str + lt_prefix_str_size,
1250 lt_str_size_max - lt_prefix_str_size);
1251 lt_str[lt_str_size_max - 1] = '\0';
1253 ret = rte_log_register_type_and_pick_level(lt_str, ll_default);
1257 return sfc_logtype_driver;
1262 struct sfc_hw_switch_id {
1263 char board_sn[RTE_SIZEOF_FIELD(efx_nic_board_info_t, enbi_serial)];
1267 sfc_hw_switch_id_init(struct sfc_adapter *sa,
1268 struct sfc_hw_switch_id **idp)
1270 efx_nic_board_info_t board_info;
1271 struct sfc_hw_switch_id *id;
1277 id = rte_zmalloc("sfc_hw_switch_id", sizeof(*id), 0);
1281 rc = efx_nic_get_board_info(sa->nic, &board_info);
1285 memcpy(id->board_sn, board_info.enbi_serial, sizeof(id->board_sn));
1293 sfc_hw_switch_id_fini(__rte_unused struct sfc_adapter *sa,
1294 struct sfc_hw_switch_id *id)
1300 sfc_hw_switch_ids_equal(const struct sfc_hw_switch_id *left,
1301 const struct sfc_hw_switch_id *right)
1303 return strncmp(left->board_sn, right->board_sn,
1304 sizeof(left->board_sn)) == 0;