4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_errno.h>
47 sfc_dma_alloc(const struct sfc_adapter *sa, const char *name, uint16_t id,
48 size_t len, int socket_id, efsys_mem_t *esmp)
50 const struct rte_memzone *mz;
52 sfc_log_init(sa, "name=%s id=%u len=%lu socket_id=%d",
53 name, id, len, socket_id);
55 mz = rte_eth_dma_zone_reserve(sa->eth_dev, name, id, len,
56 sysconf(_SC_PAGESIZE), socket_id);
58 sfc_err(sa, "cannot reserve DMA zone for %s:%u %#x@%d: %s",
59 name, (unsigned int)id, (unsigned int)len, socket_id,
60 rte_strerror(rte_errno));
64 esmp->esm_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
65 if (esmp->esm_addr == RTE_BAD_PHYS_ADDR) {
66 (void)rte_memzone_free(mz);
71 esmp->esm_base = mz->addr;
77 sfc_dma_free(const struct sfc_adapter *sa, efsys_mem_t *esmp)
81 sfc_log_init(sa, "name=%s", esmp->esm_mz->name);
83 rc = rte_memzone_free(esmp->esm_mz);
85 sfc_err(sa, "rte_memzone_free(() failed: %d", rc);
87 memset(esmp, 0, sizeof(*esmp));
91 sfc_phy_cap_from_link_speeds(uint32_t speeds)
93 uint32_t phy_caps = 0;
95 if (~speeds & ETH_LINK_SPEED_FIXED) {
96 phy_caps |= (1 << EFX_PHY_CAP_AN);
98 * If no speeds are specified in the mask, any supported
101 if (speeds == ETH_LINK_SPEED_AUTONEG)
103 (1 << EFX_PHY_CAP_1000FDX) |
104 (1 << EFX_PHY_CAP_10000FDX) |
105 (1 << EFX_PHY_CAP_40000FDX);
107 if (speeds & ETH_LINK_SPEED_1G)
108 phy_caps |= (1 << EFX_PHY_CAP_1000FDX);
109 if (speeds & ETH_LINK_SPEED_10G)
110 phy_caps |= (1 << EFX_PHY_CAP_10000FDX);
111 if (speeds & ETH_LINK_SPEED_40G)
112 phy_caps |= (1 << EFX_PHY_CAP_40000FDX);
118 * Check requested device level configuration.
119 * Receive and transmit configuration is checked in corresponding
123 sfc_check_conf(struct sfc_adapter *sa)
125 const struct rte_eth_conf *conf = &sa->eth_dev->data->dev_conf;
128 sa->port.phy_adv_cap =
129 sfc_phy_cap_from_link_speeds(conf->link_speeds) &
130 sa->port.phy_adv_cap_mask;
131 if ((sa->port.phy_adv_cap & ~(1 << EFX_PHY_CAP_AN)) == 0) {
132 sfc_err(sa, "No link speeds from mask %#x are supported",
137 if (conf->lpbk_mode != 0) {
138 sfc_err(sa, "Loopback not supported");
142 if (conf->dcb_capability_en != 0) {
143 sfc_err(sa, "Priority-based flow control not supported");
147 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
148 sfc_err(sa, "Flow Director not supported");
152 if ((conf->intr_conf.lsc != 0) &&
153 (sa->intr.type != EFX_INTR_LINE) &&
154 (sa->intr.type != EFX_INTR_MESSAGE)) {
155 sfc_err(sa, "Link status change interrupt not supported");
159 if (conf->intr_conf.rxq != 0) {
160 sfc_err(sa, "Receive queue interrupt not supported");
168 * Find out maximum number of receive and transmit queues which could be
171 * NIC is kept initialized on success to allow other modules acquire
172 * defaults and capabilities.
175 sfc_estimate_resource_limits(struct sfc_adapter *sa)
177 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
178 efx_drv_limits_t limits;
180 uint32_t evq_allocated;
181 uint32_t rxq_allocated;
182 uint32_t txq_allocated;
184 memset(&limits, 0, sizeof(limits));
186 /* Request at least one Rx and Tx queue */
187 limits.edl_min_rxq_count = 1;
188 limits.edl_min_txq_count = 1;
189 /* Management event queue plus event queue for each Tx and Rx queue */
190 limits.edl_min_evq_count =
191 1 + limits.edl_min_rxq_count + limits.edl_min_txq_count;
193 /* Divide by number of functions to guarantee that all functions
194 * will get promised resources
196 /* FIXME Divide by number of functions (not 2) below */
197 limits.edl_max_evq_count = encp->enc_evq_limit / 2;
198 SFC_ASSERT(limits.edl_max_evq_count >= limits.edl_min_rxq_count);
200 /* Split equally between receive and transmit */
201 limits.edl_max_rxq_count =
202 MIN(encp->enc_rxq_limit, (limits.edl_max_evq_count - 1) / 2);
203 SFC_ASSERT(limits.edl_max_rxq_count >= limits.edl_min_rxq_count);
205 limits.edl_max_txq_count =
206 MIN(encp->enc_txq_limit,
207 limits.edl_max_evq_count - 1 - limits.edl_max_rxq_count);
210 limits.edl_max_txq_count =
211 MIN(limits.edl_max_txq_count,
212 encp->enc_fw_assisted_tso_v2_n_contexts /
213 encp->enc_hw_pf_count);
215 SFC_ASSERT(limits.edl_max_txq_count >= limits.edl_min_rxq_count);
217 /* Configure the minimum required resources needed for the
218 * driver to operate, and the maximum desired resources that the
219 * driver is capable of using.
221 efx_nic_set_drv_limits(sa->nic, &limits);
223 sfc_log_init(sa, "init nic");
224 rc = efx_nic_init(sa->nic);
228 /* Find resource dimensions assigned by firmware to this function */
229 rc = efx_nic_get_vi_pool(sa->nic, &evq_allocated, &rxq_allocated,
232 goto fail_get_vi_pool;
234 /* It still may allocate more than maximum, ensure limit */
235 evq_allocated = MIN(evq_allocated, limits.edl_max_evq_count);
236 rxq_allocated = MIN(rxq_allocated, limits.edl_max_rxq_count);
237 txq_allocated = MIN(txq_allocated, limits.edl_max_txq_count);
239 /* Subtract management EVQ not used for traffic */
240 SFC_ASSERT(evq_allocated > 0);
243 /* Right now we use separate EVQ for Rx and Tx */
244 sa->rxq_max = MIN(rxq_allocated, evq_allocated / 2);
245 sa->txq_max = MIN(txq_allocated, evq_allocated - sa->rxq_max);
247 /* Keep NIC initialized */
252 efx_nic_fini(sa->nic);
257 sfc_set_drv_limits(struct sfc_adapter *sa)
259 const struct rte_eth_dev_data *data = sa->eth_dev->data;
260 efx_drv_limits_t lim;
262 memset(&lim, 0, sizeof(lim));
264 /* Limits are strict since take into account initial estimation */
265 lim.edl_min_evq_count = lim.edl_max_evq_count =
266 1 + data->nb_rx_queues + data->nb_tx_queues;
267 lim.edl_min_rxq_count = lim.edl_max_rxq_count = data->nb_rx_queues;
268 lim.edl_min_txq_count = lim.edl_max_txq_count = data->nb_tx_queues;
270 return efx_nic_set_drv_limits(sa->nic, &lim);
274 sfc_start(struct sfc_adapter *sa)
278 sfc_log_init(sa, "entry");
280 SFC_ASSERT(sfc_adapter_is_locked(sa));
283 case SFC_ADAPTER_CONFIGURED:
285 case SFC_ADAPTER_STARTED:
286 sfc_info(sa, "already started");
293 sa->state = SFC_ADAPTER_STARTING;
295 sfc_log_init(sa, "set resource limits");
296 rc = sfc_set_drv_limits(sa);
298 goto fail_set_drv_limits;
300 sfc_log_init(sa, "init nic");
301 rc = efx_nic_init(sa->nic);
305 rc = sfc_intr_start(sa);
307 goto fail_intr_start;
309 rc = sfc_ev_start(sa);
313 rc = sfc_port_start(sa);
315 goto fail_port_start;
317 rc = sfc_rx_start(sa);
321 rc = sfc_tx_start(sa);
325 rc = sfc_flow_start(sa);
327 goto fail_flows_insert;
329 sa->state = SFC_ADAPTER_STARTED;
330 sfc_log_init(sa, "done");
349 efx_nic_fini(sa->nic);
353 sa->state = SFC_ADAPTER_CONFIGURED;
355 sfc_log_init(sa, "failed %d", rc);
360 sfc_stop(struct sfc_adapter *sa)
362 sfc_log_init(sa, "entry");
364 SFC_ASSERT(sfc_adapter_is_locked(sa));
367 case SFC_ADAPTER_STARTED:
369 case SFC_ADAPTER_CONFIGURED:
370 sfc_info(sa, "already stopped");
373 sfc_err(sa, "stop in unexpected state %u", sa->state);
378 sa->state = SFC_ADAPTER_STOPPING;
386 efx_nic_fini(sa->nic);
388 sa->state = SFC_ADAPTER_CONFIGURED;
389 sfc_log_init(sa, "done");
393 sfc_configure(struct sfc_adapter *sa)
397 sfc_log_init(sa, "entry");
399 SFC_ASSERT(sfc_adapter_is_locked(sa));
401 SFC_ASSERT(sa->state == SFC_ADAPTER_INITIALIZED ||
402 sa->state == SFC_ADAPTER_CONFIGURED);
403 sa->state = SFC_ADAPTER_CONFIGURING;
405 rc = sfc_check_conf(sa);
407 goto fail_check_conf;
409 rc = sfc_intr_configure(sa);
411 goto fail_intr_configure;
413 rc = sfc_port_configure(sa);
415 goto fail_port_configure;
417 rc = sfc_rx_configure(sa);
419 goto fail_rx_configure;
421 rc = sfc_tx_configure(sa);
423 goto fail_tx_configure;
425 sa->state = SFC_ADAPTER_CONFIGURED;
426 sfc_log_init(sa, "done");
440 sa->state = SFC_ADAPTER_INITIALIZED;
441 sfc_log_init(sa, "failed %d", rc);
446 sfc_close(struct sfc_adapter *sa)
448 sfc_log_init(sa, "entry");
450 SFC_ASSERT(sfc_adapter_is_locked(sa));
452 SFC_ASSERT(sa->state == SFC_ADAPTER_CONFIGURED);
453 sa->state = SFC_ADAPTER_CLOSING;
460 sa->state = SFC_ADAPTER_INITIALIZED;
461 sfc_log_init(sa, "done");
465 sfc_mem_bar_init(struct sfc_adapter *sa)
467 struct rte_eth_dev *eth_dev = sa->eth_dev;
468 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
469 efsys_bar_t *ebp = &sa->mem_bar;
471 struct rte_mem_resource *res;
473 for (i = 0; i < RTE_DIM(pci_dev->mem_resource); i++) {
474 res = &pci_dev->mem_resource[i];
475 if ((res->len != 0) && (res->phys_addr != 0)) {
476 /* Found first memory BAR */
477 SFC_BAR_LOCK_INIT(ebp, eth_dev->data->name);
479 ebp->esb_dev = pci_dev;
480 ebp->esb_base = res->addr;
489 sfc_mem_bar_fini(struct sfc_adapter *sa)
491 efsys_bar_t *ebp = &sa->mem_bar;
493 SFC_BAR_LOCK_DESTROY(ebp);
494 memset(ebp, 0, sizeof(*ebp));
497 #if EFSYS_OPT_RX_SCALE
499 * A fixed RSS key which has a property of being symmetric
500 * (symmetrical flows are distributed to the same CPU)
501 * and also known to give a uniform distribution
502 * (a good distribution of traffic between different CPUs)
504 static const uint8_t default_rss_key[EFX_RSS_KEY_SIZE] = {
505 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
506 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
507 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
508 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
509 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
513 #if EFSYS_OPT_RX_SCALE
515 sfc_set_rss_defaults(struct sfc_adapter *sa)
519 rc = efx_intr_init(sa->nic, sa->intr.type, NULL);
523 rc = efx_ev_init(sa->nic);
527 rc = efx_rx_init(sa->nic);
531 rc = efx_rx_scale_default_support_get(sa->nic, &sa->rss_support);
533 goto fail_scale_support_get;
535 rc = efx_rx_hash_default_support_get(sa->nic, &sa->hash_support);
537 goto fail_hash_support_get;
539 efx_rx_fini(sa->nic);
540 efx_ev_fini(sa->nic);
541 efx_intr_fini(sa->nic);
543 sa->rss_hash_types = sfc_rte_to_efx_hash_type(SFC_RSS_OFFLOADS);
545 rte_memcpy(sa->rss_key, default_rss_key, sizeof(sa->rss_key));
549 fail_hash_support_get:
550 fail_scale_support_get:
552 efx_ev_fini(sa->nic);
555 efx_intr_fini(sa->nic);
562 sfc_set_rss_defaults(__rte_unused struct sfc_adapter *sa)
569 sfc_attach(struct sfc_adapter *sa)
571 const efx_nic_cfg_t *encp;
572 efx_nic_t *enp = sa->nic;
575 sfc_log_init(sa, "entry");
577 SFC_ASSERT(sfc_adapter_is_locked(sa));
579 efx_mcdi_new_epoch(enp);
581 sfc_log_init(sa, "reset nic");
582 rc = efx_nic_reset(enp);
586 encp = efx_nic_cfg_get(sa->nic);
588 if (sa->dp_tx->features & SFC_DP_TX_FEAT_TSO) {
589 sa->tso = encp->enc_fw_assisted_tso_v2_enabled;
592 "TSO support isn't available on this adapter");
595 sfc_log_init(sa, "estimate resource limits");
596 rc = sfc_estimate_resource_limits(sa);
598 goto fail_estimate_rsrc_limits;
600 sa->txq_max_entries = encp->enc_txq_max_ndescs;
601 SFC_ASSERT(rte_is_power_of_2(sa->txq_max_entries));
603 rc = sfc_intr_attach(sa);
605 goto fail_intr_attach;
607 rc = sfc_ev_attach(sa);
611 rc = sfc_port_attach(sa);
613 goto fail_port_attach;
615 rc = sfc_set_rss_defaults(sa);
617 goto fail_set_rss_defaults;
619 rc = sfc_filter_attach(sa);
621 goto fail_filter_attach;
623 sfc_log_init(sa, "fini nic");
628 sa->state = SFC_ADAPTER_INITIALIZED;
630 sfc_log_init(sa, "done");
634 fail_set_rss_defaults:
644 efx_nic_fini(sa->nic);
646 fail_estimate_rsrc_limits:
649 sfc_log_init(sa, "failed %d", rc);
654 sfc_detach(struct sfc_adapter *sa)
656 sfc_log_init(sa, "entry");
658 SFC_ASSERT(sfc_adapter_is_locked(sa));
662 sfc_filter_detach(sa);
667 sa->state = SFC_ADAPTER_UNINITIALIZED;
671 sfc_probe(struct sfc_adapter *sa)
673 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(sa->eth_dev);
677 sfc_log_init(sa, "entry");
679 SFC_ASSERT(sfc_adapter_is_locked(sa));
681 sa->socket_id = rte_socket_id();
683 sfc_log_init(sa, "init mem bar");
684 rc = sfc_mem_bar_init(sa);
686 goto fail_mem_bar_init;
688 sfc_log_init(sa, "get family");
689 rc = efx_family(pci_dev->id.vendor_id, pci_dev->id.device_id,
693 sfc_log_init(sa, "family is %u", sa->family);
695 sfc_log_init(sa, "create nic");
696 rte_spinlock_init(&sa->nic_lock);
697 rc = efx_nic_create(sa->family, (efsys_identifier_t *)sa,
698 &sa->mem_bar, &sa->nic_lock, &enp);
700 goto fail_nic_create;
703 rc = sfc_mcdi_init(sa);
707 sfc_log_init(sa, "probe nic");
708 rc = efx_nic_probe(enp);
712 sfc_log_init(sa, "done");
719 sfc_log_init(sa, "destroy nic");
721 efx_nic_destroy(enp);
725 sfc_mem_bar_fini(sa);
728 sfc_log_init(sa, "failed %d", rc);
733 sfc_unprobe(struct sfc_adapter *sa)
735 efx_nic_t *enp = sa->nic;
737 sfc_log_init(sa, "entry");
739 SFC_ASSERT(sfc_adapter_is_locked(sa));
741 sfc_log_init(sa, "unprobe nic");
742 efx_nic_unprobe(enp);
746 sfc_log_init(sa, "destroy nic");
748 efx_nic_destroy(enp);
750 sfc_mem_bar_fini(sa);
753 sa->state = SFC_ADAPTER_UNINITIALIZED;