1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2016-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
13 #include <rte_errno.h>
14 #include <rte_alarm.h>
19 #include "sfc_debug.h"
23 #include "sfc_mae_counter.h"
25 #include "sfc_kvargs.h"
26 #include "sfc_tweak.h"
27 #include "sfc_sw_stats.h"
31 sfc_repr_supported(const struct sfc_adapter *sa)
37 * Representor proxy should use service lcore on PF's socket
38 * (sa->socket_id) to be efficient. But the proxy will fall back
39 * to any socket if it is not possible to get the service core
40 * on the same socket. Check that at least service core on any
41 * socket is available.
43 if (sfc_get_service_lcore(SOCKET_ID_ANY) == RTE_MAX_LCORE)
50 sfc_dma_alloc(const struct sfc_adapter *sa, const char *name, uint16_t id,
51 size_t len, int socket_id, efsys_mem_t *esmp)
53 const struct rte_memzone *mz;
55 sfc_log_init(sa, "name=%s id=%u len=%zu socket_id=%d",
56 name, id, len, socket_id);
58 mz = rte_eth_dma_zone_reserve(sa->eth_dev, name, id, len,
59 sysconf(_SC_PAGESIZE), socket_id);
61 sfc_err(sa, "cannot reserve DMA zone for %s:%u %#x@%d: %s",
62 name, (unsigned int)id, (unsigned int)len, socket_id,
63 rte_strerror(rte_errno));
67 esmp->esm_addr = mz->iova;
68 if (esmp->esm_addr == RTE_BAD_IOVA) {
69 (void)rte_memzone_free(mz);
74 esmp->esm_base = mz->addr;
77 "DMA name=%s id=%u len=%lu socket_id=%d => virt=%p iova=%lx",
78 name, id, len, socket_id, esmp->esm_base,
79 (unsigned long)esmp->esm_addr);
85 sfc_dma_free(const struct sfc_adapter *sa, efsys_mem_t *esmp)
89 sfc_log_init(sa, "name=%s", esmp->esm_mz->name);
91 rc = rte_memzone_free(esmp->esm_mz);
93 sfc_err(sa, "rte_memzone_free(() failed: %d", rc);
95 memset(esmp, 0, sizeof(*esmp));
99 sfc_phy_cap_from_link_speeds(uint32_t speeds)
101 uint32_t phy_caps = 0;
103 if (~speeds & ETH_LINK_SPEED_FIXED) {
104 phy_caps |= (1 << EFX_PHY_CAP_AN);
106 * If no speeds are specified in the mask, any supported
109 if (speeds == ETH_LINK_SPEED_AUTONEG)
111 (1 << EFX_PHY_CAP_1000FDX) |
112 (1 << EFX_PHY_CAP_10000FDX) |
113 (1 << EFX_PHY_CAP_25000FDX) |
114 (1 << EFX_PHY_CAP_40000FDX) |
115 (1 << EFX_PHY_CAP_50000FDX) |
116 (1 << EFX_PHY_CAP_100000FDX);
118 if (speeds & ETH_LINK_SPEED_1G)
119 phy_caps |= (1 << EFX_PHY_CAP_1000FDX);
120 if (speeds & ETH_LINK_SPEED_10G)
121 phy_caps |= (1 << EFX_PHY_CAP_10000FDX);
122 if (speeds & ETH_LINK_SPEED_25G)
123 phy_caps |= (1 << EFX_PHY_CAP_25000FDX);
124 if (speeds & ETH_LINK_SPEED_40G)
125 phy_caps |= (1 << EFX_PHY_CAP_40000FDX);
126 if (speeds & ETH_LINK_SPEED_50G)
127 phy_caps |= (1 << EFX_PHY_CAP_50000FDX);
128 if (speeds & ETH_LINK_SPEED_100G)
129 phy_caps |= (1 << EFX_PHY_CAP_100000FDX);
135 * Check requested device level configuration.
136 * Receive and transmit configuration is checked in corresponding
140 sfc_check_conf(struct sfc_adapter *sa)
142 const struct rte_eth_conf *conf = &sa->eth_dev->data->dev_conf;
145 sa->port.phy_adv_cap =
146 sfc_phy_cap_from_link_speeds(conf->link_speeds) &
147 sa->port.phy_adv_cap_mask;
148 if ((sa->port.phy_adv_cap & ~(1 << EFX_PHY_CAP_AN)) == 0) {
149 sfc_err(sa, "No link speeds from mask %#x are supported",
154 #if !EFSYS_OPT_LOOPBACK
155 if (conf->lpbk_mode != 0) {
156 sfc_err(sa, "Loopback not supported");
161 if (conf->dcb_capability_en != 0) {
162 sfc_err(sa, "Priority-based flow control not supported");
166 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
167 sfc_err(sa, "Flow Director not supported");
171 if ((conf->intr_conf.lsc != 0) &&
172 (sa->intr.type != EFX_INTR_LINE) &&
173 (sa->intr.type != EFX_INTR_MESSAGE)) {
174 sfc_err(sa, "Link status change interrupt not supported");
178 if (conf->intr_conf.rxq != 0 &&
179 (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_INTR) == 0) {
180 sfc_err(sa, "Receive queue interrupt not supported");
188 * Find out maximum number of receive and transmit queues which could be
191 * NIC is kept initialized on success to allow other modules acquire
192 * defaults and capabilities.
195 sfc_estimate_resource_limits(struct sfc_adapter *sa)
197 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
198 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
199 efx_drv_limits_t limits;
201 uint32_t evq_allocated;
202 uint32_t rxq_allocated;
203 uint32_t txq_allocated;
205 memset(&limits, 0, sizeof(limits));
207 /* Request at least one Rx and Tx queue */
208 limits.edl_min_rxq_count = 1;
209 limits.edl_min_txq_count = 1;
210 /* Management event queue plus event queue for each Tx and Rx queue */
211 limits.edl_min_evq_count =
212 1 + limits.edl_min_rxq_count + limits.edl_min_txq_count;
214 /* Divide by number of functions to guarantee that all functions
215 * will get promised resources
217 /* FIXME Divide by number of functions (not 2) below */
218 limits.edl_max_evq_count = encp->enc_evq_limit / 2;
219 SFC_ASSERT(limits.edl_max_evq_count >= limits.edl_min_rxq_count);
221 /* Split equally between receive and transmit */
222 limits.edl_max_rxq_count =
223 MIN(encp->enc_rxq_limit, (limits.edl_max_evq_count - 1) / 2);
224 SFC_ASSERT(limits.edl_max_rxq_count >= limits.edl_min_rxq_count);
226 limits.edl_max_txq_count =
227 MIN(encp->enc_txq_limit,
228 limits.edl_max_evq_count - 1 - limits.edl_max_rxq_count);
230 if (sa->tso && encp->enc_fw_assisted_tso_v2_enabled)
231 limits.edl_max_txq_count =
232 MIN(limits.edl_max_txq_count,
233 encp->enc_fw_assisted_tso_v2_n_contexts /
234 encp->enc_hw_pf_count);
236 SFC_ASSERT(limits.edl_max_txq_count >= limits.edl_min_rxq_count);
238 /* Configure the minimum required resources needed for the
239 * driver to operate, and the maximum desired resources that the
240 * driver is capable of using.
242 efx_nic_set_drv_limits(sa->nic, &limits);
244 sfc_log_init(sa, "init nic");
245 rc = efx_nic_init(sa->nic);
249 /* Find resource dimensions assigned by firmware to this function */
250 rc = efx_nic_get_vi_pool(sa->nic, &evq_allocated, &rxq_allocated,
253 goto fail_get_vi_pool;
255 /* It still may allocate more than maximum, ensure limit */
256 evq_allocated = MIN(evq_allocated, limits.edl_max_evq_count);
257 rxq_allocated = MIN(rxq_allocated, limits.edl_max_rxq_count);
258 txq_allocated = MIN(txq_allocated, limits.edl_max_txq_count);
261 * Subtract management EVQ not used for traffic
262 * The resource allocation strategy is as follows:
263 * - one EVQ for management
264 * - one EVQ for each ethdev RXQ
265 * - one EVQ for each ethdev TXQ
266 * - one EVQ and one RXQ for optional MAE counters.
268 if (evq_allocated == 0) {
269 sfc_err(sa, "count of allocated EvQ is 0");
271 goto fail_allocate_evq;
276 * Reserve absolutely required minimum.
277 * Right now we use separate EVQ for Rx and Tx.
279 if (rxq_allocated > 0 && evq_allocated > 0) {
284 if (txq_allocated > 0 && evq_allocated > 0) {
290 if (sfc_mae_counter_rxq_required(sa) &&
291 rxq_allocated > 0 && evq_allocated > 0) {
294 sas->counters_rxq_allocated = true;
296 sas->counters_rxq_allocated = false;
299 /* Add remaining allocated queues */
300 sa->rxq_max += MIN(rxq_allocated, evq_allocated / 2);
301 sa->txq_max += MIN(txq_allocated, evq_allocated - sa->rxq_max);
303 /* Keep NIC initialized */
308 efx_nic_fini(sa->nic);
314 sfc_set_drv_limits(struct sfc_adapter *sa)
316 const struct rte_eth_dev_data *data = sa->eth_dev->data;
317 uint32_t rxq_reserved = sfc_nb_reserved_rxq(sfc_sa2shared(sa));
318 efx_drv_limits_t lim;
320 memset(&lim, 0, sizeof(lim));
323 * Limits are strict since take into account initial estimation.
324 * Resource allocation stategy is described in
325 * sfc_estimate_resource_limits().
327 lim.edl_min_evq_count = lim.edl_max_evq_count =
328 1 + data->nb_rx_queues + data->nb_tx_queues + rxq_reserved;
329 lim.edl_min_rxq_count = lim.edl_max_rxq_count =
330 data->nb_rx_queues + rxq_reserved;
331 lim.edl_min_txq_count = lim.edl_max_txq_count = data->nb_tx_queues;
333 return efx_nic_set_drv_limits(sa->nic, &lim);
337 sfc_set_fw_subvariant(struct sfc_adapter *sa)
339 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
340 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
341 uint64_t tx_offloads = sa->eth_dev->data->dev_conf.txmode.offloads;
342 unsigned int txq_index;
343 efx_nic_fw_subvariant_t req_fw_subvariant;
344 efx_nic_fw_subvariant_t cur_fw_subvariant;
347 if (!encp->enc_fw_subvariant_no_tx_csum_supported) {
348 sfc_info(sa, "no-Tx-checksum subvariant not supported");
352 for (txq_index = 0; txq_index < sas->txq_count; ++txq_index) {
353 struct sfc_txq_info *txq_info = &sas->txq_info[txq_index];
355 if (txq_info->state & SFC_TXQ_INITIALIZED)
356 tx_offloads |= txq_info->offloads;
359 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
360 DEV_TX_OFFLOAD_TCP_CKSUM |
361 DEV_TX_OFFLOAD_UDP_CKSUM |
362 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM))
363 req_fw_subvariant = EFX_NIC_FW_SUBVARIANT_DEFAULT;
365 req_fw_subvariant = EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM;
367 rc = efx_nic_get_fw_subvariant(sa->nic, &cur_fw_subvariant);
369 sfc_err(sa, "failed to get FW subvariant: %d", rc);
372 sfc_info(sa, "FW subvariant is %u vs required %u",
373 cur_fw_subvariant, req_fw_subvariant);
375 if (cur_fw_subvariant == req_fw_subvariant)
378 rc = efx_nic_set_fw_subvariant(sa->nic, req_fw_subvariant);
380 sfc_err(sa, "failed to set FW subvariant %u: %d",
381 req_fw_subvariant, rc);
384 sfc_info(sa, "FW subvariant set to %u", req_fw_subvariant);
390 sfc_try_start(struct sfc_adapter *sa)
392 const efx_nic_cfg_t *encp;
395 sfc_log_init(sa, "entry");
397 SFC_ASSERT(sfc_adapter_is_locked(sa));
398 SFC_ASSERT(sa->state == SFC_ADAPTER_STARTING);
400 sfc_log_init(sa, "set FW subvariant");
401 rc = sfc_set_fw_subvariant(sa);
403 goto fail_set_fw_subvariant;
405 sfc_log_init(sa, "set resource limits");
406 rc = sfc_set_drv_limits(sa);
408 goto fail_set_drv_limits;
410 sfc_log_init(sa, "init nic");
411 rc = efx_nic_init(sa->nic);
415 encp = efx_nic_cfg_get(sa->nic);
418 * Refresh (since it may change on NIC reset/restart) a copy of
419 * supported tunnel encapsulations in shared memory to be used
420 * on supported Rx packet type classes get.
422 sa->priv.shared->tunnel_encaps =
423 encp->enc_tunnel_encapsulations_supported;
425 if (encp->enc_tunnel_encapsulations_supported != 0) {
426 sfc_log_init(sa, "apply tunnel config");
427 rc = efx_tunnel_reconfigure(sa->nic);
429 goto fail_tunnel_reconfigure;
432 rc = sfc_intr_start(sa);
434 goto fail_intr_start;
436 rc = sfc_ev_start(sa);
440 rc = sfc_port_start(sa);
442 goto fail_port_start;
444 rc = sfc_rx_start(sa);
448 rc = sfc_tx_start(sa);
452 rc = sfc_flow_start(sa);
454 goto fail_flows_insert;
456 rc = sfc_repr_proxy_start(sa);
458 goto fail_repr_proxy_start;
460 sfc_log_init(sa, "done");
463 fail_repr_proxy_start:
482 fail_tunnel_reconfigure:
483 efx_nic_fini(sa->nic);
487 fail_set_fw_subvariant:
488 sfc_log_init(sa, "failed %d", rc);
493 sfc_start(struct sfc_adapter *sa)
495 unsigned int start_tries = 3;
498 sfc_log_init(sa, "entry");
500 SFC_ASSERT(sfc_adapter_is_locked(sa));
503 case SFC_ADAPTER_CONFIGURED:
505 case SFC_ADAPTER_STARTED:
506 sfc_notice(sa, "already started");
513 sa->state = SFC_ADAPTER_STARTING;
518 * FIXME Try to recreate vSwitch on start retry.
519 * vSwitch is absent after MC reboot like events and
520 * we should recreate it. May be we need proper
521 * indication instead of guessing.
524 sfc_sriov_vswitch_destroy(sa);
525 rc = sfc_sriov_vswitch_create(sa);
527 goto fail_sriov_vswitch_create;
529 rc = sfc_try_start(sa);
530 } while ((--start_tries > 0) &&
531 (rc == EIO || rc == EAGAIN || rc == ENOENT || rc == EINVAL));
536 sa->state = SFC_ADAPTER_STARTED;
537 sfc_log_init(sa, "done");
541 fail_sriov_vswitch_create:
542 sa->state = SFC_ADAPTER_CONFIGURED;
544 sfc_log_init(sa, "failed %d", rc);
549 sfc_stop(struct sfc_adapter *sa)
551 sfc_log_init(sa, "entry");
553 SFC_ASSERT(sfc_adapter_is_locked(sa));
556 case SFC_ADAPTER_STARTED:
558 case SFC_ADAPTER_CONFIGURED:
559 sfc_notice(sa, "already stopped");
562 sfc_err(sa, "stop in unexpected state %u", sa->state);
567 sa->state = SFC_ADAPTER_STOPPING;
569 sfc_repr_proxy_stop(sa);
576 efx_nic_fini(sa->nic);
578 sa->state = SFC_ADAPTER_CONFIGURED;
579 sfc_log_init(sa, "done");
583 sfc_restart(struct sfc_adapter *sa)
587 SFC_ASSERT(sfc_adapter_is_locked(sa));
589 if (sa->state != SFC_ADAPTER_STARTED)
596 sfc_err(sa, "restart failed");
602 sfc_restart_if_required(void *arg)
604 struct sfc_adapter *sa = arg;
606 /* If restart is scheduled, clear the flag and do it */
607 if (rte_atomic32_cmpset((volatile uint32_t *)&sa->restart_required,
609 sfc_adapter_lock(sa);
610 if (sa->state == SFC_ADAPTER_STARTED)
611 (void)sfc_restart(sa);
612 sfc_adapter_unlock(sa);
617 sfc_schedule_restart(struct sfc_adapter *sa)
621 /* Schedule restart alarm if it is not scheduled yet */
622 if (!rte_atomic32_test_and_set(&sa->restart_required))
625 rc = rte_eal_alarm_set(1, sfc_restart_if_required, sa);
627 sfc_warn(sa, "alarms are not supported, restart is pending");
629 sfc_err(sa, "cannot arm restart alarm (rc=%d)", rc);
631 sfc_notice(sa, "restart scheduled");
635 sfc_configure(struct sfc_adapter *sa)
639 sfc_log_init(sa, "entry");
641 SFC_ASSERT(sfc_adapter_is_locked(sa));
643 SFC_ASSERT(sa->state == SFC_ADAPTER_INITIALIZED ||
644 sa->state == SFC_ADAPTER_CONFIGURED);
645 sa->state = SFC_ADAPTER_CONFIGURING;
647 rc = sfc_check_conf(sa);
649 goto fail_check_conf;
651 rc = sfc_intr_configure(sa);
653 goto fail_intr_configure;
655 rc = sfc_port_configure(sa);
657 goto fail_port_configure;
659 rc = sfc_rx_configure(sa);
661 goto fail_rx_configure;
663 rc = sfc_tx_configure(sa);
665 goto fail_tx_configure;
667 rc = sfc_sw_xstats_configure(sa);
669 goto fail_sw_xstats_configure;
671 sa->state = SFC_ADAPTER_CONFIGURED;
672 sfc_log_init(sa, "done");
675 fail_sw_xstats_configure:
689 sa->state = SFC_ADAPTER_INITIALIZED;
690 sfc_log_init(sa, "failed %d", rc);
695 sfc_close(struct sfc_adapter *sa)
697 sfc_log_init(sa, "entry");
699 SFC_ASSERT(sfc_adapter_is_locked(sa));
701 SFC_ASSERT(sa->state == SFC_ADAPTER_CONFIGURED);
702 sa->state = SFC_ADAPTER_CLOSING;
704 sfc_sw_xstats_close(sa);
710 sa->state = SFC_ADAPTER_INITIALIZED;
711 sfc_log_init(sa, "done");
715 sfc_mem_bar_init(struct sfc_adapter *sa, const efx_bar_region_t *mem_ebrp)
717 struct rte_eth_dev *eth_dev = sa->eth_dev;
718 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
719 efsys_bar_t *ebp = &sa->mem_bar;
720 struct rte_mem_resource *res =
721 &pci_dev->mem_resource[mem_ebrp->ebr_index];
723 SFC_BAR_LOCK_INIT(ebp, eth_dev->data->name);
724 ebp->esb_rid = mem_ebrp->ebr_index;
725 ebp->esb_dev = pci_dev;
726 ebp->esb_base = res->addr;
728 sa->fcw_offset = mem_ebrp->ebr_offset;
734 sfc_mem_bar_fini(struct sfc_adapter *sa)
736 efsys_bar_t *ebp = &sa->mem_bar;
738 SFC_BAR_LOCK_DESTROY(ebp);
739 memset(ebp, 0, sizeof(*ebp));
743 * A fixed RSS key which has a property of being symmetric
744 * (symmetrical flows are distributed to the same CPU)
745 * and also known to give a uniform distribution
746 * (a good distribution of traffic between different CPUs)
748 static const uint8_t default_rss_key[EFX_RSS_KEY_SIZE] = {
749 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
750 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
751 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
752 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
753 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a, 0x6d, 0x5a,
757 sfc_rss_attach(struct sfc_adapter *sa)
759 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
762 rc = efx_intr_init(sa->nic, sa->intr.type, NULL);
766 rc = efx_ev_init(sa->nic);
770 rc = efx_rx_init(sa->nic);
774 rc = efx_rx_scale_default_support_get(sa->nic, &rss->context_type);
776 goto fail_scale_support_get;
778 rc = efx_rx_hash_default_support_get(sa->nic, &rss->hash_support);
780 goto fail_hash_support_get;
782 rc = sfc_rx_hash_init(sa);
784 goto fail_rx_hash_init;
786 efx_rx_fini(sa->nic);
787 efx_ev_fini(sa->nic);
788 efx_intr_fini(sa->nic);
790 rte_memcpy(rss->key, default_rss_key, sizeof(rss->key));
791 rss->dummy_rss_context = EFX_RSS_CONTEXT_DEFAULT;
796 fail_hash_support_get:
797 fail_scale_support_get:
798 efx_rx_fini(sa->nic);
801 efx_ev_fini(sa->nic);
804 efx_intr_fini(sa->nic);
811 sfc_rss_detach(struct sfc_adapter *sa)
813 sfc_rx_hash_fini(sa);
817 sfc_attach(struct sfc_adapter *sa)
819 const efx_nic_cfg_t *encp;
820 efx_nic_t *enp = sa->nic;
823 sfc_log_init(sa, "entry");
825 SFC_ASSERT(sfc_adapter_is_locked(sa));
827 efx_mcdi_new_epoch(enp);
829 sfc_log_init(sa, "reset nic");
830 rc = efx_nic_reset(enp);
834 rc = sfc_sriov_attach(sa);
836 goto fail_sriov_attach;
839 * Probed NIC is sufficient for tunnel init.
840 * Initialize tunnel support to be able to use libefx
841 * efx_tunnel_config_udp_{add,remove}() in any state and
842 * efx_tunnel_reconfigure() on start up.
844 rc = efx_tunnel_init(enp);
846 goto fail_tunnel_init;
848 encp = efx_nic_cfg_get(sa->nic);
851 * Make a copy of supported tunnel encapsulations in shared
852 * memory to be used on supported Rx packet type classes get.
854 sa->priv.shared->tunnel_encaps =
855 encp->enc_tunnel_encapsulations_supported;
857 if (sfc_dp_tx_offload_capa(sa->priv.dp_tx) & DEV_TX_OFFLOAD_TCP_TSO) {
858 sa->tso = encp->enc_fw_assisted_tso_v2_enabled ||
859 encp->enc_tso_v3_enabled;
861 sfc_info(sa, "TSO support isn't available on this adapter");
865 (sfc_dp_tx_offload_capa(sa->priv.dp_tx) &
866 (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
867 DEV_TX_OFFLOAD_GENEVE_TNL_TSO)) != 0) {
868 sa->tso_encap = encp->enc_fw_assisted_tso_v2_encap_enabled ||
869 encp->enc_tso_v3_enabled;
871 sfc_info(sa, "Encapsulated TSO support isn't available on this adapter");
874 sfc_log_init(sa, "estimate resource limits");
875 rc = sfc_estimate_resource_limits(sa);
877 goto fail_estimate_rsrc_limits;
879 sa->evq_max_entries = encp->enc_evq_max_nevs;
880 SFC_ASSERT(rte_is_power_of_2(sa->evq_max_entries));
882 sa->evq_min_entries = encp->enc_evq_min_nevs;
883 SFC_ASSERT(rte_is_power_of_2(sa->evq_min_entries));
885 sa->rxq_max_entries = encp->enc_rxq_max_ndescs;
886 SFC_ASSERT(rte_is_power_of_2(sa->rxq_max_entries));
888 sa->rxq_min_entries = encp->enc_rxq_min_ndescs;
889 SFC_ASSERT(rte_is_power_of_2(sa->rxq_min_entries));
891 sa->txq_max_entries = encp->enc_txq_max_ndescs;
892 SFC_ASSERT(rte_is_power_of_2(sa->txq_max_entries));
894 sa->txq_min_entries = encp->enc_txq_min_ndescs;
895 SFC_ASSERT(rte_is_power_of_2(sa->txq_min_entries));
897 rc = sfc_intr_attach(sa);
899 goto fail_intr_attach;
901 rc = sfc_ev_attach(sa);
905 rc = sfc_port_attach(sa);
907 goto fail_port_attach;
909 rc = sfc_rss_attach(sa);
911 goto fail_rss_attach;
913 rc = sfc_filter_attach(sa);
915 goto fail_filter_attach;
917 rc = sfc_mae_counter_rxq_attach(sa);
919 goto fail_mae_counter_rxq_attach;
921 rc = sfc_mae_attach(sa);
923 goto fail_mae_attach;
925 rc = sfc_mae_switchdev_init(sa);
927 goto fail_mae_switchdev_init;
929 rc = sfc_repr_proxy_attach(sa);
931 goto fail_repr_proxy_attach;
933 sfc_log_init(sa, "fini nic");
938 rc = sfc_sw_xstats_init(sa);
940 goto fail_sw_xstats_init;
943 * Create vSwitch to be able to use VFs when PF is not started yet
944 * as DPDK port. VFs should be able to talk to each other even
947 rc = sfc_sriov_vswitch_create(sa);
949 goto fail_sriov_vswitch_create;
951 sa->state = SFC_ADAPTER_INITIALIZED;
953 sfc_log_init(sa, "done");
956 fail_sriov_vswitch_create:
957 sfc_sw_xstats_close(sa);
961 sfc_repr_proxy_detach(sa);
963 fail_repr_proxy_attach:
964 sfc_mae_switchdev_fini(sa);
966 fail_mae_switchdev_init:
970 sfc_mae_counter_rxq_detach(sa);
972 fail_mae_counter_rxq_attach:
973 sfc_filter_detach(sa);
988 efx_nic_fini(sa->nic);
990 fail_estimate_rsrc_limits:
992 efx_tunnel_fini(sa->nic);
993 sfc_sriov_detach(sa);
998 sfc_log_init(sa, "failed %d", rc);
1003 sfc_detach(struct sfc_adapter *sa)
1005 sfc_log_init(sa, "entry");
1007 SFC_ASSERT(sfc_adapter_is_locked(sa));
1009 sfc_sriov_vswitch_destroy(sa);
1013 sfc_repr_proxy_detach(sa);
1014 sfc_mae_switchdev_fini(sa);
1016 sfc_mae_counter_rxq_detach(sa);
1017 sfc_filter_detach(sa);
1019 sfc_port_detach(sa);
1021 sfc_intr_detach(sa);
1022 efx_tunnel_fini(sa->nic);
1023 sfc_sriov_detach(sa);
1025 sa->state = SFC_ADAPTER_UNINITIALIZED;
1029 sfc_kvarg_fv_variant_handler(__rte_unused const char *key,
1030 const char *value_str, void *opaque)
1032 uint32_t *value = opaque;
1034 if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_DONT_CARE) == 0)
1035 *value = EFX_FW_VARIANT_DONT_CARE;
1036 else if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_FULL_FEATURED) == 0)
1037 *value = EFX_FW_VARIANT_FULL_FEATURED;
1038 else if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_LOW_LATENCY) == 0)
1039 *value = EFX_FW_VARIANT_LOW_LATENCY;
1040 else if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_PACKED_STREAM) == 0)
1041 *value = EFX_FW_VARIANT_PACKED_STREAM;
1042 else if (strcasecmp(value_str, SFC_KVARG_FW_VARIANT_DPDK) == 0)
1043 *value = EFX_FW_VARIANT_DPDK;
1051 sfc_get_fw_variant(struct sfc_adapter *sa, efx_fw_variant_t *efv)
1053 efx_nic_fw_info_t enfi;
1056 rc = efx_nic_get_fw_version(sa->nic, &enfi);
1059 else if (!enfi.enfi_dpcpu_fw_ids_valid)
1063 * Firmware variant can be uniquely identified by the RxDPCPU
1066 switch (enfi.enfi_rx_dpcpu_fw_id) {
1067 case EFX_RXDP_FULL_FEATURED_FW_ID:
1068 *efv = EFX_FW_VARIANT_FULL_FEATURED;
1071 case EFX_RXDP_LOW_LATENCY_FW_ID:
1072 *efv = EFX_FW_VARIANT_LOW_LATENCY;
1075 case EFX_RXDP_PACKED_STREAM_FW_ID:
1076 *efv = EFX_FW_VARIANT_PACKED_STREAM;
1079 case EFX_RXDP_DPDK_FW_ID:
1080 *efv = EFX_FW_VARIANT_DPDK;
1085 * Other firmware variants are not considered, since they are
1086 * not supported in the device parameters
1088 *efv = EFX_FW_VARIANT_DONT_CARE;
1096 sfc_fw_variant2str(efx_fw_variant_t efv)
1099 case EFX_RXDP_FULL_FEATURED_FW_ID:
1100 return SFC_KVARG_FW_VARIANT_FULL_FEATURED;
1101 case EFX_RXDP_LOW_LATENCY_FW_ID:
1102 return SFC_KVARG_FW_VARIANT_LOW_LATENCY;
1103 case EFX_RXDP_PACKED_STREAM_FW_ID:
1104 return SFC_KVARG_FW_VARIANT_PACKED_STREAM;
1105 case EFX_RXDP_DPDK_FW_ID:
1106 return SFC_KVARG_FW_VARIANT_DPDK;
1113 sfc_kvarg_rxd_wait_timeout_ns(struct sfc_adapter *sa)
1118 value = SFC_RXD_WAIT_TIMEOUT_NS_DEF;
1120 rc = sfc_kvargs_process(sa, SFC_KVARG_RXD_WAIT_TIMEOUT_NS,
1121 sfc_kvarg_long_handler, &value);
1126 (unsigned long)value > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
1127 sfc_err(sa, "wrong '" SFC_KVARG_RXD_WAIT_TIMEOUT_NS "' "
1128 "was set (%ld);", value);
1129 sfc_err(sa, "it must not be less than 0 or greater than %u",
1130 EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX);
1134 sa->rxd_wait_timeout_ns = value;
1139 sfc_nic_probe(struct sfc_adapter *sa)
1141 efx_nic_t *enp = sa->nic;
1142 efx_fw_variant_t preferred_efv;
1143 efx_fw_variant_t efv;
1146 preferred_efv = EFX_FW_VARIANT_DONT_CARE;
1147 rc = sfc_kvargs_process(sa, SFC_KVARG_FW_VARIANT,
1148 sfc_kvarg_fv_variant_handler,
1151 sfc_err(sa, "invalid %s parameter value", SFC_KVARG_FW_VARIANT);
1155 rc = sfc_kvarg_rxd_wait_timeout_ns(sa);
1159 rc = efx_nic_probe(enp, preferred_efv);
1161 /* Unprivileged functions cannot set FW variant */
1162 rc = efx_nic_probe(enp, EFX_FW_VARIANT_DONT_CARE);
1167 rc = sfc_get_fw_variant(sa, &efv);
1168 if (rc == ENOTSUP) {
1169 sfc_warn(sa, "FW variant can not be obtained");
1175 /* Check that firmware variant was changed to the requested one */
1176 if (preferred_efv != EFX_FW_VARIANT_DONT_CARE && preferred_efv != efv) {
1177 sfc_warn(sa, "FW variant has not changed to the requested %s",
1178 sfc_fw_variant2str(preferred_efv));
1181 sfc_notice(sa, "running FW variant is %s", sfc_fw_variant2str(efv));
1187 sfc_probe(struct sfc_adapter *sa)
1189 efx_bar_region_t mem_ebrp;
1190 struct rte_eth_dev *eth_dev = sa->eth_dev;
1191 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1195 sfc_log_init(sa, "entry");
1197 SFC_ASSERT(sfc_adapter_is_locked(sa));
1199 sa->socket_id = rte_socket_id();
1200 rte_atomic32_init(&sa->restart_required);
1202 sfc_log_init(sa, "get family");
1203 rc = sfc_efx_family(pci_dev, &mem_ebrp, &sa->family);
1208 "family is %u, membar is %u, function control window offset is %lu",
1209 sa->family, mem_ebrp.ebr_index, mem_ebrp.ebr_offset);
1211 sfc_log_init(sa, "init mem bar");
1212 rc = sfc_mem_bar_init(sa, &mem_ebrp);
1214 goto fail_mem_bar_init;
1216 sfc_log_init(sa, "create nic");
1217 rte_spinlock_init(&sa->nic_lock);
1218 rc = efx_nic_create(sa->family, (efsys_identifier_t *)sa,
1219 &sa->mem_bar, mem_ebrp.ebr_offset,
1220 &sa->nic_lock, &enp);
1222 goto fail_nic_create;
1225 rc = sfc_mcdi_init(sa);
1227 goto fail_mcdi_init;
1229 sfc_log_init(sa, "probe nic");
1230 rc = sfc_nic_probe(sa);
1232 goto fail_nic_probe;
1234 sfc_log_init(sa, "done");
1241 sfc_log_init(sa, "destroy nic");
1243 efx_nic_destroy(enp);
1246 sfc_mem_bar_fini(sa);
1250 sfc_log_init(sa, "failed %d", rc);
1255 sfc_unprobe(struct sfc_adapter *sa)
1257 efx_nic_t *enp = sa->nic;
1259 sfc_log_init(sa, "entry");
1261 SFC_ASSERT(sfc_adapter_is_locked(sa));
1263 sfc_log_init(sa, "unprobe nic");
1264 efx_nic_unprobe(enp);
1269 * Make sure there is no pending alarm to restart since we are
1270 * going to free device private which is passed as the callback
1271 * opaque data. A new alarm cannot be scheduled since MCDI is
1274 rte_eal_alarm_cancel(sfc_restart_if_required, sa);
1276 sfc_log_init(sa, "destroy nic");
1278 efx_nic_destroy(enp);
1280 sfc_mem_bar_fini(sa);
1283 sa->state = SFC_ADAPTER_UNINITIALIZED;
1287 sfc_register_logtype(const struct rte_pci_addr *pci_addr,
1288 const char *lt_prefix_str, uint32_t ll_default)
1290 size_t lt_prefix_str_size = strlen(lt_prefix_str);
1291 size_t lt_str_size_max;
1292 char *lt_str = NULL;
1295 if (SIZE_MAX - PCI_PRI_STR_SIZE - 1 > lt_prefix_str_size) {
1296 ++lt_prefix_str_size; /* Reserve space for prefix separator */
1297 lt_str_size_max = lt_prefix_str_size + PCI_PRI_STR_SIZE + 1;
1299 return sfc_logtype_driver;
1302 lt_str = rte_zmalloc("logtype_str", lt_str_size_max, 0);
1304 return sfc_logtype_driver;
1306 strncpy(lt_str, lt_prefix_str, lt_prefix_str_size);
1307 lt_str[lt_prefix_str_size - 1] = '.';
1308 rte_pci_device_name(pci_addr, lt_str + lt_prefix_str_size,
1309 lt_str_size_max - lt_prefix_str_size);
1310 lt_str[lt_str_size_max - 1] = '\0';
1312 ret = rte_log_register_type_and_pick_level(lt_str, ll_default);
1316 return sfc_logtype_driver;
1321 struct sfc_hw_switch_id {
1322 char board_sn[RTE_SIZEOF_FIELD(efx_nic_board_info_t, enbi_serial)];
1326 sfc_hw_switch_id_init(struct sfc_adapter *sa,
1327 struct sfc_hw_switch_id **idp)
1329 efx_nic_board_info_t board_info;
1330 struct sfc_hw_switch_id *id;
1336 id = rte_zmalloc("sfc_hw_switch_id", sizeof(*id), 0);
1340 rc = efx_nic_get_board_info(sa->nic, &board_info);
1344 memcpy(id->board_sn, board_info.enbi_serial, sizeof(id->board_sn));
1352 sfc_hw_switch_id_fini(__rte_unused struct sfc_adapter *sa,
1353 struct sfc_hw_switch_id *id)
1359 sfc_hw_switch_ids_equal(const struct sfc_hw_switch_id *left,
1360 const struct sfc_hw_switch_id *right)
1362 return strncmp(left->board_sn, right->board_sn,
1363 sizeof(left->board_sn)) == 0;