1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
17 #include "efx_types.h"
19 #include "efx_regs_ef100.h"
21 #include "sfc_debug.h"
22 #include "sfc_dp_tx.h"
23 #include "sfc_tweak.h"
24 #include "sfc_kvargs.h"
25 #include "sfc_ef100.h"
28 #define sfc_ef100_tx_err(_txq, ...) \
29 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, ERR, &(_txq)->dp.dpq, __VA_ARGS__)
31 #define sfc_ef100_tx_debug(_txq, ...) \
32 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, DEBUG, &(_txq)->dp.dpq, \
36 /** Maximum length of the send descriptor data */
37 #define SFC_EF100_TX_SEND_DESC_LEN_MAX \
38 ((1u << ESF_GZ_TX_SEND_LEN_WIDTH) - 1)
40 /** Maximum length of the segment descriptor data */
41 #define SFC_EF100_TX_SEG_DESC_LEN_MAX \
42 ((1u << ESF_GZ_TX_SEG_LEN_WIDTH) - 1)
45 * Maximum number of descriptors/buffers in the Tx ring.
46 * It should guarantee that corresponding event queue never overfill.
47 * EF100 native datapath uses event queue of the same size as Tx queue.
48 * Maximum number of events on datapath can be estimated as number of
49 * Tx queue entries (one event per Tx buffer in the worst case) plus
50 * Tx error and flush events.
52 #define SFC_EF100_TXQ_LIMIT(_ndesc) \
53 ((_ndesc) - 1 /* head must not step on tail */ - \
54 1 /* Rx error */ - 1 /* flush */)
56 struct sfc_ef100_tx_sw_desc {
57 struct rte_mbuf *mbuf;
60 struct sfc_ef100_txq {
62 #define SFC_EF100_TXQ_STARTED 0x1
63 #define SFC_EF100_TXQ_NOT_RUNNING 0x2
64 #define SFC_EF100_TXQ_EXCEPTION 0x4
66 unsigned int ptr_mask;
68 unsigned int completed;
69 unsigned int max_fill_level;
70 unsigned int free_thresh;
71 struct sfc_ef100_tx_sw_desc *sw_ring;
72 efx_oword_t *txq_hw_ring;
73 volatile void *doorbell;
76 unsigned int evq_read_ptr;
77 unsigned int evq_phase_bit_shift;
78 volatile efx_qword_t *evq_hw_ring;
80 /* Datapath transmit queue anchor */
84 static inline struct sfc_ef100_txq *
85 sfc_ef100_txq_by_dp_txq(struct sfc_dp_txq *dp_txq)
87 return container_of(dp_txq, struct sfc_ef100_txq, dp);
91 sfc_ef100_tx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
94 struct sfc_ef100_txq * const txq = sfc_ef100_txq_by_dp_txq(tx_queue);
97 for (i = 0; i < nb_pkts; i++) {
98 struct rte_mbuf *m = tx_pkts[i];
99 unsigned int max_nb_header_segs = 0;
100 bool calc_phdr_cksum = false;
104 * Partial checksum offload is used in the case of
105 * inner TCP/UDP checksum offload. It requires
106 * pseudo-header checksum which is calculated below,
107 * but requires contiguous packet headers.
109 if ((m->ol_flags & PKT_TX_TUNNEL_MASK) &&
110 (m->ol_flags & PKT_TX_L4_MASK)) {
111 calc_phdr_cksum = true;
112 max_nb_header_segs = 1;
115 ret = sfc_dp_tx_prepare_pkt(m, max_nb_header_segs, 0,
116 0, txq->max_fill_level, 0, 0);
117 if (unlikely(ret != 0)) {
122 if (m->nb_segs > EFX_MASK32(ESF_GZ_TX_SEND_NUM_SEGS)) {
127 if (calc_phdr_cksum) {
129 * Full checksum offload does IPv4 header checksum
130 * and does not require any assistance.
132 ret = rte_net_intel_cksum_flags_prepare(m,
133 m->ol_flags & ~PKT_TX_IP_CKSUM);
134 if (unlikely(ret != 0)) {
145 sfc_ef100_tx_get_event(struct sfc_ef100_txq *txq, efx_qword_t *ev)
147 volatile efx_qword_t *evq_hw_ring = txq->evq_hw_ring;
150 * Exception flag is set when reap is done.
151 * It is never done twice per packet burst get, and absence of
152 * the flag is checked on burst get entry.
154 SFC_ASSERT((txq->flags & SFC_EF100_TXQ_EXCEPTION) == 0);
156 *ev = evq_hw_ring[txq->evq_read_ptr & txq->ptr_mask];
158 if (!sfc_ef100_ev_present(ev,
159 (txq->evq_read_ptr >> txq->evq_phase_bit_shift) & 1))
162 if (unlikely(!sfc_ef100_ev_type_is(ev,
163 ESE_GZ_EF100_EV_TX_COMPLETION))) {
165 * Do not move read_ptr to keep the event for exception
166 * handling by the control path.
168 txq->flags |= SFC_EF100_TXQ_EXCEPTION;
169 sfc_ef100_tx_err(txq,
170 "TxQ exception at EvQ ptr %u(%#x), event %08x:%08x",
171 txq->evq_read_ptr, txq->evq_read_ptr & txq->ptr_mask,
172 EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
173 EFX_QWORD_FIELD(*ev, EFX_DWORD_0));
177 sfc_ef100_tx_debug(txq, "TxQ got event %08x:%08x at %u (%#x)",
178 EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
179 EFX_QWORD_FIELD(*ev, EFX_DWORD_0),
181 txq->evq_read_ptr & txq->ptr_mask);
188 sfc_ef100_tx_process_events(struct sfc_ef100_txq *txq)
190 unsigned int num_descs = 0;
193 while (sfc_ef100_tx_get_event(txq, &tx_ev))
194 num_descs += EFX_QWORD_FIELD(tx_ev, ESF_GZ_EV_TXCMPL_NUM_DESC);
200 sfc_ef100_tx_reap_num_descs(struct sfc_ef100_txq *txq, unsigned int num_descs)
203 unsigned int completed = txq->completed;
204 unsigned int pending = completed + num_descs;
205 struct rte_mbuf *bulk[SFC_TX_REAP_BULK_SIZE];
209 struct sfc_ef100_tx_sw_desc *txd;
212 txd = &txq->sw_ring[completed & txq->ptr_mask];
213 if (txd->mbuf == NULL)
216 m = rte_pktmbuf_prefree_seg(txd->mbuf);
222 if (nb == RTE_DIM(bulk) ||
223 (nb != 0 && m->pool != bulk[0]->pool)) {
224 rte_mempool_put_bulk(bulk[0]->pool,
230 } while (++completed != pending);
233 rte_mempool_put_bulk(bulk[0]->pool, (void *)bulk, nb);
235 txq->completed = completed;
240 sfc_ef100_tx_reap(struct sfc_ef100_txq *txq)
242 sfc_ef100_tx_reap_num_descs(txq, sfc_ef100_tx_process_events(txq));
246 sfc_ef100_tx_qdesc_cso_inner_l3(uint64_t tx_tunnel)
251 case PKT_TX_TUNNEL_VXLAN:
252 inner_l3 = ESE_GZ_TX_DESC_CS_INNER_L3_VXLAN;
254 case PKT_TX_TUNNEL_GENEVE:
255 inner_l3 = ESE_GZ_TX_DESC_CS_INNER_L3_GENEVE;
258 inner_l3 = ESE_GZ_TX_DESC_CS_INNER_L3_OFF;
265 sfc_ef100_tx_qdesc_send_create(const struct rte_mbuf *m, efx_oword_t *tx_desc)
271 uint16_t part_cksum_w;
272 uint16_t l4_offset_w;
274 if ((m->ol_flags & PKT_TX_TUNNEL_MASK) == 0) {
275 outer_l3 = (m->ol_flags & PKT_TX_IP_CKSUM);
276 outer_l4 = (m->ol_flags & PKT_TX_L4_MASK);
277 inner_l3 = ESE_GZ_TX_DESC_CS_INNER_L3_OFF;
278 partial_en = ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF;
282 outer_l3 = (m->ol_flags & PKT_TX_OUTER_IP_CKSUM);
283 outer_l4 = (m->ol_flags & PKT_TX_OUTER_UDP_CKSUM);
284 inner_l3 = sfc_ef100_tx_qdesc_cso_inner_l3(m->ol_flags &
287 switch (m->ol_flags & PKT_TX_L4_MASK) {
288 case PKT_TX_TCP_CKSUM:
289 partial_en = ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP;
290 part_cksum_w = offsetof(struct rte_tcp_hdr, cksum) >> 1;
292 case PKT_TX_UDP_CKSUM:
293 partial_en = ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP;
294 part_cksum_w = offsetof(struct rte_udp_hdr,
298 partial_en = ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF;
302 l4_offset_w = (m->outer_l2_len + m->outer_l3_len +
303 m->l2_len + m->l3_len) >> 1;
306 EFX_POPULATE_OWORD_10(*tx_desc,
307 ESF_GZ_TX_SEND_ADDR, rte_mbuf_data_iova(m),
308 ESF_GZ_TX_SEND_LEN, rte_pktmbuf_data_len(m),
309 ESF_GZ_TX_SEND_NUM_SEGS, m->nb_segs,
310 ESF_GZ_TX_SEND_CSO_PARTIAL_START_W, l4_offset_w,
311 ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W, part_cksum_w,
312 ESF_GZ_TX_SEND_CSO_PARTIAL_EN, partial_en,
313 ESF_GZ_TX_SEND_CSO_INNER_L3, inner_l3,
314 ESF_GZ_TX_SEND_CSO_OUTER_L3, outer_l3,
315 ESF_GZ_TX_SEND_CSO_OUTER_L4, outer_l4,
316 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEND);
320 sfc_ef100_tx_qdesc_seg_create(rte_iova_t addr, uint16_t len,
321 efx_oword_t *tx_desc)
323 EFX_POPULATE_OWORD_3(*tx_desc,
324 ESF_GZ_TX_SEG_ADDR, addr,
325 ESF_GZ_TX_SEG_LEN, len,
326 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEG);
330 sfc_ef100_tx_qpush(struct sfc_ef100_txq *txq, unsigned int added)
334 EFX_POPULATE_DWORD_1(dword, ERF_GZ_TX_RING_PIDX, added & txq->ptr_mask);
336 /* DMA sync to device is not required */
339 * rte_write32() has rte_io_wmb() which guarantees that the STORE
340 * operations (i.e. Rx and event descriptor updates) that precede
341 * the rte_io_wmb() call are visible to NIC before the STORE
342 * operations that follow it (i.e. doorbell write).
344 rte_write32(dword.ed_u32[0], txq->doorbell);
346 sfc_ef100_tx_debug(txq, "TxQ pushed doorbell at pidx %u (added=%u)",
347 EFX_DWORD_FIELD(dword, ERF_GZ_TX_RING_PIDX),
352 sfc_ef100_tx_pkt_descs_max(const struct rte_mbuf *m)
354 /** Maximum length of an mbuf segment data */
355 #define SFC_MBUF_SEG_LEN_MAX UINT16_MAX
356 RTE_BUILD_BUG_ON(sizeof(m->data_len) != 2);
359 * mbuf segment cannot be bigger than maximum segment length and
360 * maximum packet length since TSO is not supported yet.
361 * Make sure that the first segment does not need fragmentation
362 * (split into many Tx descriptors).
364 RTE_BUILD_BUG_ON(SFC_EF100_TX_SEND_DESC_LEN_MAX <
365 RTE_MIN((unsigned int)EFX_MAC_PDU_MAX, SFC_MBUF_SEG_LEN_MAX));
368 * Any segment of scattered packet cannot be bigger than maximum
369 * segment length and maximum packet length since TSO is not
371 * Make sure that subsequent segments do not need fragmentation (split
372 * into many Tx descriptors).
374 RTE_BUILD_BUG_ON(SFC_EF100_TX_SEG_DESC_LEN_MAX <
375 RTE_MIN((unsigned int)EFX_MAC_PDU_MAX, SFC_MBUF_SEG_LEN_MAX));
381 sfc_ef100_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
383 struct sfc_ef100_txq * const txq = sfc_ef100_txq_by_dp_txq(tx_queue);
385 unsigned int dma_desc_space;
387 struct rte_mbuf **pktp;
388 struct rte_mbuf **pktp_end;
390 if (unlikely(txq->flags &
391 (SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION)))
395 dma_desc_space = txq->max_fill_level - (added - txq->completed);
397 reap_done = (dma_desc_space < txq->free_thresh);
399 sfc_ef100_tx_reap(txq);
400 dma_desc_space = txq->max_fill_level - (added - txq->completed);
403 for (pktp = &tx_pkts[0], pktp_end = &tx_pkts[nb_pkts];
406 struct rte_mbuf *m_seg = *pktp;
407 unsigned int pkt_start = added;
410 if (likely(pktp + 1 != pktp_end))
411 rte_mbuf_prefetch_part1(pktp[1]);
413 if (sfc_ef100_tx_pkt_descs_max(m_seg) > dma_desc_space) {
417 /* Push already prepared descriptors before polling */
418 if (added != txq->added) {
419 sfc_ef100_tx_qpush(txq, added);
423 sfc_ef100_tx_reap(txq);
425 dma_desc_space = txq->max_fill_level -
426 (added - txq->completed);
427 if (sfc_ef100_tx_pkt_descs_max(m_seg) > dma_desc_space)
431 id = added++ & txq->ptr_mask;
432 sfc_ef100_tx_qdesc_send_create(m_seg, &txq->txq_hw_ring[id]);
435 * rte_pktmbuf_free() is commonly used in DPDK for
436 * recycling packets - the function checks every
437 * segment's reference counter and returns the
438 * buffer to its pool whenever possible;
439 * nevertheless, freeing mbuf segments one by one
440 * may entail some performance decline;
441 * from this point, sfc_efx_tx_reap() does the same job
442 * on its own and frees buffers in bulks (all mbufs
443 * within a bulk belong to the same pool);
444 * from this perspective, individual segment pointers
445 * must be associated with the corresponding SW
446 * descriptors independently so that only one loop
447 * is sufficient on reap to inspect all the buffers
449 txq->sw_ring[id].mbuf = m_seg;
451 while ((m_seg = m_seg->next) != NULL) {
452 RTE_BUILD_BUG_ON(SFC_MBUF_SEG_LEN_MAX >
453 SFC_EF100_TX_SEG_DESC_LEN_MAX);
455 id = added++ & txq->ptr_mask;
456 sfc_ef100_tx_qdesc_seg_create(rte_mbuf_data_iova(m_seg),
457 rte_pktmbuf_data_len(m_seg),
458 &txq->txq_hw_ring[id]);
459 txq->sw_ring[id].mbuf = m_seg;
462 dma_desc_space -= (added - pkt_start);
465 if (likely(added != txq->added)) {
466 sfc_ef100_tx_qpush(txq, added);
470 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
472 sfc_ef100_tx_reap(txq);
475 return pktp - &tx_pkts[0];
478 static sfc_dp_tx_get_dev_info_t sfc_ef100_get_dev_info;
480 sfc_ef100_get_dev_info(struct rte_eth_dev_info *dev_info)
483 * Number of descriptors just defines maximum number of pushed
484 * descriptors (fill level).
486 dev_info->tx_desc_lim.nb_min = 1;
487 dev_info->tx_desc_lim.nb_align = 1;
490 static sfc_dp_tx_qsize_up_rings_t sfc_ef100_tx_qsize_up_rings;
492 sfc_ef100_tx_qsize_up_rings(uint16_t nb_tx_desc,
493 struct sfc_dp_tx_hw_limits *limits,
494 unsigned int *txq_entries,
495 unsigned int *evq_entries,
496 unsigned int *txq_max_fill_level)
499 * rte_ethdev API guarantees that the number meets min, max and
500 * alignment requirements.
502 if (nb_tx_desc <= limits->txq_min_entries)
503 *txq_entries = limits->txq_min_entries;
505 *txq_entries = rte_align32pow2(nb_tx_desc);
507 *evq_entries = *txq_entries;
509 *txq_max_fill_level = RTE_MIN(nb_tx_desc,
510 SFC_EF100_TXQ_LIMIT(*evq_entries));
514 static sfc_dp_tx_qcreate_t sfc_ef100_tx_qcreate;
516 sfc_ef100_tx_qcreate(uint16_t port_id, uint16_t queue_id,
517 const struct rte_pci_addr *pci_addr, int socket_id,
518 const struct sfc_dp_tx_qcreate_info *info,
519 struct sfc_dp_txq **dp_txqp)
521 struct sfc_ef100_txq *txq;
525 if (info->txq_entries != info->evq_entries)
529 txq = rte_zmalloc_socket("sfc-ef100-txq", sizeof(*txq),
530 RTE_CACHE_LINE_SIZE, socket_id);
534 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
537 txq->sw_ring = rte_calloc_socket("sfc-ef100-txq-sw_ring",
539 sizeof(*txq->sw_ring),
540 RTE_CACHE_LINE_SIZE, socket_id);
541 if (txq->sw_ring == NULL)
542 goto fail_sw_ring_alloc;
544 txq->flags = SFC_EF100_TXQ_NOT_RUNNING;
545 txq->ptr_mask = info->txq_entries - 1;
546 txq->max_fill_level = info->max_fill_level;
547 txq->free_thresh = info->free_thresh;
548 txq->evq_phase_bit_shift = rte_bsf32(info->evq_entries);
549 txq->txq_hw_ring = info->txq_hw_ring;
550 txq->doorbell = (volatile uint8_t *)info->mem_bar +
551 ER_GZ_TX_RING_DOORBELL_OFST +
552 (info->hw_index << info->vi_window_shift);
553 txq->evq_hw_ring = info->evq_hw_ring;
555 sfc_ef100_tx_debug(txq, "TxQ doorbell is %p", txq->doorbell);
568 static sfc_dp_tx_qdestroy_t sfc_ef100_tx_qdestroy;
570 sfc_ef100_tx_qdestroy(struct sfc_dp_txq *dp_txq)
572 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
574 rte_free(txq->sw_ring);
578 static sfc_dp_tx_qstart_t sfc_ef100_tx_qstart;
580 sfc_ef100_tx_qstart(struct sfc_dp_txq *dp_txq, unsigned int evq_read_ptr,
581 unsigned int txq_desc_index)
583 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
585 txq->evq_read_ptr = evq_read_ptr;
586 txq->added = txq->completed = txq_desc_index;
588 txq->flags |= SFC_EF100_TXQ_STARTED;
589 txq->flags &= ~(SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION);
594 static sfc_dp_tx_qstop_t sfc_ef100_tx_qstop;
596 sfc_ef100_tx_qstop(struct sfc_dp_txq *dp_txq, unsigned int *evq_read_ptr)
598 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
600 txq->flags |= SFC_EF100_TXQ_NOT_RUNNING;
602 *evq_read_ptr = txq->evq_read_ptr;
605 static sfc_dp_tx_qtx_ev_t sfc_ef100_tx_qtx_ev;
607 sfc_ef100_tx_qtx_ev(struct sfc_dp_txq *dp_txq, unsigned int num_descs)
609 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
611 SFC_ASSERT(txq->flags & SFC_EF100_TXQ_NOT_RUNNING);
613 sfc_ef100_tx_reap_num_descs(txq, num_descs);
618 static sfc_dp_tx_qreap_t sfc_ef100_tx_qreap;
620 sfc_ef100_tx_qreap(struct sfc_dp_txq *dp_txq)
622 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
623 unsigned int completed;
625 for (completed = txq->completed; completed != txq->added; ++completed) {
626 struct sfc_ef100_tx_sw_desc *txd;
628 txd = &txq->sw_ring[completed & txq->ptr_mask];
629 if (txd->mbuf != NULL) {
630 rte_pktmbuf_free_seg(txd->mbuf);
635 txq->flags &= ~SFC_EF100_TXQ_STARTED;
639 sfc_ef100_tx_qdesc_npending(struct sfc_ef100_txq *txq)
641 const unsigned int evq_old_read_ptr = txq->evq_read_ptr;
642 unsigned int npending = 0;
645 if (unlikely(txq->flags &
646 (SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION)))
649 while (sfc_ef100_tx_get_event(txq, &tx_ev))
650 npending += EFX_QWORD_FIELD(tx_ev, ESF_GZ_EV_TXCMPL_NUM_DESC);
653 * The function does not process events, so return event queue read
654 * pointer to the original position to allow the events that were
655 * read to be processed later
657 txq->evq_read_ptr = evq_old_read_ptr;
662 static sfc_dp_tx_qdesc_status_t sfc_ef100_tx_qdesc_status;
664 sfc_ef100_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
666 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
667 unsigned int pushed = txq->added - txq->completed;
669 if (unlikely(offset > txq->ptr_mask))
672 if (unlikely(offset >= txq->max_fill_level))
673 return RTE_ETH_TX_DESC_UNAVAIL;
675 return (offset >= pushed ||
676 offset < sfc_ef100_tx_qdesc_npending(txq)) ?
677 RTE_ETH_TX_DESC_DONE : RTE_ETH_TX_DESC_FULL;
680 struct sfc_dp_tx sfc_ef100_tx = {
682 .name = SFC_KVARG_DATAPATH_EF100,
684 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF100,
686 .features = SFC_DP_TX_FEAT_MULTI_PROCESS,
687 .dev_offload_capa = 0,
688 .queue_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
689 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
690 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |
691 DEV_TX_OFFLOAD_UDP_CKSUM |
692 DEV_TX_OFFLOAD_TCP_CKSUM |
693 DEV_TX_OFFLOAD_MULTI_SEGS,
694 .get_dev_info = sfc_ef100_get_dev_info,
695 .qsize_up_rings = sfc_ef100_tx_qsize_up_rings,
696 .qcreate = sfc_ef100_tx_qcreate,
697 .qdestroy = sfc_ef100_tx_qdestroy,
698 .qstart = sfc_ef100_tx_qstart,
699 .qtx_ev = sfc_ef100_tx_qtx_ev,
700 .qstop = sfc_ef100_tx_qstop,
701 .qreap = sfc_ef100_tx_qreap,
702 .qdesc_status = sfc_ef100_tx_qdesc_status,
703 .pkt_prepare = sfc_ef100_tx_prepare_pkts,
704 .pkt_burst = sfc_ef100_xmit_pkts,