1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
16 #include "efx_types.h"
18 #include "efx_regs_ef100.h"
20 #include "sfc_debug.h"
21 #include "sfc_dp_tx.h"
22 #include "sfc_tweak.h"
23 #include "sfc_kvargs.h"
24 #include "sfc_ef100.h"
27 #define sfc_ef100_tx_err(_txq, ...) \
28 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, ERR, &(_txq)->dp.dpq, __VA_ARGS__)
30 #define sfc_ef100_tx_debug(_txq, ...) \
31 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF100, DEBUG, &(_txq)->dp.dpq, \
35 /** Maximum length of the send descriptor data */
36 #define SFC_EF100_TX_SEND_DESC_LEN_MAX \
37 ((1u << ESF_GZ_TX_SEND_LEN_WIDTH) - 1)
39 /** Maximum length of the segment descriptor data */
40 #define SFC_EF100_TX_SEG_DESC_LEN_MAX \
41 ((1u << ESF_GZ_TX_SEG_LEN_WIDTH) - 1)
44 * Maximum number of descriptors/buffers in the Tx ring.
45 * It should guarantee that corresponding event queue never overfill.
46 * EF100 native datapath uses event queue of the same size as Tx queue.
47 * Maximum number of events on datapath can be estimated as number of
48 * Tx queue entries (one event per Tx buffer in the worst case) plus
49 * Tx error and flush events.
51 #define SFC_EF100_TXQ_LIMIT(_ndesc) \
52 ((_ndesc) - 1 /* head must not step on tail */ - \
53 1 /* Rx error */ - 1 /* flush */)
55 struct sfc_ef100_tx_sw_desc {
56 struct rte_mbuf *mbuf;
59 struct sfc_ef100_txq {
61 #define SFC_EF100_TXQ_STARTED 0x1
62 #define SFC_EF100_TXQ_NOT_RUNNING 0x2
63 #define SFC_EF100_TXQ_EXCEPTION 0x4
65 unsigned int ptr_mask;
67 unsigned int completed;
68 unsigned int max_fill_level;
69 unsigned int free_thresh;
70 struct sfc_ef100_tx_sw_desc *sw_ring;
71 efx_oword_t *txq_hw_ring;
72 volatile void *doorbell;
75 unsigned int evq_read_ptr;
76 unsigned int evq_phase_bit_shift;
77 volatile efx_qword_t *evq_hw_ring;
79 /* Datapath transmit queue anchor */
83 static inline struct sfc_ef100_txq *
84 sfc_ef100_txq_by_dp_txq(struct sfc_dp_txq *dp_txq)
86 return container_of(dp_txq, struct sfc_ef100_txq, dp);
90 sfc_ef100_tx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
93 struct sfc_ef100_txq * const txq = sfc_ef100_txq_by_dp_txq(tx_queue);
96 for (i = 0; i < nb_pkts; i++) {
97 struct rte_mbuf *m = tx_pkts[i];
98 unsigned int max_nb_header_segs = 0;
101 ret = sfc_dp_tx_prepare_pkt(m, max_nb_header_segs, 0,
102 0, txq->max_fill_level, 0, 0);
103 if (unlikely(ret != 0)) {
108 if (m->nb_segs > EFX_MASK32(ESF_GZ_TX_SEND_NUM_SEGS)) {
118 sfc_ef100_tx_get_event(struct sfc_ef100_txq *txq, efx_qword_t *ev)
120 volatile efx_qword_t *evq_hw_ring = txq->evq_hw_ring;
123 * Exception flag is set when reap is done.
124 * It is never done twice per packet burst get, and absence of
125 * the flag is checked on burst get entry.
127 SFC_ASSERT((txq->flags & SFC_EF100_TXQ_EXCEPTION) == 0);
129 *ev = evq_hw_ring[txq->evq_read_ptr & txq->ptr_mask];
131 if (!sfc_ef100_ev_present(ev,
132 (txq->evq_read_ptr >> txq->evq_phase_bit_shift) & 1))
135 if (unlikely(!sfc_ef100_ev_type_is(ev,
136 ESE_GZ_EF100_EV_TX_COMPLETION))) {
138 * Do not move read_ptr to keep the event for exception
139 * handling by the control path.
141 txq->flags |= SFC_EF100_TXQ_EXCEPTION;
142 sfc_ef100_tx_err(txq,
143 "TxQ exception at EvQ ptr %u(%#x), event %08x:%08x",
144 txq->evq_read_ptr, txq->evq_read_ptr & txq->ptr_mask,
145 EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
146 EFX_QWORD_FIELD(*ev, EFX_DWORD_0));
150 sfc_ef100_tx_debug(txq, "TxQ got event %08x:%08x at %u (%#x)",
151 EFX_QWORD_FIELD(*ev, EFX_DWORD_1),
152 EFX_QWORD_FIELD(*ev, EFX_DWORD_0),
154 txq->evq_read_ptr & txq->ptr_mask);
161 sfc_ef100_tx_process_events(struct sfc_ef100_txq *txq)
163 unsigned int num_descs = 0;
166 while (sfc_ef100_tx_get_event(txq, &tx_ev))
167 num_descs += EFX_QWORD_FIELD(tx_ev, ESF_GZ_EV_TXCMPL_NUM_DESC);
173 sfc_ef100_tx_reap_num_descs(struct sfc_ef100_txq *txq, unsigned int num_descs)
176 unsigned int completed = txq->completed;
177 unsigned int pending = completed + num_descs;
178 struct rte_mbuf *bulk[SFC_TX_REAP_BULK_SIZE];
182 struct sfc_ef100_tx_sw_desc *txd;
185 txd = &txq->sw_ring[completed & txq->ptr_mask];
186 if (txd->mbuf == NULL)
189 m = rte_pktmbuf_prefree_seg(txd->mbuf);
195 if (nb == RTE_DIM(bulk) ||
196 (nb != 0 && m->pool != bulk[0]->pool)) {
197 rte_mempool_put_bulk(bulk[0]->pool,
203 } while (++completed != pending);
206 rte_mempool_put_bulk(bulk[0]->pool, (void *)bulk, nb);
208 txq->completed = completed;
213 sfc_ef100_tx_reap(struct sfc_ef100_txq *txq)
215 sfc_ef100_tx_reap_num_descs(txq, sfc_ef100_tx_process_events(txq));
219 sfc_ef100_tx_qdesc_send_create(const struct rte_mbuf *m, efx_oword_t *tx_desc)
224 outer_l3 = (m->ol_flags & PKT_TX_IP_CKSUM);
225 outer_l4 = (m->ol_flags & PKT_TX_L4_MASK);
227 EFX_POPULATE_OWORD_6(*tx_desc,
228 ESF_GZ_TX_SEND_ADDR, rte_mbuf_data_iova(m),
229 ESF_GZ_TX_SEND_LEN, rte_pktmbuf_data_len(m),
230 ESF_GZ_TX_SEND_NUM_SEGS, m->nb_segs,
231 ESF_GZ_TX_SEND_CSO_OUTER_L3, outer_l3,
232 ESF_GZ_TX_SEND_CSO_OUTER_L4, outer_l4,
233 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEND);
237 sfc_ef100_tx_qdesc_seg_create(rte_iova_t addr, uint16_t len,
238 efx_oword_t *tx_desc)
240 EFX_POPULATE_OWORD_3(*tx_desc,
241 ESF_GZ_TX_SEG_ADDR, addr,
242 ESF_GZ_TX_SEG_LEN, len,
243 ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEG);
247 sfc_ef100_tx_qpush(struct sfc_ef100_txq *txq, unsigned int added)
251 EFX_POPULATE_DWORD_1(dword, ERF_GZ_TX_RING_PIDX, added & txq->ptr_mask);
253 /* DMA sync to device is not required */
256 * rte_write32() has rte_io_wmb() which guarantees that the STORE
257 * operations (i.e. Rx and event descriptor updates) that precede
258 * the rte_io_wmb() call are visible to NIC before the STORE
259 * operations that follow it (i.e. doorbell write).
261 rte_write32(dword.ed_u32[0], txq->doorbell);
263 sfc_ef100_tx_debug(txq, "TxQ pushed doorbell at pidx %u (added=%u)",
264 EFX_DWORD_FIELD(dword, ERF_GZ_TX_RING_PIDX),
269 sfc_ef100_tx_pkt_descs_max(const struct rte_mbuf *m)
271 /** Maximum length of an mbuf segment data */
272 #define SFC_MBUF_SEG_LEN_MAX UINT16_MAX
273 RTE_BUILD_BUG_ON(sizeof(m->data_len) != 2);
276 * mbuf segment cannot be bigger than maximum segment length and
277 * maximum packet length since TSO is not supported yet.
278 * Make sure that the first segment does not need fragmentation
279 * (split into many Tx descriptors).
281 RTE_BUILD_BUG_ON(SFC_EF100_TX_SEND_DESC_LEN_MAX <
282 RTE_MIN((unsigned int)EFX_MAC_PDU_MAX, SFC_MBUF_SEG_LEN_MAX));
285 * Any segment of scattered packet cannot be bigger than maximum
286 * segment length and maximum packet length since TSO is not
288 * Make sure that subsequent segments do not need fragmentation (split
289 * into many Tx descriptors).
291 RTE_BUILD_BUG_ON(SFC_EF100_TX_SEG_DESC_LEN_MAX <
292 RTE_MIN((unsigned int)EFX_MAC_PDU_MAX, SFC_MBUF_SEG_LEN_MAX));
298 sfc_ef100_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
300 struct sfc_ef100_txq * const txq = sfc_ef100_txq_by_dp_txq(tx_queue);
302 unsigned int dma_desc_space;
304 struct rte_mbuf **pktp;
305 struct rte_mbuf **pktp_end;
307 if (unlikely(txq->flags &
308 (SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION)))
312 dma_desc_space = txq->max_fill_level - (added - txq->completed);
314 reap_done = (dma_desc_space < txq->free_thresh);
316 sfc_ef100_tx_reap(txq);
317 dma_desc_space = txq->max_fill_level - (added - txq->completed);
320 for (pktp = &tx_pkts[0], pktp_end = &tx_pkts[nb_pkts];
323 struct rte_mbuf *m_seg = *pktp;
324 unsigned int pkt_start = added;
327 if (likely(pktp + 1 != pktp_end))
328 rte_mbuf_prefetch_part1(pktp[1]);
330 if (sfc_ef100_tx_pkt_descs_max(m_seg) > dma_desc_space) {
334 /* Push already prepared descriptors before polling */
335 if (added != txq->added) {
336 sfc_ef100_tx_qpush(txq, added);
340 sfc_ef100_tx_reap(txq);
342 dma_desc_space = txq->max_fill_level -
343 (added - txq->completed);
344 if (sfc_ef100_tx_pkt_descs_max(m_seg) > dma_desc_space)
348 id = added++ & txq->ptr_mask;
349 sfc_ef100_tx_qdesc_send_create(m_seg, &txq->txq_hw_ring[id]);
352 * rte_pktmbuf_free() is commonly used in DPDK for
353 * recycling packets - the function checks every
354 * segment's reference counter and returns the
355 * buffer to its pool whenever possible;
356 * nevertheless, freeing mbuf segments one by one
357 * may entail some performance decline;
358 * from this point, sfc_efx_tx_reap() does the same job
359 * on its own and frees buffers in bulks (all mbufs
360 * within a bulk belong to the same pool);
361 * from this perspective, individual segment pointers
362 * must be associated with the corresponding SW
363 * descriptors independently so that only one loop
364 * is sufficient on reap to inspect all the buffers
366 txq->sw_ring[id].mbuf = m_seg;
368 while ((m_seg = m_seg->next) != NULL) {
369 RTE_BUILD_BUG_ON(SFC_MBUF_SEG_LEN_MAX >
370 SFC_EF100_TX_SEG_DESC_LEN_MAX);
372 id = added++ & txq->ptr_mask;
373 sfc_ef100_tx_qdesc_seg_create(rte_mbuf_data_iova(m_seg),
374 rte_pktmbuf_data_len(m_seg),
375 &txq->txq_hw_ring[id]);
376 txq->sw_ring[id].mbuf = m_seg;
379 dma_desc_space -= (added - pkt_start);
382 if (likely(added != txq->added)) {
383 sfc_ef100_tx_qpush(txq, added);
387 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
389 sfc_ef100_tx_reap(txq);
392 return pktp - &tx_pkts[0];
395 static sfc_dp_tx_get_dev_info_t sfc_ef100_get_dev_info;
397 sfc_ef100_get_dev_info(struct rte_eth_dev_info *dev_info)
400 * Number of descriptors just defines maximum number of pushed
401 * descriptors (fill level).
403 dev_info->tx_desc_lim.nb_min = 1;
404 dev_info->tx_desc_lim.nb_align = 1;
407 static sfc_dp_tx_qsize_up_rings_t sfc_ef100_tx_qsize_up_rings;
409 sfc_ef100_tx_qsize_up_rings(uint16_t nb_tx_desc,
410 struct sfc_dp_tx_hw_limits *limits,
411 unsigned int *txq_entries,
412 unsigned int *evq_entries,
413 unsigned int *txq_max_fill_level)
416 * rte_ethdev API guarantees that the number meets min, max and
417 * alignment requirements.
419 if (nb_tx_desc <= limits->txq_min_entries)
420 *txq_entries = limits->txq_min_entries;
422 *txq_entries = rte_align32pow2(nb_tx_desc);
424 *evq_entries = *txq_entries;
426 *txq_max_fill_level = RTE_MIN(nb_tx_desc,
427 SFC_EF100_TXQ_LIMIT(*evq_entries));
431 static sfc_dp_tx_qcreate_t sfc_ef100_tx_qcreate;
433 sfc_ef100_tx_qcreate(uint16_t port_id, uint16_t queue_id,
434 const struct rte_pci_addr *pci_addr, int socket_id,
435 const struct sfc_dp_tx_qcreate_info *info,
436 struct sfc_dp_txq **dp_txqp)
438 struct sfc_ef100_txq *txq;
442 if (info->txq_entries != info->evq_entries)
446 txq = rte_zmalloc_socket("sfc-ef100-txq", sizeof(*txq),
447 RTE_CACHE_LINE_SIZE, socket_id);
451 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
454 txq->sw_ring = rte_calloc_socket("sfc-ef100-txq-sw_ring",
456 sizeof(*txq->sw_ring),
457 RTE_CACHE_LINE_SIZE, socket_id);
458 if (txq->sw_ring == NULL)
459 goto fail_sw_ring_alloc;
461 txq->flags = SFC_EF100_TXQ_NOT_RUNNING;
462 txq->ptr_mask = info->txq_entries - 1;
463 txq->max_fill_level = info->max_fill_level;
464 txq->free_thresh = info->free_thresh;
465 txq->evq_phase_bit_shift = rte_bsf32(info->evq_entries);
466 txq->txq_hw_ring = info->txq_hw_ring;
467 txq->doorbell = (volatile uint8_t *)info->mem_bar +
468 ER_GZ_TX_RING_DOORBELL_OFST +
469 (info->hw_index << info->vi_window_shift);
470 txq->evq_hw_ring = info->evq_hw_ring;
472 sfc_ef100_tx_debug(txq, "TxQ doorbell is %p", txq->doorbell);
485 static sfc_dp_tx_qdestroy_t sfc_ef100_tx_qdestroy;
487 sfc_ef100_tx_qdestroy(struct sfc_dp_txq *dp_txq)
489 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
491 rte_free(txq->sw_ring);
495 static sfc_dp_tx_qstart_t sfc_ef100_tx_qstart;
497 sfc_ef100_tx_qstart(struct sfc_dp_txq *dp_txq, unsigned int evq_read_ptr,
498 unsigned int txq_desc_index)
500 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
502 txq->evq_read_ptr = evq_read_ptr;
503 txq->added = txq->completed = txq_desc_index;
505 txq->flags |= SFC_EF100_TXQ_STARTED;
506 txq->flags &= ~(SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION);
511 static sfc_dp_tx_qstop_t sfc_ef100_tx_qstop;
513 sfc_ef100_tx_qstop(struct sfc_dp_txq *dp_txq, unsigned int *evq_read_ptr)
515 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
517 txq->flags |= SFC_EF100_TXQ_NOT_RUNNING;
519 *evq_read_ptr = txq->evq_read_ptr;
522 static sfc_dp_tx_qtx_ev_t sfc_ef100_tx_qtx_ev;
524 sfc_ef100_tx_qtx_ev(struct sfc_dp_txq *dp_txq, unsigned int num_descs)
526 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
528 SFC_ASSERT(txq->flags & SFC_EF100_TXQ_NOT_RUNNING);
530 sfc_ef100_tx_reap_num_descs(txq, num_descs);
535 static sfc_dp_tx_qreap_t sfc_ef100_tx_qreap;
537 sfc_ef100_tx_qreap(struct sfc_dp_txq *dp_txq)
539 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
540 unsigned int completed;
542 for (completed = txq->completed; completed != txq->added; ++completed) {
543 struct sfc_ef100_tx_sw_desc *txd;
545 txd = &txq->sw_ring[completed & txq->ptr_mask];
546 if (txd->mbuf != NULL) {
547 rte_pktmbuf_free_seg(txd->mbuf);
552 txq->flags &= ~SFC_EF100_TXQ_STARTED;
556 sfc_ef100_tx_qdesc_npending(struct sfc_ef100_txq *txq)
558 const unsigned int evq_old_read_ptr = txq->evq_read_ptr;
559 unsigned int npending = 0;
562 if (unlikely(txq->flags &
563 (SFC_EF100_TXQ_NOT_RUNNING | SFC_EF100_TXQ_EXCEPTION)))
566 while (sfc_ef100_tx_get_event(txq, &tx_ev))
567 npending += EFX_QWORD_FIELD(tx_ev, ESF_GZ_EV_TXCMPL_NUM_DESC);
570 * The function does not process events, so return event queue read
571 * pointer to the original position to allow the events that were
572 * read to be processed later
574 txq->evq_read_ptr = evq_old_read_ptr;
579 static sfc_dp_tx_qdesc_status_t sfc_ef100_tx_qdesc_status;
581 sfc_ef100_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
583 struct sfc_ef100_txq *txq = sfc_ef100_txq_by_dp_txq(dp_txq);
584 unsigned int pushed = txq->added - txq->completed;
586 if (unlikely(offset > txq->ptr_mask))
589 if (unlikely(offset >= txq->max_fill_level))
590 return RTE_ETH_TX_DESC_UNAVAIL;
592 return (offset >= pushed ||
593 offset < sfc_ef100_tx_qdesc_npending(txq)) ?
594 RTE_ETH_TX_DESC_DONE : RTE_ETH_TX_DESC_FULL;
597 struct sfc_dp_tx sfc_ef100_tx = {
599 .name = SFC_KVARG_DATAPATH_EF100,
601 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF100,
603 .features = SFC_DP_TX_FEAT_MULTI_PROCESS,
604 .dev_offload_capa = 0,
605 .queue_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
606 DEV_TX_OFFLOAD_UDP_CKSUM |
607 DEV_TX_OFFLOAD_TCP_CKSUM |
608 DEV_TX_OFFLOAD_MULTI_SEGS,
609 .get_dev_info = sfc_ef100_get_dev_info,
610 .qsize_up_rings = sfc_ef100_tx_qsize_up_rings,
611 .qcreate = sfc_ef100_tx_qcreate,
612 .qdestroy = sfc_ef100_tx_qdestroy,
613 .qstart = sfc_ef100_tx_qstart,
614 .qtx_ev = sfc_ef100_tx_qtx_ev,
615 .qstop = sfc_ef100_tx_qstop,
616 .qreap = sfc_ef100_tx_qreap,
617 .qdesc_status = sfc_ef100_tx_qdesc_status,
618 .pkt_prepare = sfc_ef100_tx_prepare_pkts,
619 .pkt_burst = sfc_ef100_xmit_pkts,