4 * Copyright (c) 2016 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 /* EF10 native datapath implementation */
36 #include <rte_byteorder.h>
37 #include <rte_mbuf_ptype.h>
42 #include "efx_types.h"
44 #include "efx_regs_ef10.h"
46 #include "sfc_tweak.h"
47 #include "sfc_dp_rx.h"
48 #include "sfc_kvargs.h"
51 #define sfc_ef10_rx_err(dpq, ...) \
52 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, ERR, dpq, __VA_ARGS__)
55 * Alignment requirement for value written to RX WPTR:
56 * the WPTR must be aligned to an 8 descriptor boundary.
58 #define SFC_EF10_RX_WPTR_ALIGN 8
61 * Maximum number of descriptors/buffers in the Rx ring.
62 * It should guarantee that corresponding event queue never overfill.
63 * EF10 native datapath uses event queue of the same size as Rx queue.
64 * Maximum number of events on datapath can be estimated as number of
65 * Rx queue entries (one event per Rx buffer in the worst case) plus
66 * Rx error and flush events.
68 #define SFC_EF10_RXQ_LIMIT(_ndesc) \
69 ((_ndesc) - 1 /* head must not step on tail */ - \
70 (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
71 1 /* Rx error */ - 1 /* flush */)
73 struct sfc_ef10_rx_sw_desc {
74 struct rte_mbuf *mbuf;
78 /* Used on data path */
80 #define SFC_EF10_RXQ_STARTED 0x1
81 #define SFC_EF10_RXQ_NOT_RUNNING 0x2
82 #define SFC_EF10_RXQ_EXCEPTION 0x4
83 #define SFC_EF10_RXQ_RSS_HASH 0x8
84 unsigned int ptr_mask;
85 unsigned int prepared;
86 unsigned int completed;
87 unsigned int evq_read_ptr;
88 efx_qword_t *evq_hw_ring;
89 struct sfc_ef10_rx_sw_desc *sw_ring;
96 unsigned int refill_threshold;
97 struct rte_mempool *refill_mb_pool;
98 efx_qword_t *rxq_hw_ring;
99 volatile void *doorbell;
101 /* Datapath receive queue anchor */
102 struct sfc_dp_rxq dp;
105 static inline struct sfc_ef10_rxq *
106 sfc_ef10_rxq_by_dp_rxq(struct sfc_dp_rxq *dp_rxq)
108 return container_of(dp_rxq, struct sfc_ef10_rxq, dp);
112 sfc_ef10_rx_qpush(struct sfc_ef10_rxq *rxq)
116 /* Hardware has alignment restriction for WPTR */
117 RTE_BUILD_BUG_ON(SFC_RX_REFILL_BULK % SFC_EF10_RX_WPTR_ALIGN != 0);
118 SFC_ASSERT(RTE_ALIGN(rxq->added, SFC_EF10_RX_WPTR_ALIGN) == rxq->added);
120 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR,
121 rxq->added & rxq->ptr_mask);
123 /* DMA sync to device is not required */
126 * rte_write32() has rte_io_wmb() which guarantees that the STORE
127 * operations (i.e. Rx and event descriptor updates) that precede
128 * the rte_io_wmb() call are visible to NIC before the STORE
129 * operations that follow it (i.e. doorbell write).
131 rte_write32(dword.ed_u32[0], rxq->doorbell);
135 sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq)
137 const unsigned int ptr_mask = rxq->ptr_mask;
138 const uint32_t buf_size = rxq->buf_size;
139 unsigned int free_space;
141 void *objs[SFC_RX_REFILL_BULK];
142 unsigned int added = rxq->added;
144 free_space = SFC_EF10_RXQ_LIMIT(ptr_mask + 1) -
145 (added - rxq->completed);
147 if (free_space < rxq->refill_threshold)
150 bulks = free_space / RTE_DIM(objs);
151 /* refill_threshold guarantees that bulks is positive */
152 SFC_ASSERT(bulks > 0);
158 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
159 RTE_DIM(objs)) < 0)) {
160 struct rte_eth_dev_data *dev_data =
161 rte_eth_devices[rxq->dp.dpq.port_id].data;
164 * It is hardly a safe way to increment counter
165 * from different contexts, but all PMDs do it.
167 dev_data->rx_mbuf_alloc_failed += RTE_DIM(objs);
168 /* Return if we have posted nothing yet */
169 if (added == rxq->added)
175 for (i = 0, id = added & ptr_mask;
178 struct rte_mbuf *m = objs[i];
179 struct sfc_ef10_rx_sw_desc *rxd;
180 rte_iova_t phys_addr;
182 SFC_ASSERT((id & ~ptr_mask) == 0);
183 rxd = &rxq->sw_ring[id];
187 * Avoid writing to mbuf. It is cheaper to do it
188 * when we receive packet and fill in nearby
192 phys_addr = rte_mbuf_data_iova_default(m);
193 EFX_POPULATE_QWORD_2(rxq->rxq_hw_ring[id],
194 ESF_DZ_RX_KER_BYTE_CNT, buf_size,
195 ESF_DZ_RX_KER_BUF_ADDR, phys_addr);
198 added += RTE_DIM(objs);
199 } while (--bulks > 0);
201 SFC_ASSERT(rxq->added != added);
203 sfc_ef10_rx_qpush(rxq);
207 sfc_ef10_rx_prefetch_next(struct sfc_ef10_rxq *rxq, unsigned int next_id)
209 struct rte_mbuf *next_mbuf;
211 /* Prefetch next bunch of software descriptors */
212 if ((next_id % (RTE_CACHE_LINE_SIZE / sizeof(rxq->sw_ring[0]))) == 0)
213 rte_prefetch0(&rxq->sw_ring[next_id]);
216 * It looks strange to prefetch depending on previous prefetch
217 * data, but measurements show that it is really efficient and
218 * increases packet rate.
220 next_mbuf = rxq->sw_ring[next_id].mbuf;
221 if (likely(next_mbuf != NULL)) {
222 /* Prefetch the next mbuf structure */
223 rte_mbuf_prefetch_part1(next_mbuf);
225 /* Prefetch pseudo header of the next packet */
226 /* data_off is not filled in yet */
227 /* Yes, data could be not ready yet, but we hope */
228 rte_prefetch0((uint8_t *)next_mbuf->buf_addr +
229 RTE_PKTMBUF_HEADROOM);
234 sfc_ef10_rx_prepared(struct sfc_ef10_rxq *rxq, struct rte_mbuf **rx_pkts,
237 uint16_t n_rx_pkts = RTE_MIN(nb_pkts, rxq->prepared);
238 unsigned int completed = rxq->completed;
241 rxq->prepared -= n_rx_pkts;
242 rxq->completed = completed + n_rx_pkts;
244 for (i = 0; i < n_rx_pkts; ++i, ++completed)
245 rx_pkts[i] = rxq->sw_ring[completed & rxq->ptr_mask].mbuf;
251 sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev,
254 uint32_t tun_ptype = 0;
255 /* Which event bit is mapped to PKT_RX_IP_CKSUM_* */
256 int8_t ip_csum_err_bit;
257 /* Which event bit is mapped to PKT_RX_L4_CKSUM_* */
258 int8_t l4_csum_err_bit;
259 uint32_t l2_ptype = 0;
260 uint32_t l3_ptype = 0;
261 uint32_t l4_ptype = 0;
262 uint64_t ol_flags = 0;
264 if (unlikely(EFX_TEST_QWORD_BIT(rx_ev, ESF_DZ_RX_PARSE_INCOMPLETE_LBN)))
267 switch (EFX_QWORD_FIELD(rx_ev, ESF_EZ_RX_ENCAP_HDR)) {
269 /* Unexpected encapsulation tag class */
272 case ESE_EZ_ENCAP_HDR_NONE:
274 case ESE_EZ_ENCAP_HDR_VXLAN:
276 * It is definitely UDP, but we have no information
277 * about IPv4 vs IPv6 and VLAN tagging.
279 tun_ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP;
281 case ESE_EZ_ENCAP_HDR_GRE:
283 * We have no information about IPv4 vs IPv6 and VLAN tagging.
285 tun_ptype = RTE_PTYPE_TUNNEL_NVGRE;
289 if (tun_ptype == 0) {
290 ip_csum_err_bit = ESF_DZ_RX_IPCKSUM_ERR_LBN;
291 l4_csum_err_bit = ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN;
293 ip_csum_err_bit = ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN;
294 l4_csum_err_bit = ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN;
295 if (unlikely(EFX_TEST_QWORD_BIT(rx_ev,
296 ESF_DZ_RX_IPCKSUM_ERR_LBN)))
297 ol_flags |= PKT_RX_EIP_CKSUM_BAD;
300 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) {
301 case ESE_DZ_ETH_TAG_CLASS_NONE:
302 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER :
303 RTE_PTYPE_INNER_L2_ETHER;
305 case ESE_DZ_ETH_TAG_CLASS_VLAN1:
306 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_VLAN :
307 RTE_PTYPE_INNER_L2_ETHER_VLAN;
309 case ESE_DZ_ETH_TAG_CLASS_VLAN2:
310 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_QINQ :
311 RTE_PTYPE_INNER_L2_ETHER_QINQ;
314 /* Unexpected Eth tag class */
318 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L3_CLASS)) {
319 case ESE_DZ_L3_CLASS_IP4_FRAG:
320 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
321 RTE_PTYPE_INNER_L4_FRAG;
323 case ESE_DZ_L3_CLASS_IP4:
324 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN :
325 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
326 ol_flags |= PKT_RX_RSS_HASH |
327 ((EFX_TEST_QWORD_BIT(rx_ev, ip_csum_err_bit)) ?
328 PKT_RX_IP_CKSUM_BAD : PKT_RX_IP_CKSUM_GOOD);
330 case ESE_DZ_L3_CLASS_IP6_FRAG:
331 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
332 RTE_PTYPE_INNER_L4_FRAG;
334 case ESE_DZ_L3_CLASS_IP6:
335 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
336 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
337 ol_flags |= PKT_RX_RSS_HASH;
339 case ESE_DZ_L3_CLASS_ARP:
340 /* Override Layer 2 packet type */
341 /* There is no ARP classification for inner packets */
343 l2_ptype = RTE_PTYPE_L2_ETHER_ARP;
346 /* Unexpected Layer 3 class */
350 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L4_CLASS)) {
351 case ESE_DZ_L4_CLASS_TCP:
352 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :
353 RTE_PTYPE_INNER_L4_TCP;
355 (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
356 PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
358 case ESE_DZ_L4_CLASS_UDP:
359 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :
360 RTE_PTYPE_INNER_L4_UDP;
362 (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
363 PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
365 case ESE_DZ_L4_CLASS_UNKNOWN:
368 /* Unexpected Layer 4 class */
372 /* Remove RSS hash offload flag if RSS is not enabled */
373 if (~rxq->flags & SFC_EF10_RXQ_RSS_HASH)
374 ol_flags &= ~PKT_RX_RSS_HASH;
377 m->ol_flags = ol_flags;
378 m->packet_type = tun_ptype | l2_ptype | l3_ptype | l4_ptype;
382 sfc_ef10_rx_pseudo_hdr_get_len(const uint8_t *pseudo_hdr)
384 return rte_le_to_cpu_16(*(const uint16_t *)&pseudo_hdr[8]);
388 sfc_ef10_rx_pseudo_hdr_get_hash(const uint8_t *pseudo_hdr)
390 return rte_le_to_cpu_32(*(const uint32_t *)pseudo_hdr);
394 sfc_ef10_rx_process_event(struct sfc_ef10_rxq *rxq, efx_qword_t rx_ev,
395 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
397 const unsigned int ptr_mask = rxq->ptr_mask;
398 unsigned int completed = rxq->completed;
400 struct sfc_ef10_rx_sw_desc *rxd;
404 const uint8_t *pseudo_hdr;
407 ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) - completed) &
408 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
409 SFC_ASSERT(ready > 0);
411 if (rx_ev.eq_u64[0] &
412 rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) |
413 (1ull << ESF_DZ_RX_ECRC_ERR_LBN))) {
414 SFC_ASSERT(rxq->prepared == 0);
415 rxq->completed += ready;
416 while (ready-- > 0) {
417 rxd = &rxq->sw_ring[completed++ & ptr_mask];
418 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
423 n_rx_pkts = RTE_MIN(ready, nb_pkts);
424 rxq->prepared = ready - n_rx_pkts;
425 rxq->completed += n_rx_pkts;
427 rxd = &rxq->sw_ring[completed++ & ptr_mask];
429 sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
435 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) != sizeof(rxq->rearm_data));
436 m->rearm_data[0] = rxq->rearm_data;
438 /* Classify packet based on Rx event */
439 sfc_ef10_rx_ev_to_offloads(rxq, rx_ev, m);
441 /* data_off already moved past pseudo header */
442 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
445 * Always get RSS hash from pseudo header to avoid
446 * condition/branching. If it is valid or not depends on
447 * PKT_RX_RSS_HASH in m->ol_flags.
449 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
452 pkt_len = EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_BYTES) -
455 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
456 SFC_ASSERT(pkt_len > 0);
457 rte_pktmbuf_data_len(m) = pkt_len;
458 rte_pktmbuf_pkt_len(m) = pkt_len;
460 SFC_ASSERT(m->next == NULL);
462 /* Remember mbuf to copy offload flags and packet type from */
464 for (--ready; ready > 0; --ready) {
465 rxd = &rxq->sw_ring[completed++ & ptr_mask];
467 sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
471 if (ready > rxq->prepared)
474 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) !=
475 sizeof(rxq->rearm_data));
476 m->rearm_data[0] = rxq->rearm_data;
478 /* Event-dependent information is the same */
479 m->ol_flags = m0->ol_flags;
480 m->packet_type = m0->packet_type;
482 /* data_off already moved past pseudo header */
483 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
486 * Always get RSS hash from pseudo header to avoid
487 * condition/branching. If it is valid or not depends on
488 * PKT_RX_RSS_HASH in m->ol_flags.
490 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
492 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
493 SFC_ASSERT(pkt_len > 0);
494 rte_pktmbuf_data_len(m) = pkt_len;
495 rte_pktmbuf_pkt_len(m) = pkt_len;
497 SFC_ASSERT(m->next == NULL);
504 sfc_ef10_rx_get_event(struct sfc_ef10_rxq *rxq, efx_qword_t *rx_ev)
506 *rx_ev = rxq->evq_hw_ring[rxq->evq_read_ptr & rxq->ptr_mask];
508 if (!sfc_ef10_ev_present(*rx_ev))
511 if (unlikely(EFX_QWORD_FIELD(*rx_ev, FSF_AZ_EV_CODE) !=
512 FSE_AZ_EV_CODE_RX_EV)) {
514 * Do not move read_ptr to keep the event for exception
515 * handling by the control path.
517 rxq->flags |= SFC_EF10_RXQ_EXCEPTION;
518 sfc_ef10_rx_err(&rxq->dp.dpq,
519 "RxQ exception at EvQ read ptr %#x",
529 sfc_ef10_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
531 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(rx_queue);
532 unsigned int evq_old_read_ptr;
536 if (unlikely(rxq->flags &
537 (SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION)))
540 n_rx_pkts = sfc_ef10_rx_prepared(rxq, rx_pkts, nb_pkts);
542 evq_old_read_ptr = rxq->evq_read_ptr;
543 while (n_rx_pkts != nb_pkts && sfc_ef10_rx_get_event(rxq, &rx_ev)) {
545 * DROP_EVENT is an internal to the NIC, software should
546 * never see it and, therefore, may ignore it.
549 n_rx_pkts += sfc_ef10_rx_process_event(rxq, rx_ev,
551 nb_pkts - n_rx_pkts);
554 sfc_ef10_ev_qclear(rxq->evq_hw_ring, rxq->ptr_mask, evq_old_read_ptr,
557 /* It is not a problem if we refill in the case of exception */
558 sfc_ef10_rx_qrefill(rxq);
563 static const uint32_t *
564 sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps)
566 static const uint32_t ef10_native_ptypes[] = {
568 RTE_PTYPE_L2_ETHER_ARP,
569 RTE_PTYPE_L2_ETHER_VLAN,
570 RTE_PTYPE_L2_ETHER_QINQ,
571 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
572 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
578 static const uint32_t ef10_overlay_ptypes[] = {
580 RTE_PTYPE_L2_ETHER_ARP,
581 RTE_PTYPE_L2_ETHER_VLAN,
582 RTE_PTYPE_L2_ETHER_QINQ,
583 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
584 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
588 RTE_PTYPE_TUNNEL_VXLAN,
589 RTE_PTYPE_TUNNEL_NVGRE,
590 RTE_PTYPE_INNER_L2_ETHER,
591 RTE_PTYPE_INNER_L2_ETHER_VLAN,
592 RTE_PTYPE_INNER_L2_ETHER_QINQ,
593 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
594 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
595 RTE_PTYPE_INNER_L4_FRAG,
596 RTE_PTYPE_INNER_L4_TCP,
597 RTE_PTYPE_INNER_L4_UDP,
602 * The function returns static set of supported packet types,
603 * so we can't build it dynamically based on supported tunnel
604 * encapsulations and should limit to known sets.
606 switch (tunnel_encaps) {
607 case (1u << EFX_TUNNEL_PROTOCOL_VXLAN |
608 1u << EFX_TUNNEL_PROTOCOL_GENEVE |
609 1u << EFX_TUNNEL_PROTOCOL_NVGRE):
610 return ef10_overlay_ptypes;
613 "Unexpected set of supported tunnel encapsulations: %#x\n",
617 return ef10_native_ptypes;
621 static sfc_dp_rx_qdesc_npending_t sfc_ef10_rx_qdesc_npending;
623 sfc_ef10_rx_qdesc_npending(__rte_unused struct sfc_dp_rxq *dp_rxq)
626 * Correct implementation requires EvQ polling and events
627 * processing (keeping all ready mbufs in prepared).
632 static sfc_dp_rx_qdesc_status_t sfc_ef10_rx_qdesc_status;
634 sfc_ef10_rx_qdesc_status(__rte_unused struct sfc_dp_rxq *dp_rxq,
635 __rte_unused uint16_t offset)
641 static sfc_dp_rx_qsize_up_rings_t sfc_ef10_rx_qsize_up_rings;
643 sfc_ef10_rx_qsize_up_rings(uint16_t nb_rx_desc,
644 unsigned int *rxq_entries,
645 unsigned int *evq_entries,
646 unsigned int *rxq_max_fill_level)
648 *rxq_entries = nb_rx_desc;
649 *evq_entries = nb_rx_desc;
650 *rxq_max_fill_level = SFC_EF10_RXQ_LIMIT(*rxq_entries);
656 sfc_ef10_mk_mbuf_rearm_data(uint16_t port_id, uint16_t prefix_size)
660 memset(&m, 0, sizeof(m));
662 rte_mbuf_refcnt_set(&m, 1);
663 m.data_off = RTE_PKTMBUF_HEADROOM + prefix_size;
667 /* rearm_data covers structure members filled in above */
668 rte_compiler_barrier();
669 RTE_BUILD_BUG_ON(sizeof(m.rearm_data[0]) != sizeof(uint64_t));
670 return m.rearm_data[0];
673 static sfc_dp_rx_qcreate_t sfc_ef10_rx_qcreate;
675 sfc_ef10_rx_qcreate(uint16_t port_id, uint16_t queue_id,
676 const struct rte_pci_addr *pci_addr, int socket_id,
677 const struct sfc_dp_rx_qcreate_info *info,
678 struct sfc_dp_rxq **dp_rxqp)
680 struct sfc_ef10_rxq *rxq;
684 if (info->rxq_entries != info->evq_entries)
688 rxq = rte_zmalloc_socket("sfc-ef10-rxq", sizeof(*rxq),
689 RTE_CACHE_LINE_SIZE, socket_id);
693 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
696 rxq->sw_ring = rte_calloc_socket("sfc-ef10-rxq-sw_ring",
698 sizeof(*rxq->sw_ring),
699 RTE_CACHE_LINE_SIZE, socket_id);
700 if (rxq->sw_ring == NULL)
701 goto fail_desc_alloc;
703 rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
704 if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
705 rxq->flags |= SFC_EF10_RXQ_RSS_HASH;
706 rxq->ptr_mask = info->rxq_entries - 1;
707 rxq->evq_hw_ring = info->evq_hw_ring;
708 rxq->refill_threshold = info->refill_threshold;
710 sfc_ef10_mk_mbuf_rearm_data(port_id, info->prefix_size);
711 rxq->prefix_size = info->prefix_size;
712 rxq->buf_size = info->buf_size;
713 rxq->refill_mb_pool = info->refill_mb_pool;
714 rxq->rxq_hw_ring = info->rxq_hw_ring;
715 rxq->doorbell = (volatile uint8_t *)info->mem_bar +
716 ER_DZ_RX_DESC_UPD_REG_OFST +
717 info->hw_index * ER_DZ_RX_DESC_UPD_REG_STEP;
730 static sfc_dp_rx_qdestroy_t sfc_ef10_rx_qdestroy;
732 sfc_ef10_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
734 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
736 rte_free(rxq->sw_ring);
740 static sfc_dp_rx_qstart_t sfc_ef10_rx_qstart;
742 sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
744 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
747 rxq->completed = rxq->added = 0;
749 sfc_ef10_rx_qrefill(rxq);
751 rxq->evq_read_ptr = evq_read_ptr;
753 rxq->flags |= SFC_EF10_RXQ_STARTED;
754 rxq->flags &= ~(SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION);
759 static sfc_dp_rx_qstop_t sfc_ef10_rx_qstop;
761 sfc_ef10_rx_qstop(struct sfc_dp_rxq *dp_rxq, unsigned int *evq_read_ptr)
763 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
765 rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
767 *evq_read_ptr = rxq->evq_read_ptr;
770 static sfc_dp_rx_qrx_ev_t sfc_ef10_rx_qrx_ev;
772 sfc_ef10_rx_qrx_ev(struct sfc_dp_rxq *dp_rxq, __rte_unused unsigned int id)
774 __rte_unused struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
776 SFC_ASSERT(rxq->flags & SFC_EF10_RXQ_NOT_RUNNING);
779 * It is safe to ignore Rx event since we free all mbufs on
780 * queue purge anyway.
786 static sfc_dp_rx_qpurge_t sfc_ef10_rx_qpurge;
788 sfc_ef10_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
790 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
792 struct sfc_ef10_rx_sw_desc *rxd;
794 for (i = rxq->completed; i != rxq->added; ++i) {
795 rxd = &rxq->sw_ring[i & rxq->ptr_mask];
796 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
800 rxq->flags &= ~SFC_EF10_RXQ_STARTED;
803 struct sfc_dp_rx sfc_ef10_rx = {
805 .name = SFC_KVARG_DATAPATH_EF10,
807 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF10,
809 .features = SFC_DP_RX_FEAT_MULTI_PROCESS |
810 SFC_DP_RX_FEAT_TUNNELS,
811 .qsize_up_rings = sfc_ef10_rx_qsize_up_rings,
812 .qcreate = sfc_ef10_rx_qcreate,
813 .qdestroy = sfc_ef10_rx_qdestroy,
814 .qstart = sfc_ef10_rx_qstart,
815 .qstop = sfc_ef10_rx_qstop,
816 .qrx_ev = sfc_ef10_rx_qrx_ev,
817 .qpurge = sfc_ef10_rx_qpurge,
818 .supported_ptypes_get = sfc_ef10_supported_ptypes_get,
819 .qdesc_npending = sfc_ef10_rx_qdesc_npending,
820 .qdesc_status = sfc_ef10_rx_qdesc_status,
821 .pkt_burst = sfc_ef10_recv_pkts,