drivers/net/sfc/sfc_ef10_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2016-2019 Solarflare Communications Inc.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 /* EF10 native datapath implementation */
  11
  12 #include <stdbool.h>
  13
  14 #include <rte_byteorder.h>
  15 #include <rte_mbuf_ptype.h>
  16 #include <rte_mbuf.h>
  17 #include <rte_io.h>
  18
  19 #include "efx.h"
  20 #include "efx_types.h"
  21 #include "efx_regs.h"
  22 #include "efx_regs_ef10.h"
  23
  24 #include "sfc_debug.h"
  25 #include "sfc_tweak.h"
  26 #include "sfc_dp_rx.h"
  27 #include "sfc_kvargs.h"
  28 #include "sfc_ef10.h"
  29
  30 #define SFC_EF10_RX_EV_ENCAP_SUPPORT    1
  31 #include "sfc_ef10_rx_ev.h"
  32
  33 #define sfc_ef10_rx_err(dpq, ...) \
  34         SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, ERR, dpq, __VA_ARGS__)
  35
  36 #define sfc_ef10_rx_info(dpq, ...) \
  37         SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, INFO, dpq, __VA_ARGS__)
  38
  39 /**
  40  * Maximum number of descriptors/buffers in the Rx ring.
  41  * It should guarantee that corresponding event queue never overfill.
  42  * EF10 native datapath uses event queue of the same size as Rx queue.
  43  * Maximum number of events on datapath can be estimated as number of
  44  * Rx queue entries (one event per Rx buffer in the worst case) plus
  45  * Rx error and flush events.
  46  */
  47 #define SFC_EF10_RXQ_LIMIT(_ndesc) \
  48         ((_ndesc) - 1 /* head must not step on tail */ - \
  49          (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
  50          1 /* Rx error */ - 1 /* flush */)
  51
  52 struct sfc_ef10_rx_sw_desc {
  53         struct rte_mbuf                 *mbuf;
  54 };
  55
  56 struct sfc_ef10_rxq {
  57         /* Used on data path */
  58         unsigned int                    flags;
  59 #define SFC_EF10_RXQ_STARTED            0x1
  60 #define SFC_EF10_RXQ_NOT_RUNNING        0x2
  61 #define SFC_EF10_RXQ_EXCEPTION          0x4
  62 #define SFC_EF10_RXQ_RSS_HASH           0x8
  63 #define SFC_EF10_RXQ_FLAG_INTR_EN       0x10
  64         unsigned int                    ptr_mask;
  65         unsigned int                    pending;
  66         unsigned int                    completed;
  67         unsigned int                    evq_read_ptr;
  68         unsigned int                    evq_read_ptr_primed;
  69         efx_qword_t                     *evq_hw_ring;
  70         struct sfc_ef10_rx_sw_desc      *sw_ring;
  71         uint64_t                        rearm_data;
  72         struct rte_mbuf                 *scatter_pkt;
  73         volatile void                   *evq_prime;
  74         uint16_t                        prefix_size;
  75
  76         /* Used on refill */
  77         uint16_t                        buf_size;
  78         unsigned int                    added;
  79         unsigned int                    max_fill_level;
  80         unsigned int                    refill_threshold;
  81         struct rte_mempool              *refill_mb_pool;
  82         efx_qword_t                     *rxq_hw_ring;
  83         volatile void                   *doorbell;
  84
  85         /* Datapath receive queue anchor */
  86         struct sfc_dp_rxq               dp;
  87 };
  88
  89 static inline struct sfc_ef10_rxq *
  90 sfc_ef10_rxq_by_dp_rxq(struct sfc_dp_rxq *dp_rxq)
  91 {
  92         return container_of(dp_rxq, struct sfc_ef10_rxq, dp);
  93 }
  94
  95 static void
  96 sfc_ef10_rx_qprime(struct sfc_ef10_rxq *rxq)
  97 {
  98         sfc_ef10_ev_qprime(rxq->evq_prime, rxq->evq_read_ptr, rxq->ptr_mask);
  99         rxq->evq_read_ptr_primed = rxq->evq_read_ptr;
 100 }
 101
 102 static void
 103 sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq)
 104 {
 105         const unsigned int ptr_mask = rxq->ptr_mask;
 106         const uint32_t buf_size = rxq->buf_size;
 107         unsigned int free_space;
 108         unsigned int bulks;
 109         void *objs[SFC_RX_REFILL_BULK];
 110         unsigned int added = rxq->added;
 111
 112         RTE_BUILD_BUG_ON(SFC_RX_REFILL_BULK % SFC_EF10_RX_WPTR_ALIGN != 0);
 113
 114         free_space = rxq->max_fill_level - (added - rxq->completed);
 115
 116         if (free_space < rxq->refill_threshold)
 117                 return;
 118
 119         bulks = free_space / RTE_DIM(objs);
 120         /* refill_threshold guarantees that bulks is positive */
 121         SFC_ASSERT(bulks > 0);
 122
 123         do {
 124                 unsigned int id;
 125                 unsigned int i;
 126
 127                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
 128                                                   RTE_DIM(objs)) < 0)) {
 129                         struct rte_eth_dev_data *dev_data =
 130                                 rte_eth_devices[rxq->dp.dpq.port_id].data;
 131
 132                         /*
 133                          * It is hardly a safe way to increment counter
 134                          * from different contexts, but all PMDs do it.
 135                          */
 136                         dev_data->rx_mbuf_alloc_failed += RTE_DIM(objs);
 137                         /* Return if we have posted nothing yet */
 138                         if (added == rxq->added)
 139                                 return;
 140                         /* Push posted */
 141                         break;
 142                 }
 143
 144                 for (i = 0, id = added & ptr_mask;
 145                      i < RTE_DIM(objs);
 146                      ++i, ++id) {
 147                         struct rte_mbuf *m = objs[i];
 148                         struct sfc_ef10_rx_sw_desc *rxd;
 149                         rte_iova_t phys_addr;
 150
 151                         MBUF_RAW_ALLOC_CHECK(m);
 152
 153                         SFC_ASSERT((id & ~ptr_mask) == 0);
 154                         rxd = &rxq->sw_ring[id];
 155                         rxd->mbuf = m;
 156
 157                         /*
 158                          * Avoid writing to mbuf. It is cheaper to do it
 159                          * when we receive packet and fill in nearby
 160                          * structure members.
 161                          */
 162
 163                         phys_addr = rte_mbuf_data_iova_default(m);
 164                         EFX_POPULATE_QWORD_2(rxq->rxq_hw_ring[id],
 165                             ESF_DZ_RX_KER_BYTE_CNT, buf_size,
 166                             ESF_DZ_RX_KER_BUF_ADDR, phys_addr);
 167                 }
 168
 169                 added += RTE_DIM(objs);
 170         } while (--bulks > 0);
 171
 172         SFC_ASSERT(rxq->added != added);
 173         rxq->added = added;
 174         sfc_ef10_rx_qpush(rxq->doorbell, added, ptr_mask);
 175 }
 176
 177 static void
 178 sfc_ef10_rx_prefetch_next(struct sfc_ef10_rxq *rxq, unsigned int next_id)
 179 {
 180         struct rte_mbuf *next_mbuf;
 181
 182         /* Prefetch next bunch of software descriptors */
 183         if ((next_id % (RTE_CACHE_LINE_SIZE / sizeof(rxq->sw_ring[0]))) == 0)
 184                 rte_prefetch0(&rxq->sw_ring[next_id]);
 185
 186         /*
 187          * It looks strange to prefetch depending on previous prefetch
 188          * data, but measurements show that it is really efficient and
 189          * increases packet rate.
 190          */
 191         next_mbuf = rxq->sw_ring[next_id].mbuf;
 192         if (likely(next_mbuf != NULL)) {
 193                 /* Prefetch the next mbuf structure */
 194                 rte_mbuf_prefetch_part1(next_mbuf);
 195
 196                 /* Prefetch pseudo header of the next packet */
 197                 /* data_off is not filled in yet */
 198                 /* Yes, data could be not ready yet, but we hope */
 199                 rte_prefetch0((uint8_t *)next_mbuf->buf_addr +
 200                               RTE_PKTMBUF_HEADROOM);
 201         }
 202 }
 203
 204 static struct rte_mbuf **
 205 sfc_ef10_rx_pending(struct sfc_ef10_rxq *rxq, struct rte_mbuf **rx_pkts,
 206                     uint16_t nb_pkts)
 207 {
 208         uint16_t n_rx_pkts = RTE_MIN(nb_pkts, rxq->pending - rxq->completed);
 209
 210         SFC_ASSERT(rxq->pending == rxq->completed || rxq->scatter_pkt == NULL);
 211
 212         if (n_rx_pkts != 0) {
 213                 unsigned int completed = rxq->completed;
 214
 215                 rxq->completed = completed + n_rx_pkts;
 216
 217                 do {
 218                         *rx_pkts++ =
 219                                 rxq->sw_ring[completed++ & rxq->ptr_mask].mbuf;
 220                 } while (completed != rxq->completed);
 221         }
 222
 223         return rx_pkts;
 224 }
 225
 226 static uint16_t
 227 sfc_ef10_rx_pseudo_hdr_get_len(const uint8_t *pseudo_hdr)
 228 {
 229         return rte_le_to_cpu_16(*(const uint16_t *)&pseudo_hdr[8]);
 230 }
 231
 232 static uint32_t
 233 sfc_ef10_rx_pseudo_hdr_get_hash(const uint8_t *pseudo_hdr)
 234 {
 235         return rte_le_to_cpu_32(*(const uint32_t *)pseudo_hdr);
 236 }
 237
 238 static struct rte_mbuf **
 239 sfc_ef10_rx_process_event(struct sfc_ef10_rxq *rxq, efx_qword_t rx_ev,
 240                           struct rte_mbuf **rx_pkts,
 241                           struct rte_mbuf ** const rx_pkts_end)
 242 {
 243         const unsigned int ptr_mask = rxq->ptr_mask;
 244         unsigned int pending = rxq->pending;
 245         unsigned int ready;
 246         struct sfc_ef10_rx_sw_desc *rxd;
 247         struct rte_mbuf *m;
 248         struct rte_mbuf *m0;
 249         const uint8_t *pseudo_hdr;
 250         uint16_t seg_len;
 251
 252         ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) - pending) &
 253                 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
 254
 255         if (ready == 0) {
 256                 /* Rx abort - it was no enough descriptors for Rx packet */
 257                 rte_pktmbuf_free(rxq->scatter_pkt);
 258                 rxq->scatter_pkt = NULL;
 259                 return rx_pkts;
 260         }
 261
 262         rxq->pending = pending + ready;
 263
 264         if (rx_ev.eq_u64[0] &
 265             rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) |
 266                              (1ull << ESF_DZ_RX_ECRC_ERR_LBN))) {
 267                 SFC_ASSERT(rxq->completed == pending);
 268                 do {
 269                         rxd = &rxq->sw_ring[pending++ & ptr_mask];
 270                         rte_mbuf_raw_free(rxd->mbuf);
 271                 } while (pending != rxq->pending);
 272                 rxq->completed = pending;
 273                 return rx_pkts;
 274         }
 275
 276         /* If scattered packet is in progress */
 277         if (rxq->scatter_pkt != NULL) {
 278                 /* Events for scattered packet frags are not merged */
 279                 SFC_ASSERT(ready == 1);
 280                 SFC_ASSERT(rxq->completed == pending);
 281
 282                 /* There is no pseudo-header in scatter segments. */
 283                 seg_len = EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_BYTES);
 284
 285                 rxd = &rxq->sw_ring[pending++ & ptr_mask];
 286                 m = rxd->mbuf;
 287
 288                 MBUF_RAW_ALLOC_CHECK(m);
 289
 290                 m->data_off = RTE_PKTMBUF_HEADROOM;
 291                 rte_pktmbuf_data_len(m) = seg_len;
 292                 rte_pktmbuf_pkt_len(m) = seg_len;
 293
 294                 rxq->scatter_pkt->nb_segs++;
 295                 rte_pktmbuf_pkt_len(rxq->scatter_pkt) += seg_len;
 296                 rte_pktmbuf_lastseg(rxq->scatter_pkt)->next = m;
 297
 298                 if (~rx_ev.eq_u64[0] &
 299                     rte_cpu_to_le_64(1ull << ESF_DZ_RX_CONT_LBN)) {
 300                         *rx_pkts++ = rxq->scatter_pkt;
 301                         rxq->scatter_pkt = NULL;
 302                 }
 303                 rxq->completed = pending;
 304                 return rx_pkts;
 305         }
 306
 307         rxd = &rxq->sw_ring[pending++ & ptr_mask];
 308
 309         sfc_ef10_rx_prefetch_next(rxq, pending & ptr_mask);
 310
 311         m = rxd->mbuf;
 312
 313         RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) != sizeof(rxq->rearm_data));
 314         m->rearm_data[0] = rxq->rearm_data;
 315
 316         /* Classify packet based on Rx event */
 317         /* Mask RSS hash offload flag if RSS is not enabled */
 318         sfc_ef10_rx_ev_to_offloads(rx_ev, m,
 319                                    (rxq->flags & SFC_EF10_RXQ_RSS_HASH) ?
 320                                    ~0ull : ~PKT_RX_RSS_HASH);
 321
 322         /* data_off already moved past pseudo header */
 323         pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
 324
 325         /*
 326          * Always get RSS hash from pseudo header to avoid
 327          * condition/branching. If it is valid or not depends on
 328          * PKT_RX_RSS_HASH in m->ol_flags.
 329          */
 330         m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
 331
 332         if (ready == 1)
 333                 seg_len = EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_BYTES) -
 334                         rxq->prefix_size;
 335         else
 336                 seg_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
 337         SFC_ASSERT(seg_len > 0);
 338         rte_pktmbuf_data_len(m) = seg_len;
 339         rte_pktmbuf_pkt_len(m) = seg_len;
 340
 341         SFC_ASSERT(m->next == NULL);
 342
 343         if (~rx_ev.eq_u64[0] & rte_cpu_to_le_64(1ull << ESF_DZ_RX_CONT_LBN)) {
 344                 *rx_pkts++ = m;
 345                 rxq->completed = pending;
 346         } else {
 347                 /* Events with CONT bit are not merged */
 348                 SFC_ASSERT(ready == 1);
 349                 rxq->scatter_pkt = m;
 350                 rxq->completed = pending;
 351                 return rx_pkts;
 352         }
 353
 354         /* Remember mbuf to copy offload flags and packet type from */
 355         m0 = m;
 356         while (pending != rxq->pending) {
 357                 rxd = &rxq->sw_ring[pending++ & ptr_mask];
 358
 359                 sfc_ef10_rx_prefetch_next(rxq, pending & ptr_mask);
 360
 361                 m = rxd->mbuf;
 362
 363                 if (rx_pkts != rx_pkts_end) {
 364                         *rx_pkts++ = m;
 365                         rxq->completed = pending;
 366                 }
 367
 368                 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) !=
 369                                  sizeof(rxq->rearm_data));
 370                 m->rearm_data[0] = rxq->rearm_data;
 371
 372                 /* Event-dependent information is the same */
 373                 m->ol_flags = m0->ol_flags;
 374                 m->packet_type = m0->packet_type;
 375
 376                 /* data_off already moved past pseudo header */
 377                 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
 378
 379                 /*
 380                  * Always get RSS hash from pseudo header to avoid
 381                  * condition/branching. If it is valid or not depends on
 382                  * PKT_RX_RSS_HASH in m->ol_flags.
 383                  */
 384                 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
 385
 386                 seg_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
 387                 SFC_ASSERT(seg_len > 0);
 388                 rte_pktmbuf_data_len(m) = seg_len;
 389                 rte_pktmbuf_pkt_len(m) = seg_len;
 390
 391                 SFC_ASSERT(m->next == NULL);
 392         }
 393
 394         return rx_pkts;
 395 }
 396
 397 static bool
 398 sfc_ef10_rx_get_event(struct sfc_ef10_rxq *rxq, efx_qword_t *rx_ev)
 399 {
 400         *rx_ev = rxq->evq_hw_ring[rxq->evq_read_ptr & rxq->ptr_mask];
 401
 402         if (!sfc_ef10_ev_present(*rx_ev))
 403                 return false;
 404
 405         if (unlikely(EFX_QWORD_FIELD(*rx_ev, FSF_AZ_EV_CODE) !=
 406                      FSE_AZ_EV_CODE_RX_EV)) {
 407                 /*
 408                  * Do not move read_ptr to keep the event for exception
 409                  * handling by the control path.
 410                  */
 411                 rxq->flags |= SFC_EF10_RXQ_EXCEPTION;
 412                 sfc_ef10_rx_err(&rxq->dp.dpq,
 413                                 "RxQ exception at EvQ read ptr %#x",
 414                                 rxq->evq_read_ptr);
 415                 return false;
 416         }
 417
 418         rxq->evq_read_ptr++;
 419         return true;
 420 }
 421
 422 static uint16_t
 423 sfc_ef10_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 424 {
 425         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(rx_queue);
 426         struct rte_mbuf ** const rx_pkts_end = &rx_pkts[nb_pkts];
 427         unsigned int evq_old_read_ptr;
 428         efx_qword_t rx_ev;
 429
 430         rx_pkts = sfc_ef10_rx_pending(rxq, rx_pkts, nb_pkts);
 431
 432         if (unlikely(rxq->flags &
 433                      (SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION)))
 434                 goto done;
 435
 436         evq_old_read_ptr = rxq->evq_read_ptr;
 437         while (rx_pkts != rx_pkts_end && sfc_ef10_rx_get_event(rxq, &rx_ev)) {
 438                 /*
 439                  * DROP_EVENT is an internal to the NIC, software should
 440                  * never see it and, therefore, may ignore it.
 441                  */
 442
 443                 rx_pkts = sfc_ef10_rx_process_event(rxq, rx_ev,
 444                                                     rx_pkts, rx_pkts_end);
 445         }
 446
 447         sfc_ef10_ev_qclear(rxq->evq_hw_ring, rxq->ptr_mask, evq_old_read_ptr,
 448                            rxq->evq_read_ptr);
 449
 450         /* It is not a problem if we refill in the case of exception */
 451         sfc_ef10_rx_qrefill(rxq);
 452
 453         if ((rxq->flags & SFC_EF10_RXQ_FLAG_INTR_EN) &&
 454             rxq->evq_read_ptr_primed != rxq->evq_read_ptr)
 455                 sfc_ef10_rx_qprime(rxq);
 456
 457 done:
 458         return nb_pkts - (rx_pkts_end - rx_pkts);
 459 }
 460
 461 const uint32_t *
 462 sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps)
 463 {
 464         static const uint32_t ef10_native_ptypes[] = {
 465                 RTE_PTYPE_L2_ETHER,
 466                 RTE_PTYPE_L2_ETHER_ARP,
 467                 RTE_PTYPE_L2_ETHER_VLAN,
 468                 RTE_PTYPE_L2_ETHER_QINQ,
 469                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 470                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 471                 RTE_PTYPE_L4_FRAG,
 472                 RTE_PTYPE_L4_TCP,
 473                 RTE_PTYPE_L4_UDP,
 474                 RTE_PTYPE_UNKNOWN
 475         };
 476         static const uint32_t ef10_overlay_ptypes[] = {
 477                 RTE_PTYPE_L2_ETHER,
 478                 RTE_PTYPE_L2_ETHER_ARP,
 479                 RTE_PTYPE_L2_ETHER_VLAN,
 480                 RTE_PTYPE_L2_ETHER_QINQ,
 481                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 482                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 483                 RTE_PTYPE_L4_FRAG,
 484                 RTE_PTYPE_L4_TCP,
 485                 RTE_PTYPE_L4_UDP,
 486                 RTE_PTYPE_TUNNEL_VXLAN,
 487                 RTE_PTYPE_TUNNEL_NVGRE,
 488                 RTE_PTYPE_INNER_L2_ETHER,
 489                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 490                 RTE_PTYPE_INNER_L2_ETHER_QINQ,
 491                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 492                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 493                 RTE_PTYPE_INNER_L4_FRAG,
 494                 RTE_PTYPE_INNER_L4_TCP,
 495                 RTE_PTYPE_INNER_L4_UDP,
 496                 RTE_PTYPE_UNKNOWN
 497         };
 498
 499         /*
 500          * The function returns static set of supported packet types,
 501          * so we can't build it dynamically based on supported tunnel
 502          * encapsulations and should limit to known sets.
 503          */
 504         switch (tunnel_encaps) {
 505         case (1u << EFX_TUNNEL_PROTOCOL_VXLAN |
 506               1u << EFX_TUNNEL_PROTOCOL_GENEVE |
 507               1u << EFX_TUNNEL_PROTOCOL_NVGRE):
 508                 return ef10_overlay_ptypes;
 509         default:
 510                 SFC_GENERIC_LOG(ERR,
 511                         "Unexpected set of supported tunnel encapsulations: %#x",
 512                         tunnel_encaps);
 513                 /* FALLTHROUGH */
 514         case 0:
 515                 return ef10_native_ptypes;
 516         }
 517 }
 518
 519 static sfc_dp_rx_qdesc_npending_t sfc_ef10_rx_qdesc_npending;
 520 static unsigned int
 521 sfc_ef10_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 522 {
 523         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 524         efx_qword_t rx_ev;
 525         const unsigned int evq_old_read_ptr = rxq->evq_read_ptr;
 526         unsigned int pending = rxq->pending;
 527         unsigned int ready;
 528
 529         if (unlikely(rxq->flags &
 530                      (SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION)))
 531                 goto done;
 532
 533         while (sfc_ef10_rx_get_event(rxq, &rx_ev)) {
 534                 ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) -
 535                          pending) &
 536                         EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
 537                 pending += ready;
 538         }
 539
 540         /*
 541          * The function does not process events, so return event queue read
 542          * pointer to the original position to allow the events that were
 543          * read to be processed later
 544          */
 545         rxq->evq_read_ptr = evq_old_read_ptr;
 546
 547 done:
 548         return pending - rxq->completed;
 549 }
 550
 551 static sfc_dp_rx_qdesc_status_t sfc_ef10_rx_qdesc_status;
 552 static int
 553 sfc_ef10_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 554 {
 555         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 556         unsigned int npending = sfc_ef10_rx_qdesc_npending(dp_rxq);
 557
 558         if (unlikely(offset > rxq->ptr_mask))
 559                 return -EINVAL;
 560
 561         if (offset < npending)
 562                 return RTE_ETH_RX_DESC_DONE;
 563
 564         if (offset < (rxq->added - rxq->completed))
 565                 return RTE_ETH_RX_DESC_AVAIL;
 566
 567         return RTE_ETH_RX_DESC_UNAVAIL;
 568 }
 569
 570
 571 static sfc_dp_rx_get_dev_info_t sfc_ef10_rx_get_dev_info;
 572 static void
 573 sfc_ef10_rx_get_dev_info(struct rte_eth_dev_info *dev_info)
 574 {
 575         /*
 576          * Number of descriptors just defines maximum number of pushed
 577          * descriptors (fill level).
 578          */
 579         dev_info->rx_desc_lim.nb_min = SFC_RX_REFILL_BULK;
 580         dev_info->rx_desc_lim.nb_align = SFC_RX_REFILL_BULK;
 581 }
 582
 583
 584 static sfc_dp_rx_qsize_up_rings_t sfc_ef10_rx_qsize_up_rings;
 585 static int
 586 sfc_ef10_rx_qsize_up_rings(uint16_t nb_rx_desc,
 587                            struct sfc_dp_rx_hw_limits *limits,
 588                            __rte_unused struct rte_mempool *mb_pool,
 589                            unsigned int *rxq_entries,
 590                            unsigned int *evq_entries,
 591                            unsigned int *rxq_max_fill_level)
 592 {
 593         /*
 594          * rte_ethdev API guarantees that the number meets min, max and
 595          * alignment requirements.
 596          */
 597         if (nb_rx_desc <= limits->rxq_min_entries)
 598                 *rxq_entries = limits->rxq_min_entries;
 599         else
 600                 *rxq_entries = rte_align32pow2(nb_rx_desc);
 601
 602         *evq_entries = *rxq_entries;
 603
 604         *rxq_max_fill_level = RTE_MIN(nb_rx_desc,
 605                                       SFC_EF10_RXQ_LIMIT(*evq_entries));
 606         return 0;
 607 }
 608
 609
 610 static uint64_t
 611 sfc_ef10_mk_mbuf_rearm_data(uint16_t port_id, uint16_t prefix_size)
 612 {
 613         struct rte_mbuf m;
 614
 615         memset(&m, 0, sizeof(m));
 616
 617         rte_mbuf_refcnt_set(&m, 1);
 618         m.data_off = RTE_PKTMBUF_HEADROOM + prefix_size;
 619         m.nb_segs = 1;
 620         m.port = port_id;
 621
 622         /* rearm_data covers structure members filled in above */
 623         rte_compiler_barrier();
 624         RTE_BUILD_BUG_ON(sizeof(m.rearm_data[0]) != sizeof(uint64_t));
 625         return m.rearm_data[0];
 626 }
 627
 628 static sfc_dp_rx_qcreate_t sfc_ef10_rx_qcreate;
 629 static int
 630 sfc_ef10_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 631                     const struct rte_pci_addr *pci_addr, int socket_id,
 632                     const struct sfc_dp_rx_qcreate_info *info,
 633                     struct sfc_dp_rxq **dp_rxqp)
 634 {
 635         struct sfc_ef10_rxq *rxq;
 636         int rc;
 637
 638         rc = EINVAL;
 639         if (info->rxq_entries != info->evq_entries)
 640                 goto fail_rxq_args;
 641
 642         rc = ENOMEM;
 643         rxq = rte_zmalloc_socket("sfc-ef10-rxq", sizeof(*rxq),
 644                                  RTE_CACHE_LINE_SIZE, socket_id);
 645         if (rxq == NULL)
 646                 goto fail_rxq_alloc;
 647
 648         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 649
 650         rc = ENOMEM;
 651         rxq->sw_ring = rte_calloc_socket("sfc-ef10-rxq-sw_ring",
 652                                          info->rxq_entries,
 653                                          sizeof(*rxq->sw_ring),
 654                                          RTE_CACHE_LINE_SIZE, socket_id);
 655         if (rxq->sw_ring == NULL)
 656                 goto fail_desc_alloc;
 657
 658         rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
 659         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 660                 rxq->flags |= SFC_EF10_RXQ_RSS_HASH;
 661         rxq->ptr_mask = info->rxq_entries - 1;
 662         rxq->evq_hw_ring = info->evq_hw_ring;
 663         rxq->max_fill_level = info->max_fill_level;
 664         rxq->refill_threshold = info->refill_threshold;
 665         rxq->rearm_data =
 666                 sfc_ef10_mk_mbuf_rearm_data(port_id, info->prefix_size);
 667         rxq->prefix_size = info->prefix_size;
 668         rxq->buf_size = info->buf_size;
 669         rxq->refill_mb_pool = info->refill_mb_pool;
 670         rxq->rxq_hw_ring = info->rxq_hw_ring;
 671         rxq->doorbell = (volatile uint8_t *)info->mem_bar +
 672                         ER_DZ_RX_DESC_UPD_REG_OFST +
 673                         (info->hw_index << info->vi_window_shift);
 674         rxq->evq_prime = (volatile uint8_t *)info->mem_bar +
 675                       ER_DZ_EVQ_RPTR_REG_OFST +
 676                       (info->evq_hw_index << info->vi_window_shift);
 677
 678         sfc_ef10_rx_info(&rxq->dp.dpq, "RxQ doorbell is %p", rxq->doorbell);
 679
 680         *dp_rxqp = &rxq->dp;
 681         return 0;
 682
 683 fail_desc_alloc:
 684         rte_free(rxq);
 685
 686 fail_rxq_alloc:
 687 fail_rxq_args:
 688         return rc;
 689 }
 690
 691 static sfc_dp_rx_qdestroy_t sfc_ef10_rx_qdestroy;
 692 static void
 693 sfc_ef10_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 694 {
 695         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 696
 697         rte_free(rxq->sw_ring);
 698         rte_free(rxq);
 699 }
 700
 701 static sfc_dp_rx_qstart_t sfc_ef10_rx_qstart;
 702 static int
 703 sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
 704 {
 705         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 706
 707         SFC_ASSERT(rxq->completed == 0);
 708         SFC_ASSERT(rxq->pending == 0);
 709         SFC_ASSERT(rxq->added == 0);
 710
 711         sfc_ef10_rx_qrefill(rxq);
 712
 713         rxq->evq_read_ptr = evq_read_ptr;
 714
 715         rxq->flags |= SFC_EF10_RXQ_STARTED;
 716         rxq->flags &= ~(SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION);
 717
 718         if (rxq->flags & SFC_EF10_RXQ_FLAG_INTR_EN)
 719                 sfc_ef10_rx_qprime(rxq);
 720
 721         return 0;
 722 }
 723
 724 static sfc_dp_rx_qstop_t sfc_ef10_rx_qstop;
 725 static void
 726 sfc_ef10_rx_qstop(struct sfc_dp_rxq *dp_rxq, unsigned int *evq_read_ptr)
 727 {
 728         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 729
 730         rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
 731
 732         *evq_read_ptr = rxq->evq_read_ptr;
 733 }
 734
 735 static sfc_dp_rx_qrx_ev_t sfc_ef10_rx_qrx_ev;
 736 static bool
 737 sfc_ef10_rx_qrx_ev(struct sfc_dp_rxq *dp_rxq, __rte_unused unsigned int id)
 738 {
 739         __rte_unused struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 740
 741         SFC_ASSERT(rxq->flags & SFC_EF10_RXQ_NOT_RUNNING);
 742
 743         /*
 744          * It is safe to ignore Rx event since we free all mbufs on
 745          * queue purge anyway.
 746          */
 747
 748         return false;
 749 }
 750
 751 static sfc_dp_rx_qpurge_t sfc_ef10_rx_qpurge;
 752 static void
 753 sfc_ef10_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 754 {
 755         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 756         unsigned int i;
 757         struct sfc_ef10_rx_sw_desc *rxd;
 758
 759         rte_pktmbuf_free(rxq->scatter_pkt);
 760         rxq->scatter_pkt = NULL;
 761
 762         for (i = rxq->completed; i != rxq->added; ++i) {
 763                 rxd = &rxq->sw_ring[i & rxq->ptr_mask];
 764                 rte_mbuf_raw_free(rxd->mbuf);
 765                 rxd->mbuf = NULL;
 766         }
 767
 768         rxq->completed = rxq->pending = rxq->added = 0;
 769
 770         rxq->flags &= ~SFC_EF10_RXQ_STARTED;
 771 }
 772
 773 static sfc_dp_rx_intr_enable_t sfc_ef10_rx_intr_enable;
 774 static int
 775 sfc_ef10_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
 776 {
 777         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 778
 779         rxq->flags |= SFC_EF10_RXQ_FLAG_INTR_EN;
 780         if (rxq->flags & SFC_EF10_RXQ_STARTED)
 781                 sfc_ef10_rx_qprime(rxq);
 782         return 0;
 783 }
 784
 785 static sfc_dp_rx_intr_disable_t sfc_ef10_rx_intr_disable;
 786 static int
 787 sfc_ef10_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
 788 {
 789         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 790
 791         /* Cannot disarm, just disable rearm */
 792         rxq->flags &= ~SFC_EF10_RXQ_FLAG_INTR_EN;
 793         return 0;
 794 }
 795
 796 struct sfc_dp_rx sfc_ef10_rx = {
 797         .dp = {
 798                 .name           = SFC_KVARG_DATAPATH_EF10,
 799                 .type           = SFC_DP_RX,
 800                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_EF10,
 801         },
 802         .features               = SFC_DP_RX_FEAT_MULTI_PROCESS |
 803                                   SFC_DP_RX_FEAT_INTR,
 804         .dev_offload_capa       = DEV_RX_OFFLOAD_CHECKSUM |
 805                                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 806                                   DEV_RX_OFFLOAD_RSS_HASH,
 807         .queue_offload_capa     = DEV_RX_OFFLOAD_SCATTER,
 808         .get_dev_info           = sfc_ef10_rx_get_dev_info,
 809         .qsize_up_rings         = sfc_ef10_rx_qsize_up_rings,
 810         .qcreate                = sfc_ef10_rx_qcreate,
 811         .qdestroy               = sfc_ef10_rx_qdestroy,
 812         .qstart                 = sfc_ef10_rx_qstart,
 813         .qstop                  = sfc_ef10_rx_qstop,
 814         .qrx_ev                 = sfc_ef10_rx_qrx_ev,
 815         .qpurge                 = sfc_ef10_rx_qpurge,
 816         .supported_ptypes_get   = sfc_ef10_supported_ptypes_get,
 817         .qdesc_npending         = sfc_ef10_rx_qdesc_npending,
 818         .qdesc_status           = sfc_ef10_rx_qdesc_status,
 819         .intr_enable            = sfc_ef10_rx_intr_enable,
 820         .intr_disable           = sfc_ef10_rx_intr_disable,
 821         .pkt_burst              = sfc_ef10_recv_pkts,
 822 };