drivers/net/sfc/sfc_ef10_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2016-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 /* EF10 native datapath implementation */
  11
  12 #include <stdbool.h>
  13
  14 #include <rte_byteorder.h>
  15 #include <rte_mbuf_ptype.h>
  16 #include <rte_mbuf.h>
  17 #include <rte_io.h>
  18
  19 #include "efx.h"
  20 #include "efx_types.h"
  21 #include "efx_regs.h"
  22 #include "efx_regs_ef10.h"
  23
  24 #include "sfc_tweak.h"
  25 #include "sfc_dp_rx.h"
  26 #include "sfc_kvargs.h"
  27 #include "sfc_ef10.h"
  28 #include "sfc_ef10_rx_ev.h"
  29
  30 #define sfc_ef10_rx_err(dpq, ...) \
  31         SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, ERR, dpq, __VA_ARGS__)
  32
  33 /**
  34  * Maximum number of descriptors/buffers in the Rx ring.
  35  * It should guarantee that corresponding event queue never overfill.
  36  * EF10 native datapath uses event queue of the same size as Rx queue.
  37  * Maximum number of events on datapath can be estimated as number of
  38  * Rx queue entries (one event per Rx buffer in the worst case) plus
  39  * Rx error and flush events.
  40  */
  41 #define SFC_EF10_RXQ_LIMIT(_ndesc) \
  42         ((_ndesc) - 1 /* head must not step on tail */ - \
  43          (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
  44          1 /* Rx error */ - 1 /* flush */)
  45
  46 struct sfc_ef10_rx_sw_desc {
  47         struct rte_mbuf                 *mbuf;
  48 };
  49
  50 struct sfc_ef10_rxq {
  51         /* Used on data path */
  52         unsigned int                    flags;
  53 #define SFC_EF10_RXQ_STARTED            0x1
  54 #define SFC_EF10_RXQ_NOT_RUNNING        0x2
  55 #define SFC_EF10_RXQ_EXCEPTION          0x4
  56 #define SFC_EF10_RXQ_RSS_HASH           0x8
  57         unsigned int                    ptr_mask;
  58         unsigned int                    prepared;
  59         unsigned int                    completed;
  60         unsigned int                    evq_read_ptr;
  61         efx_qword_t                     *evq_hw_ring;
  62         struct sfc_ef10_rx_sw_desc      *sw_ring;
  63         uint64_t                        rearm_data;
  64         uint16_t                        prefix_size;
  65
  66         /* Used on refill */
  67         uint16_t                        buf_size;
  68         unsigned int                    added;
  69         unsigned int                    max_fill_level;
  70         unsigned int                    refill_threshold;
  71         struct rte_mempool              *refill_mb_pool;
  72         efx_qword_t                     *rxq_hw_ring;
  73         volatile void                   *doorbell;
  74
  75         /* Datapath receive queue anchor */
  76         struct sfc_dp_rxq               dp;
  77 };
  78
  79 static inline struct sfc_ef10_rxq *
  80 sfc_ef10_rxq_by_dp_rxq(struct sfc_dp_rxq *dp_rxq)
  81 {
  82         return container_of(dp_rxq, struct sfc_ef10_rxq, dp);
  83 }
  84
  85 static void
  86 sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq)
  87 {
  88         const unsigned int ptr_mask = rxq->ptr_mask;
  89         const uint32_t buf_size = rxq->buf_size;
  90         unsigned int free_space;
  91         unsigned int bulks;
  92         void *objs[SFC_RX_REFILL_BULK];
  93         unsigned int added = rxq->added;
  94
  95         RTE_BUILD_BUG_ON(SFC_RX_REFILL_BULK % SFC_EF10_RX_WPTR_ALIGN != 0);
  96
  97         free_space = rxq->max_fill_level - (added - rxq->completed);
  98
  99         if (free_space < rxq->refill_threshold)
 100                 return;
 101
 102         bulks = free_space / RTE_DIM(objs);
 103         /* refill_threshold guarantees that bulks is positive */
 104         SFC_ASSERT(bulks > 0);
 105
 106         do {
 107                 unsigned int id;
 108                 unsigned int i;
 109
 110                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
 111                                                   RTE_DIM(objs)) < 0)) {
 112                         struct rte_eth_dev_data *dev_data =
 113                                 rte_eth_devices[rxq->dp.dpq.port_id].data;
 114
 115                         /*
 116                          * It is hardly a safe way to increment counter
 117                          * from different contexts, but all PMDs do it.
 118                          */
 119                         dev_data->rx_mbuf_alloc_failed += RTE_DIM(objs);
 120                         /* Return if we have posted nothing yet */
 121                         if (added == rxq->added)
 122                                 return;
 123                         /* Push posted */
 124                         break;
 125                 }
 126
 127                 for (i = 0, id = added & ptr_mask;
 128                      i < RTE_DIM(objs);
 129                      ++i, ++id) {
 130                         struct rte_mbuf *m = objs[i];
 131                         struct sfc_ef10_rx_sw_desc *rxd;
 132                         rte_iova_t phys_addr;
 133
 134                         SFC_ASSERT((id & ~ptr_mask) == 0);
 135                         rxd = &rxq->sw_ring[id];
 136                         rxd->mbuf = m;
 137
 138                         /*
 139                          * Avoid writing to mbuf. It is cheaper to do it
 140                          * when we receive packet and fill in nearby
 141                          * structure members.
 142                          */
 143
 144                         phys_addr = rte_mbuf_data_iova_default(m);
 145                         EFX_POPULATE_QWORD_2(rxq->rxq_hw_ring[id],
 146                             ESF_DZ_RX_KER_BYTE_CNT, buf_size,
 147                             ESF_DZ_RX_KER_BUF_ADDR, phys_addr);
 148                 }
 149
 150                 added += RTE_DIM(objs);
 151         } while (--bulks > 0);
 152
 153         SFC_ASSERT(rxq->added != added);
 154         rxq->added = added;
 155         sfc_ef10_rx_qpush(rxq->doorbell, added, ptr_mask);
 156 }
 157
 158 static void
 159 sfc_ef10_rx_prefetch_next(struct sfc_ef10_rxq *rxq, unsigned int next_id)
 160 {
 161         struct rte_mbuf *next_mbuf;
 162
 163         /* Prefetch next bunch of software descriptors */
 164         if ((next_id % (RTE_CACHE_LINE_SIZE / sizeof(rxq->sw_ring[0]))) == 0)
 165                 rte_prefetch0(&rxq->sw_ring[next_id]);
 166
 167         /*
 168          * It looks strange to prefetch depending on previous prefetch
 169          * data, but measurements show that it is really efficient and
 170          * increases packet rate.
 171          */
 172         next_mbuf = rxq->sw_ring[next_id].mbuf;
 173         if (likely(next_mbuf != NULL)) {
 174                 /* Prefetch the next mbuf structure */
 175                 rte_mbuf_prefetch_part1(next_mbuf);
 176
 177                 /* Prefetch pseudo header of the next packet */
 178                 /* data_off is not filled in yet */
 179                 /* Yes, data could be not ready yet, but we hope */
 180                 rte_prefetch0((uint8_t *)next_mbuf->buf_addr +
 181                               RTE_PKTMBUF_HEADROOM);
 182         }
 183 }
 184
 185 static uint16_t
 186 sfc_ef10_rx_prepared(struct sfc_ef10_rxq *rxq, struct rte_mbuf **rx_pkts,
 187                      uint16_t nb_pkts)
 188 {
 189         uint16_t n_rx_pkts = RTE_MIN(nb_pkts, rxq->prepared);
 190         unsigned int completed = rxq->completed;
 191         unsigned int i;
 192
 193         rxq->prepared -= n_rx_pkts;
 194         rxq->completed = completed + n_rx_pkts;
 195
 196         for (i = 0; i < n_rx_pkts; ++i, ++completed)
 197                 rx_pkts[i] = rxq->sw_ring[completed & rxq->ptr_mask].mbuf;
 198
 199         return n_rx_pkts;
 200 }
 201
 202 static uint16_t
 203 sfc_ef10_rx_pseudo_hdr_get_len(const uint8_t *pseudo_hdr)
 204 {
 205         return rte_le_to_cpu_16(*(const uint16_t *)&pseudo_hdr[8]);
 206 }
 207
 208 static uint32_t
 209 sfc_ef10_rx_pseudo_hdr_get_hash(const uint8_t *pseudo_hdr)
 210 {
 211         return rte_le_to_cpu_32(*(const uint32_t *)pseudo_hdr);
 212 }
 213
 214 static uint16_t
 215 sfc_ef10_rx_process_event(struct sfc_ef10_rxq *rxq, efx_qword_t rx_ev,
 216                           struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 217 {
 218         const unsigned int ptr_mask = rxq->ptr_mask;
 219         unsigned int completed = rxq->completed;
 220         unsigned int ready;
 221         struct sfc_ef10_rx_sw_desc *rxd;
 222         struct rte_mbuf *m;
 223         struct rte_mbuf *m0;
 224         uint16_t n_rx_pkts;
 225         const uint8_t *pseudo_hdr;
 226         uint16_t pkt_len;
 227
 228         ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) - completed) &
 229                 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
 230         SFC_ASSERT(ready > 0);
 231
 232         if (rx_ev.eq_u64[0] &
 233             rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) |
 234                              (1ull << ESF_DZ_RX_ECRC_ERR_LBN))) {
 235                 SFC_ASSERT(rxq->prepared == 0);
 236                 rxq->completed += ready;
 237                 while (ready-- > 0) {
 238                         rxd = &rxq->sw_ring[completed++ & ptr_mask];
 239                         rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
 240                 }
 241                 return 0;
 242         }
 243
 244         n_rx_pkts = RTE_MIN(ready, nb_pkts);
 245         rxq->prepared = ready - n_rx_pkts;
 246         rxq->completed += n_rx_pkts;
 247
 248         rxd = &rxq->sw_ring[completed++ & ptr_mask];
 249
 250         sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
 251
 252         m = rxd->mbuf;
 253
 254         *rx_pkts++ = m;
 255
 256         RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) != sizeof(rxq->rearm_data));
 257         m->rearm_data[0] = rxq->rearm_data;
 258
 259         /* Classify packet based on Rx event */
 260         /* Mask RSS hash offload flag if RSS is not enabled */
 261         sfc_ef10_rx_ev_to_offloads(rx_ev, m,
 262                                    (rxq->flags & SFC_EF10_RXQ_RSS_HASH) ?
 263                                    ~0ull : ~PKT_RX_RSS_HASH);
 264
 265         /* data_off already moved past pseudo header */
 266         pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
 267
 268         /*
 269          * Always get RSS hash from pseudo header to avoid
 270          * condition/branching. If it is valid or not depends on
 271          * PKT_RX_RSS_HASH in m->ol_flags.
 272          */
 273         m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
 274
 275         if (ready == 1)
 276                 pkt_len = EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_BYTES) -
 277                         rxq->prefix_size;
 278         else
 279                 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
 280         SFC_ASSERT(pkt_len > 0);
 281         rte_pktmbuf_data_len(m) = pkt_len;
 282         rte_pktmbuf_pkt_len(m) = pkt_len;
 283
 284         SFC_ASSERT(m->next == NULL);
 285
 286         /* Remember mbuf to copy offload flags and packet type from */
 287         m0 = m;
 288         for (--ready; ready > 0; --ready) {
 289                 rxd = &rxq->sw_ring[completed++ & ptr_mask];
 290
 291                 sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
 292
 293                 m = rxd->mbuf;
 294
 295                 if (ready > rxq->prepared)
 296                         *rx_pkts++ = m;
 297
 298                 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) !=
 299                                  sizeof(rxq->rearm_data));
 300                 m->rearm_data[0] = rxq->rearm_data;
 301
 302                 /* Event-dependent information is the same */
 303                 m->ol_flags = m0->ol_flags;
 304                 m->packet_type = m0->packet_type;
 305
 306                 /* data_off already moved past pseudo header */
 307                 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
 308
 309                 /*
 310                  * Always get RSS hash from pseudo header to avoid
 311                  * condition/branching. If it is valid or not depends on
 312                  * PKT_RX_RSS_HASH in m->ol_flags.
 313                  */
 314                 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
 315
 316                 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
 317                 SFC_ASSERT(pkt_len > 0);
 318                 rte_pktmbuf_data_len(m) = pkt_len;
 319                 rte_pktmbuf_pkt_len(m) = pkt_len;
 320
 321                 SFC_ASSERT(m->next == NULL);
 322         }
 323
 324         return n_rx_pkts;
 325 }
 326
 327 static bool
 328 sfc_ef10_rx_get_event(struct sfc_ef10_rxq *rxq, efx_qword_t *rx_ev)
 329 {
 330         *rx_ev = rxq->evq_hw_ring[rxq->evq_read_ptr & rxq->ptr_mask];
 331
 332         if (!sfc_ef10_ev_present(*rx_ev))
 333                 return false;
 334
 335         if (unlikely(EFX_QWORD_FIELD(*rx_ev, FSF_AZ_EV_CODE) !=
 336                      FSE_AZ_EV_CODE_RX_EV)) {
 337                 /*
 338                  * Do not move read_ptr to keep the event for exception
 339                  * handling by the control path.
 340                  */
 341                 rxq->flags |= SFC_EF10_RXQ_EXCEPTION;
 342                 sfc_ef10_rx_err(&rxq->dp.dpq,
 343                                 "RxQ exception at EvQ read ptr %#x",
 344                                 rxq->evq_read_ptr);
 345                 return false;
 346         }
 347
 348         rxq->evq_read_ptr++;
 349         return true;
 350 }
 351
 352 static uint16_t
 353 sfc_ef10_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 354 {
 355         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(rx_queue);
 356         unsigned int evq_old_read_ptr;
 357         uint16_t n_rx_pkts;
 358         efx_qword_t rx_ev;
 359
 360         if (unlikely(rxq->flags &
 361                      (SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION)))
 362                 return 0;
 363
 364         n_rx_pkts = sfc_ef10_rx_prepared(rxq, rx_pkts, nb_pkts);
 365
 366         evq_old_read_ptr = rxq->evq_read_ptr;
 367         while (n_rx_pkts != nb_pkts && sfc_ef10_rx_get_event(rxq, &rx_ev)) {
 368                 /*
 369                  * DROP_EVENT is an internal to the NIC, software should
 370                  * never see it and, therefore, may ignore it.
 371                  */
 372
 373                 n_rx_pkts += sfc_ef10_rx_process_event(rxq, rx_ev,
 374                                                        rx_pkts + n_rx_pkts,
 375                                                        nb_pkts - n_rx_pkts);
 376         }
 377
 378         sfc_ef10_ev_qclear(rxq->evq_hw_ring, rxq->ptr_mask, evq_old_read_ptr,
 379                            rxq->evq_read_ptr);
 380
 381         /* It is not a problem if we refill in the case of exception */
 382         sfc_ef10_rx_qrefill(rxq);
 383
 384         return n_rx_pkts;
 385 }
 386
 387 static const uint32_t *
 388 sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps)
 389 {
 390         static const uint32_t ef10_native_ptypes[] = {
 391                 RTE_PTYPE_L2_ETHER,
 392                 RTE_PTYPE_L2_ETHER_ARP,
 393                 RTE_PTYPE_L2_ETHER_VLAN,
 394                 RTE_PTYPE_L2_ETHER_QINQ,
 395                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 396                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 397                 RTE_PTYPE_L4_FRAG,
 398                 RTE_PTYPE_L4_TCP,
 399                 RTE_PTYPE_L4_UDP,
 400                 RTE_PTYPE_UNKNOWN
 401         };
 402         static const uint32_t ef10_overlay_ptypes[] = {
 403                 RTE_PTYPE_L2_ETHER,
 404                 RTE_PTYPE_L2_ETHER_ARP,
 405                 RTE_PTYPE_L2_ETHER_VLAN,
 406                 RTE_PTYPE_L2_ETHER_QINQ,
 407                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 408                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 409                 RTE_PTYPE_L4_FRAG,
 410                 RTE_PTYPE_L4_TCP,
 411                 RTE_PTYPE_L4_UDP,
 412                 RTE_PTYPE_TUNNEL_VXLAN,
 413                 RTE_PTYPE_TUNNEL_NVGRE,
 414                 RTE_PTYPE_INNER_L2_ETHER,
 415                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 416                 RTE_PTYPE_INNER_L2_ETHER_QINQ,
 417                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 418                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 419                 RTE_PTYPE_INNER_L4_FRAG,
 420                 RTE_PTYPE_INNER_L4_TCP,
 421                 RTE_PTYPE_INNER_L4_UDP,
 422                 RTE_PTYPE_UNKNOWN
 423         };
 424
 425         /*
 426          * The function returns static set of supported packet types,
 427          * so we can't build it dynamically based on supported tunnel
 428          * encapsulations and should limit to known sets.
 429          */
 430         switch (tunnel_encaps) {
 431         case (1u << EFX_TUNNEL_PROTOCOL_VXLAN |
 432               1u << EFX_TUNNEL_PROTOCOL_GENEVE |
 433               1u << EFX_TUNNEL_PROTOCOL_NVGRE):
 434                 return ef10_overlay_ptypes;
 435         default:
 436                 SFC_GENERIC_LOG(ERR,
 437                         "Unexpected set of supported tunnel encapsulations: %#x",
 438                         tunnel_encaps);
 439                 /* FALLTHROUGH */
 440         case 0:
 441                 return ef10_native_ptypes;
 442         }
 443 }
 444
 445 static sfc_dp_rx_qdesc_npending_t sfc_ef10_rx_qdesc_npending;
 446 static unsigned int
 447 sfc_ef10_rx_qdesc_npending(__rte_unused struct sfc_dp_rxq *dp_rxq)
 448 {
 449         /*
 450          * Correct implementation requires EvQ polling and events
 451          * processing (keeping all ready mbufs in prepared).
 452          */
 453         return -ENOTSUP;
 454 }
 455
 456 static sfc_dp_rx_qdesc_status_t sfc_ef10_rx_qdesc_status;
 457 static int
 458 sfc_ef10_rx_qdesc_status(__rte_unused struct sfc_dp_rxq *dp_rxq,
 459                          __rte_unused uint16_t offset)
 460 {
 461         return -ENOTSUP;
 462 }
 463
 464
 465 static sfc_dp_rx_get_dev_info_t sfc_ef10_rx_get_dev_info;
 466 static void
 467 sfc_ef10_rx_get_dev_info(struct rte_eth_dev_info *dev_info)
 468 {
 469         /*
 470          * Number of descriptors just defines maximum number of pushed
 471          * descriptors (fill level).
 472          */
 473         dev_info->rx_desc_lim.nb_min = SFC_RX_REFILL_BULK;
 474         dev_info->rx_desc_lim.nb_align = SFC_RX_REFILL_BULK;
 475 }
 476
 477
 478 static sfc_dp_rx_qsize_up_rings_t sfc_ef10_rx_qsize_up_rings;
 479 static int
 480 sfc_ef10_rx_qsize_up_rings(uint16_t nb_rx_desc,
 481                            unsigned int *rxq_entries,
 482                            unsigned int *evq_entries,
 483                            unsigned int *rxq_max_fill_level)
 484 {
 485         /*
 486          * rte_ethdev API guarantees that the number meets min, max and
 487          * alignment requirements.
 488          */
 489         if (nb_rx_desc <= EFX_RXQ_MINNDESCS)
 490                 *rxq_entries = EFX_RXQ_MINNDESCS;
 491         else
 492                 *rxq_entries = rte_align32pow2(nb_rx_desc);
 493
 494         *evq_entries = *rxq_entries;
 495
 496         *rxq_max_fill_level = RTE_MIN(nb_rx_desc,
 497                                       SFC_EF10_RXQ_LIMIT(*evq_entries));
 498         return 0;
 499 }
 500
 501
 502 static uint64_t
 503 sfc_ef10_mk_mbuf_rearm_data(uint16_t port_id, uint16_t prefix_size)
 504 {
 505         struct rte_mbuf m;
 506
 507         memset(&m, 0, sizeof(m));
 508
 509         rte_mbuf_refcnt_set(&m, 1);
 510         m.data_off = RTE_PKTMBUF_HEADROOM + prefix_size;
 511         m.nb_segs = 1;
 512         m.port = port_id;
 513
 514         /* rearm_data covers structure members filled in above */
 515         rte_compiler_barrier();
 516         RTE_BUILD_BUG_ON(sizeof(m.rearm_data[0]) != sizeof(uint64_t));
 517         return m.rearm_data[0];
 518 }
 519
 520 static sfc_dp_rx_qcreate_t sfc_ef10_rx_qcreate;
 521 static int
 522 sfc_ef10_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 523                     const struct rte_pci_addr *pci_addr, int socket_id,
 524                     const struct sfc_dp_rx_qcreate_info *info,
 525                     struct sfc_dp_rxq **dp_rxqp)
 526 {
 527         struct sfc_ef10_rxq *rxq;
 528         int rc;
 529
 530         rc = EINVAL;
 531         if (info->rxq_entries != info->evq_entries)
 532                 goto fail_rxq_args;
 533
 534         rc = ENOMEM;
 535         rxq = rte_zmalloc_socket("sfc-ef10-rxq", sizeof(*rxq),
 536                                  RTE_CACHE_LINE_SIZE, socket_id);
 537         if (rxq == NULL)
 538                 goto fail_rxq_alloc;
 539
 540         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 541
 542         rc = ENOMEM;
 543         rxq->sw_ring = rte_calloc_socket("sfc-ef10-rxq-sw_ring",
 544                                          info->rxq_entries,
 545                                          sizeof(*rxq->sw_ring),
 546                                          RTE_CACHE_LINE_SIZE, socket_id);
 547         if (rxq->sw_ring == NULL)
 548                 goto fail_desc_alloc;
 549
 550         rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
 551         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 552                 rxq->flags |= SFC_EF10_RXQ_RSS_HASH;
 553         rxq->ptr_mask = info->rxq_entries - 1;
 554         rxq->evq_hw_ring = info->evq_hw_ring;
 555         rxq->max_fill_level = info->max_fill_level;
 556         rxq->refill_threshold = info->refill_threshold;
 557         rxq->rearm_data =
 558                 sfc_ef10_mk_mbuf_rearm_data(port_id, info->prefix_size);
 559         rxq->prefix_size = info->prefix_size;
 560         rxq->buf_size = info->buf_size;
 561         rxq->refill_mb_pool = info->refill_mb_pool;
 562         rxq->rxq_hw_ring = info->rxq_hw_ring;
 563         rxq->doorbell = (volatile uint8_t *)info->mem_bar +
 564                         ER_DZ_RX_DESC_UPD_REG_OFST +
 565                         (info->hw_index << info->vi_window_shift);
 566
 567         *dp_rxqp = &rxq->dp;
 568         return 0;
 569
 570 fail_desc_alloc:
 571         rte_free(rxq);
 572
 573 fail_rxq_alloc:
 574 fail_rxq_args:
 575         return rc;
 576 }
 577
 578 static sfc_dp_rx_qdestroy_t sfc_ef10_rx_qdestroy;
 579 static void
 580 sfc_ef10_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 581 {
 582         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 583
 584         rte_free(rxq->sw_ring);
 585         rte_free(rxq);
 586 }
 587
 588 static sfc_dp_rx_qstart_t sfc_ef10_rx_qstart;
 589 static int
 590 sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
 591 {
 592         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 593
 594         rxq->prepared = 0;
 595         rxq->completed = rxq->added = 0;
 596
 597         sfc_ef10_rx_qrefill(rxq);
 598
 599         rxq->evq_read_ptr = evq_read_ptr;
 600
 601         rxq->flags |= SFC_EF10_RXQ_STARTED;
 602         rxq->flags &= ~(SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION);
 603
 604         return 0;
 605 }
 606
 607 static sfc_dp_rx_qstop_t sfc_ef10_rx_qstop;
 608 static void
 609 sfc_ef10_rx_qstop(struct sfc_dp_rxq *dp_rxq, unsigned int *evq_read_ptr)
 610 {
 611         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 612
 613         rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
 614
 615         *evq_read_ptr = rxq->evq_read_ptr;
 616 }
 617
 618 static sfc_dp_rx_qrx_ev_t sfc_ef10_rx_qrx_ev;
 619 static bool
 620 sfc_ef10_rx_qrx_ev(struct sfc_dp_rxq *dp_rxq, __rte_unused unsigned int id)
 621 {
 622         __rte_unused struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 623
 624         SFC_ASSERT(rxq->flags & SFC_EF10_RXQ_NOT_RUNNING);
 625
 626         /*
 627          * It is safe to ignore Rx event since we free all mbufs on
 628          * queue purge anyway.
 629          */
 630
 631         return false;
 632 }
 633
 634 static sfc_dp_rx_qpurge_t sfc_ef10_rx_qpurge;
 635 static void
 636 sfc_ef10_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 637 {
 638         struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
 639         unsigned int i;
 640         struct sfc_ef10_rx_sw_desc *rxd;
 641
 642         for (i = rxq->completed; i != rxq->added; ++i) {
 643                 rxd = &rxq->sw_ring[i & rxq->ptr_mask];
 644                 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
 645                 rxd->mbuf = NULL;
 646         }
 647
 648         rxq->flags &= ~SFC_EF10_RXQ_STARTED;
 649 }
 650
 651 struct sfc_dp_rx sfc_ef10_rx = {
 652         .dp = {
 653                 .name           = SFC_KVARG_DATAPATH_EF10,
 654                 .type           = SFC_DP_RX,
 655                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_EF10,
 656         },
 657         .features               = SFC_DP_RX_FEAT_MULTI_PROCESS |
 658                                   SFC_DP_RX_FEAT_TUNNELS,
 659         .get_dev_info           = sfc_ef10_rx_get_dev_info,
 660         .qsize_up_rings         = sfc_ef10_rx_qsize_up_rings,
 661         .qcreate                = sfc_ef10_rx_qcreate,
 662         .qdestroy               = sfc_ef10_rx_qdestroy,
 663         .qstart                 = sfc_ef10_rx_qstart,
 664         .qstop                  = sfc_ef10_rx_qstop,
 665         .qrx_ev                 = sfc_ef10_rx_qrx_ev,
 666         .qpurge                 = sfc_ef10_rx_qpurge,
 667         .supported_ptypes_get   = sfc_ef10_supported_ptypes_get,
 668         .qdesc_npending         = sfc_ef10_rx_qdesc_npending,
 669         .qdesc_status           = sfc_ef10_rx_qdesc_status,
 670         .pkt_burst              = sfc_ef10_recv_pkts,
 671 };