1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 #ifndef _SFC_EF10_RX_EV_H
11 #define _SFC_EF10_RX_EV_H
15 #include "efx_types.h"
17 #include "efx_regs_ef10.h"
24 sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
27 uint32_t tun_ptype = 0;
28 /* Which event bit is mapped to PKT_RX_IP_CKSUM_* */
29 int8_t ip_csum_err_bit;
30 /* Which event bit is mapped to PKT_RX_L4_CKSUM_* */
31 int8_t l4_csum_err_bit;
32 uint32_t l2_ptype = 0;
33 uint32_t l3_ptype = 0;
34 uint32_t l4_ptype = 0;
35 uint64_t ol_flags = 0;
37 if (unlikely(EFX_TEST_QWORD_BIT(rx_ev, ESF_DZ_RX_PARSE_INCOMPLETE_LBN)))
40 switch (EFX_QWORD_FIELD(rx_ev, ESF_EZ_RX_ENCAP_HDR)) {
42 /* Unexpected encapsulation tag class */
45 case ESE_EZ_ENCAP_HDR_NONE:
47 case ESE_EZ_ENCAP_HDR_VXLAN:
49 * It is definitely UDP, but we have no information
50 * about IPv4 vs IPv6 and VLAN tagging.
52 tun_ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP;
54 case ESE_EZ_ENCAP_HDR_GRE:
56 * We have no information about IPv4 vs IPv6 and VLAN tagging.
58 tun_ptype = RTE_PTYPE_TUNNEL_NVGRE;
63 ip_csum_err_bit = ESF_DZ_RX_IPCKSUM_ERR_LBN;
64 l4_csum_err_bit = ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN;
66 ip_csum_err_bit = ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN;
67 l4_csum_err_bit = ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN;
68 if (unlikely(EFX_TEST_QWORD_BIT(rx_ev,
69 ESF_DZ_RX_IPCKSUM_ERR_LBN)))
70 ol_flags |= PKT_RX_EIP_CKSUM_BAD;
73 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) {
74 case ESE_DZ_ETH_TAG_CLASS_NONE:
75 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER :
76 RTE_PTYPE_INNER_L2_ETHER;
78 case ESE_DZ_ETH_TAG_CLASS_VLAN1:
79 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_VLAN :
80 RTE_PTYPE_INNER_L2_ETHER_VLAN;
82 case ESE_DZ_ETH_TAG_CLASS_VLAN2:
83 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_QINQ :
84 RTE_PTYPE_INNER_L2_ETHER_QINQ;
87 /* Unexpected Eth tag class */
91 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L3_CLASS)) {
92 case ESE_DZ_L3_CLASS_IP4_FRAG:
93 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
94 RTE_PTYPE_INNER_L4_FRAG;
96 case ESE_DZ_L3_CLASS_IP4:
97 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN :
98 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
99 ol_flags |= PKT_RX_RSS_HASH |
100 ((EFX_TEST_QWORD_BIT(rx_ev, ip_csum_err_bit)) ?
101 PKT_RX_IP_CKSUM_BAD : PKT_RX_IP_CKSUM_GOOD);
103 case ESE_DZ_L3_CLASS_IP6_FRAG:
104 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
105 RTE_PTYPE_INNER_L4_FRAG;
107 case ESE_DZ_L3_CLASS_IP6:
108 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
109 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
110 ol_flags |= PKT_RX_RSS_HASH;
112 case ESE_DZ_L3_CLASS_ARP:
113 /* Override Layer 2 packet type */
114 /* There is no ARP classification for inner packets */
116 l2_ptype = RTE_PTYPE_L2_ETHER_ARP;
119 /* Unexpected Layer 3 class */
124 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
125 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
126 * and values for all EF10 controllers.
128 RTE_BUILD_BUG_ON(ESF_FZ_RX_L4_CLASS_LBN != ESF_DE_RX_L4_CLASS_LBN);
129 switch (EFX_QWORD_FIELD(rx_ev, ESF_FZ_RX_L4_CLASS)) {
130 case ESE_FZ_L4_CLASS_TCP:
131 RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_TCP != ESE_DE_L4_CLASS_TCP);
132 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :
133 RTE_PTYPE_INNER_L4_TCP;
135 (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
136 PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
138 case ESE_FZ_L4_CLASS_UDP:
139 RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP);
140 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :
141 RTE_PTYPE_INNER_L4_UDP;
143 (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
144 PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
146 case ESE_FZ_L4_CLASS_UNKNOWN:
147 RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN !=
148 ESE_DE_L4_CLASS_UNKNOWN);
151 /* Unexpected Layer 4 class */
156 m->ol_flags = ol_flags & ol_mask;
157 m->packet_type = tun_ptype | l2_ptype | l3_ptype | l4_ptype;
164 #endif /* _SFC_EF10_RX_EV_H */