1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
18 #include "efx_types.h"
20 #include "efx_regs_ef10.h"
22 #include "sfc_dp_tx.h"
23 #include "sfc_tweak.h"
24 #include "sfc_kvargs.h"
28 #define sfc_ef10_tx_err(dpq, ...) \
29 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, ERR, dpq, __VA_ARGS__)
31 /** Maximum length of the DMA descriptor data */
32 #define SFC_EF10_TX_DMA_DESC_LEN_MAX \
33 ((1u << ESF_DZ_TX_KER_BYTE_CNT_WIDTH) - 1)
36 * Maximum number of descriptors/buffers in the Tx ring.
37 * It should guarantee that corresponding event queue never overfill.
38 * EF10 native datapath uses event queue of the same size as Tx queue.
39 * Maximum number of events on datapath can be estimated as number of
40 * Tx queue entries (one event per Tx buffer in the worst case) plus
41 * Tx error and flush events.
43 #define SFC_EF10_TXQ_LIMIT(_ndesc) \
44 ((_ndesc) - 1 /* head must not step on tail */ - \
45 (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
46 1 /* Rx error */ - 1 /* flush */)
48 struct sfc_ef10_tx_sw_desc {
49 struct rte_mbuf *mbuf;
54 #define SFC_EF10_TXQ_STARTED 0x1
55 #define SFC_EF10_TXQ_NOT_RUNNING 0x2
56 #define SFC_EF10_TXQ_EXCEPTION 0x4
58 unsigned int ptr_mask;
60 unsigned int completed;
61 unsigned int max_fill_level;
62 unsigned int free_thresh;
63 unsigned int evq_read_ptr;
64 struct sfc_ef10_tx_sw_desc *sw_ring;
65 efx_qword_t *txq_hw_ring;
66 volatile void *doorbell;
67 efx_qword_t *evq_hw_ring;
70 uint16_t tso_tcp_header_offset_limit;
72 /* Datapath transmit queue anchor */
76 static inline struct sfc_ef10_txq *
77 sfc_ef10_txq_by_dp_txq(struct sfc_dp_txq *dp_txq)
79 return container_of(dp_txq, struct sfc_ef10_txq, dp);
83 sfc_ef10_tx_get_event(struct sfc_ef10_txq *txq, efx_qword_t *tx_ev)
85 volatile efx_qword_t *evq_hw_ring = txq->evq_hw_ring;
88 * Exception flag is set when reap is done.
89 * It is never done twice per packet burst get and absence of
90 * the flag is checked on burst get entry.
92 SFC_ASSERT((txq->flags & SFC_EF10_TXQ_EXCEPTION) == 0);
94 *tx_ev = evq_hw_ring[txq->evq_read_ptr & txq->ptr_mask];
96 if (!sfc_ef10_ev_present(*tx_ev))
99 if (unlikely(EFX_QWORD_FIELD(*tx_ev, FSF_AZ_EV_CODE) !=
100 FSE_AZ_EV_CODE_TX_EV)) {
102 * Do not move read_ptr to keep the event for exception
103 * handling by the control path.
105 txq->flags |= SFC_EF10_TXQ_EXCEPTION;
106 sfc_ef10_tx_err(&txq->dp.dpq,
107 "TxQ exception at EvQ read ptr %#x",
117 sfc_ef10_tx_process_events(struct sfc_ef10_txq *txq)
119 const unsigned int curr_done = txq->completed - 1;
120 unsigned int anew_done = curr_done;
123 while (sfc_ef10_tx_get_event(txq, &tx_ev)) {
125 * DROP_EVENT is an internal to the NIC, software should
126 * never see it and, therefore, may ignore it.
129 /* Update the latest done descriptor */
130 anew_done = EFX_QWORD_FIELD(tx_ev, ESF_DZ_TX_DESCR_INDX);
132 return (anew_done - curr_done) & txq->ptr_mask;
136 sfc_ef10_tx_reap(struct sfc_ef10_txq *txq)
138 const unsigned int old_read_ptr = txq->evq_read_ptr;
139 const unsigned int ptr_mask = txq->ptr_mask;
140 unsigned int completed = txq->completed;
141 unsigned int pending = completed;
143 pending += sfc_ef10_tx_process_events(txq);
145 if (pending != completed) {
146 struct rte_mbuf *bulk[SFC_TX_REAP_BULK_SIZE];
150 struct sfc_ef10_tx_sw_desc *txd;
153 txd = &txq->sw_ring[completed & ptr_mask];
154 if (txd->mbuf == NULL)
157 m = rte_pktmbuf_prefree_seg(txd->mbuf);
162 if ((nb == RTE_DIM(bulk)) ||
163 ((nb != 0) && (m->pool != bulk[0]->pool))) {
164 rte_mempool_put_bulk(bulk[0]->pool,
170 } while (++completed != pending);
173 rte_mempool_put_bulk(bulk[0]->pool, (void *)bulk, nb);
175 txq->completed = completed;
178 sfc_ef10_ev_qclear(txq->evq_hw_ring, ptr_mask, old_read_ptr,
183 sfc_ef10_tx_qdesc_dma_create(rte_iova_t addr, uint16_t size, bool eop,
186 EFX_POPULATE_QWORD_4(*edp,
187 ESF_DZ_TX_KER_TYPE, 0,
188 ESF_DZ_TX_KER_CONT, !eop,
189 ESF_DZ_TX_KER_BYTE_CNT, size,
190 ESF_DZ_TX_KER_BUF_ADDR, addr);
194 sfc_ef10_tx_qdesc_tso2_create(struct sfc_ef10_txq * const txq,
195 unsigned int added, uint16_t ipv4_id,
196 uint16_t outer_ipv4_id, uint32_t tcp_seq,
199 EFX_POPULATE_QWORD_5(txq->txq_hw_ring[added & txq->ptr_mask],
200 ESF_DZ_TX_DESC_IS_OPT, 1,
201 ESF_DZ_TX_OPTION_TYPE,
202 ESE_DZ_TX_OPTION_DESC_TSO,
203 ESF_DZ_TX_TSO_OPTION_TYPE,
204 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
205 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
206 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
207 EFX_POPULATE_QWORD_5(txq->txq_hw_ring[(added + 1) & txq->ptr_mask],
208 ESF_DZ_TX_DESC_IS_OPT, 1,
209 ESF_DZ_TX_OPTION_TYPE,
210 ESE_DZ_TX_OPTION_DESC_TSO,
211 ESF_DZ_TX_TSO_OPTION_TYPE,
212 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
213 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss,
214 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id);
218 sfc_ef10_tx_qpush(struct sfc_ef10_txq *txq, unsigned int added,
225 * This improves performance by pushing a TX descriptor at the same
226 * time as the doorbell. The descriptor must be added to the TXQ,
227 * so that can be used if the hardware decides not to use the pushed
230 desc.eq_u64[0] = txq->txq_hw_ring[pushed & txq->ptr_mask].eq_u64[0];
231 EFX_POPULATE_OWORD_3(oword,
232 ERF_DZ_TX_DESC_WPTR, added & txq->ptr_mask,
233 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
234 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
236 /* DMA sync to device is not required */
239 * rte_io_wmb() which guarantees that the STORE operations
240 * (i.e. Tx and event descriptor updates) that precede
241 * the rte_io_wmb() call are visible to NIC before the STORE
242 * operations that follow it (i.e. doorbell write).
246 *(volatile __m128i *)txq->doorbell = oword.eo_u128[0];
250 sfc_ef10_tx_pkt_descs_max(const struct rte_mbuf *m)
252 unsigned int extra_descs_per_seg;
253 unsigned int extra_descs_per_pkt;
256 * VLAN offload is not supported yet, so no extra descriptors
257 * are required for VLAN option descriptor.
260 /** Maximum length of the mbuf segment data */
261 #define SFC_MBUF_SEG_LEN_MAX UINT16_MAX
262 RTE_BUILD_BUG_ON(sizeof(m->data_len) != 2);
265 * Each segment is already counted once below. So, calculate
266 * how many extra DMA descriptors may be required per segment in
267 * the worst case because of maximum DMA descriptor length limit.
268 * If maximum segment length is less or equal to maximum DMA
269 * descriptor length, no extra DMA descriptors are required.
271 extra_descs_per_seg =
272 (SFC_MBUF_SEG_LEN_MAX - 1) / SFC_EF10_TX_DMA_DESC_LEN_MAX;
274 /** Maximum length of the packet */
275 #define SFC_MBUF_PKT_LEN_MAX UINT32_MAX
276 RTE_BUILD_BUG_ON(sizeof(m->pkt_len) != 4);
279 * One more limitation on maximum number of extra DMA descriptors
280 * comes from slicing entire packet because of DMA descriptor length
281 * limit taking into account that there is at least one segment
282 * which is already counted below (so division of the maximum
283 * packet length minus one with round down).
284 * TSO is not supported yet, so packet length is limited by
287 extra_descs_per_pkt =
288 (RTE_MIN((unsigned int)EFX_MAC_PDU_MAX,
289 SFC_MBUF_PKT_LEN_MAX) - 1) /
290 SFC_EF10_TX_DMA_DESC_LEN_MAX;
292 return m->nb_segs + RTE_MIN(m->nb_segs * extra_descs_per_seg,
293 extra_descs_per_pkt);
297 sfc_ef10_try_reap(struct sfc_ef10_txq * const txq, unsigned int added,
298 unsigned int needed_desc, unsigned int *dma_desc_space,
304 if (added != txq->added) {
305 sfc_ef10_tx_qpush(txq, added, txq->added);
309 sfc_ef10_tx_reap(txq);
313 * Recalculate DMA descriptor space since Tx reap may change
314 * the number of completed descriptors
316 *dma_desc_space = txq->max_fill_level -
317 (added - txq->completed);
319 return (needed_desc <= *dma_desc_space);
323 sfc_ef10_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
326 struct sfc_ef10_txq * const txq = sfc_ef10_txq_by_dp_txq(tx_queue);
329 for (i = 0; i < nb_pkts; i++) {
330 struct rte_mbuf *m = tx_pkts[i];
333 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
335 * In non-TSO case, check that a packet segments do not exceed
336 * the size limit. Perform the check in debug mode since MTU
337 * more than 9k is not supported, but the limit here is 16k-1.
339 if (!(m->ol_flags & PKT_TX_TCP_SEG)) {
340 struct rte_mbuf *m_seg;
342 for (m_seg = m; m_seg != NULL; m_seg = m_seg->next) {
343 if (m_seg->data_len >
344 SFC_EF10_TX_DMA_DESC_LEN_MAX) {
351 ret = sfc_dp_tx_prepare_pkt(m,
352 txq->tso_tcp_header_offset_limit,
354 SFC_EF10_TSO_OPT_DESCS_NUM, 0);
355 if (unlikely(ret != 0)) {
365 sfc_ef10_xmit_tso_pkt(struct sfc_ef10_txq * const txq, struct rte_mbuf *m_seg,
366 unsigned int *added, unsigned int *dma_desc_space,
369 size_t iph_off = m_seg->l2_len;
370 size_t tcph_off = m_seg->l2_len + m_seg->l3_len;
371 size_t header_len = m_seg->l2_len + m_seg->l3_len + m_seg->l4_len;
372 /* Offset of the payload in the last segment that contains the header */
374 const struct tcp_hdr *th;
375 uint16_t packet_id = 0;
379 struct rte_mbuf *first_m_seg = m_seg;
380 unsigned int pkt_start = *added;
381 unsigned int needed_desc;
382 struct rte_mbuf *m_seg_to_free_up_to = first_m_seg;
386 * Preliminary estimation of required DMA descriptors, including extra
387 * descriptor for TSO header that is needed when the header is
388 * separated from payload in one segment. It does not include
389 * extra descriptors that may appear when a big segment is split across
390 * several descriptors.
392 needed_desc = m_seg->nb_segs +
393 (unsigned int)SFC_EF10_TSO_OPT_DESCS_NUM +
394 (unsigned int)SFC_EF10_TSO_HDR_DESCS_NUM;
396 if (needed_desc > *dma_desc_space &&
397 !sfc_ef10_try_reap(txq, pkt_start, needed_desc,
398 dma_desc_space, reap_done)) {
400 * If a future Tx reap may increase available DMA descriptor
401 * space, do not try to send the packet.
403 if (txq->completed != pkt_start)
406 * Do not allow to send packet if the maximum DMA
407 * descriptor space is not sufficient to hold TSO
408 * descriptors, header descriptor and at least 1
409 * segment descriptor.
411 if (*dma_desc_space < SFC_EF10_TSO_OPT_DESCS_NUM +
412 SFC_EF10_TSO_HDR_DESCS_NUM + 1)
416 /* Check if the header is not fragmented */
417 if (rte_pktmbuf_data_len(m_seg) >= header_len) {
418 hdr_addr = rte_pktmbuf_mtod(m_seg, uint8_t *);
419 hdr_iova = rte_mbuf_data_iova(m_seg);
420 if (rte_pktmbuf_data_len(m_seg) == header_len) {
421 /* Cannot send a packet that consists only of header */
422 if (unlikely(m_seg->next == NULL))
425 * Associate header mbuf with header descriptor
426 * which is located after TSO descriptors.
428 txq->sw_ring[(pkt_start + SFC_EF10_TSO_OPT_DESCS_NUM) &
429 txq->ptr_mask].mbuf = m_seg;
434 * If there is no payload offset (payload starts at the
435 * beginning of a segment) then an extra descriptor for
436 * separated header is not needed.
443 unsigned int copied_segs;
444 unsigned int hdr_addr_off = (*added & txq->ptr_mask) *
448 * Discard a packet if header linearization is needed but
449 * the header is too big.
450 * Duplicate Tx prepare check here to avoid spoil of
451 * memory if Tx prepare is skipped.
453 if (unlikely(header_len > SFC_TSOH_STD_LEN))
456 hdr_addr = txq->tsoh + hdr_addr_off;
457 hdr_iova = txq->tsoh_iova + hdr_addr_off;
458 copied_segs = sfc_tso_prepare_header(hdr_addr, header_len,
461 /* Cannot send a packet that consists only of header */
462 if (unlikely(m_seg == NULL))
465 m_seg_to_free_up_to = m_seg;
467 * Reduce the number of needed descriptors by the number of
468 * segments that entirely consist of header data.
470 needed_desc -= copied_segs;
472 /* Extra descriptor for separated header is not needed */
478 * Tx prepare has debug-only checks that offload flags are correctly
479 * filled in in TSO mbuf. Use zero IPID if there is no IPv4 flag.
480 * If the packet is still IPv4, HW will simply start from zero IPID.
482 if (first_m_seg->ol_flags & PKT_TX_IPV4)
483 packet_id = sfc_tso_ip4_get_ipid(hdr_addr, iph_off);
485 th = (const struct tcp_hdr *)(hdr_addr + tcph_off);
486 rte_memcpy(&sent_seq, &th->sent_seq, sizeof(uint32_t));
487 sent_seq = rte_be_to_cpu_32(sent_seq);
489 sfc_ef10_tx_qdesc_tso2_create(txq, *added, packet_id, 0, sent_seq,
490 first_m_seg->tso_segsz);
491 (*added) += SFC_EF10_TSO_OPT_DESCS_NUM;
493 sfc_ef10_tx_qdesc_dma_create(hdr_iova, header_len, false,
494 &txq->txq_hw_ring[(*added) & txq->ptr_mask]);
498 rte_iova_t next_frag = rte_mbuf_data_iova(m_seg);
499 unsigned int seg_len = rte_pktmbuf_data_len(m_seg);
507 rte_iova_t frag_addr = next_frag;
510 frag_len = RTE_MIN(seg_len,
511 SFC_EF10_TX_DMA_DESC_LEN_MAX);
513 next_frag += frag_len;
516 eop = (seg_len == 0 && m_seg->next == NULL);
518 id = (*added) & txq->ptr_mask;
522 * Initially we assume that one DMA descriptor is needed
523 * for every segment. When the segment is split across
524 * several DMA descriptors, increase the estimation.
526 needed_desc += (seg_len != 0);
529 * When no more descriptors can be added, but not all
530 * segments are processed.
532 if (*added - pkt_start == *dma_desc_space &&
534 !sfc_ef10_try_reap(txq, pkt_start, needed_desc,
535 dma_desc_space, reap_done)) {
537 struct rte_mbuf *m_next;
539 if (txq->completed != pkt_start) {
543 * Reset mbuf associations with added
546 for (i = pkt_start; i != *added; i++) {
547 id = i & txq->ptr_mask;
548 txq->sw_ring[id].mbuf = NULL;
553 /* Free the segments that cannot be sent */
554 for (m = m_seg->next; m != NULL; m = m_next) {
556 rte_pktmbuf_free_seg(m);
559 /* Ignore the rest of the segment */
563 sfc_ef10_tx_qdesc_dma_create(frag_addr, frag_len,
564 eop, &txq->txq_hw_ring[id]);
566 } while (seg_len != 0);
568 txq->sw_ring[id].mbuf = m_seg;
574 * Free segments which content was entirely copied to the TSO header
575 * memory space of Tx queue
577 for (m_seg = first_m_seg; m_seg != m_seg_to_free_up_to;) {
578 struct rte_mbuf *seg_to_free = m_seg;
581 rte_pktmbuf_free_seg(seg_to_free);
588 sfc_ef10_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
590 struct sfc_ef10_txq * const txq = sfc_ef10_txq_by_dp_txq(tx_queue);
592 unsigned int dma_desc_space;
594 struct rte_mbuf **pktp;
595 struct rte_mbuf **pktp_end;
597 if (unlikely(txq->flags &
598 (SFC_EF10_TXQ_NOT_RUNNING | SFC_EF10_TXQ_EXCEPTION)))
602 dma_desc_space = txq->max_fill_level - (added - txq->completed);
604 reap_done = (dma_desc_space < txq->free_thresh);
606 sfc_ef10_tx_reap(txq);
607 dma_desc_space = txq->max_fill_level - (added - txq->completed);
610 for (pktp = &tx_pkts[0], pktp_end = &tx_pkts[nb_pkts];
613 struct rte_mbuf *m_seg = *pktp;
614 unsigned int pkt_start = added;
617 if (likely(pktp + 1 != pktp_end))
618 rte_mbuf_prefetch_part1(pktp[1]);
620 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
623 rc = sfc_ef10_xmit_tso_pkt(txq, m_seg, &added,
624 &dma_desc_space, &reap_done);
628 /* Packet can be sent in following xmit calls */
629 if (likely(rc == ENOSPC))
633 * Packet cannot be sent, tell RTE that
634 * it is sent, but actually drop it and
635 * continue with another packet
637 rte_pktmbuf_free(*pktp);
641 goto dma_desc_space_update;
644 if (sfc_ef10_tx_pkt_descs_max(m_seg) > dma_desc_space) {
648 /* Push already prepared descriptors before polling */
649 if (added != txq->added) {
650 sfc_ef10_tx_qpush(txq, added, txq->added);
654 sfc_ef10_tx_reap(txq);
656 dma_desc_space = txq->max_fill_level -
657 (added - txq->completed);
658 if (sfc_ef10_tx_pkt_descs_max(m_seg) > dma_desc_space)
662 pkt_len = m_seg->pkt_len;
664 rte_iova_t seg_addr = rte_mbuf_data_iova(m_seg);
665 unsigned int seg_len = rte_pktmbuf_data_len(m_seg);
666 unsigned int id = added & txq->ptr_mask;
668 SFC_ASSERT(seg_len <= SFC_EF10_TX_DMA_DESC_LEN_MAX);
672 sfc_ef10_tx_qdesc_dma_create(seg_addr,
673 seg_len, (pkt_len == 0),
674 &txq->txq_hw_ring[id]);
677 * rte_pktmbuf_free() is commonly used in DPDK for
678 * recycling packets - the function checks every
679 * segment's reference counter and returns the
680 * buffer to its pool whenever possible;
681 * nevertheless, freeing mbuf segments one by one
682 * may entail some performance decline;
683 * from this point, sfc_efx_tx_reap() does the same job
684 * on its own and frees buffers in bulks (all mbufs
685 * within a bulk belong to the same pool);
686 * from this perspective, individual segment pointers
687 * must be associated with the corresponding SW
688 * descriptors independently so that only one loop
689 * is sufficient on reap to inspect all the buffers
691 txq->sw_ring[id].mbuf = m_seg;
695 } while ((m_seg = m_seg->next) != 0);
697 dma_desc_space_update:
698 dma_desc_space -= (added - pkt_start);
701 if (likely(added != txq->added)) {
702 sfc_ef10_tx_qpush(txq, added, txq->added);
706 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
708 sfc_ef10_tx_reap(txq);
711 return pktp - &tx_pkts[0];
715 sfc_ef10_simple_tx_reap(struct sfc_ef10_txq *txq)
717 const unsigned int old_read_ptr = txq->evq_read_ptr;
718 const unsigned int ptr_mask = txq->ptr_mask;
719 unsigned int completed = txq->completed;
720 unsigned int pending = completed;
722 pending += sfc_ef10_tx_process_events(txq);
724 if (pending != completed) {
725 struct rte_mbuf *bulk[SFC_TX_REAP_BULK_SIZE];
729 struct sfc_ef10_tx_sw_desc *txd;
731 txd = &txq->sw_ring[completed & ptr_mask];
733 if (nb == RTE_DIM(bulk)) {
734 rte_mempool_put_bulk(bulk[0]->pool,
739 bulk[nb++] = txd->mbuf;
740 } while (++completed != pending);
742 rte_mempool_put_bulk(bulk[0]->pool, (void *)bulk, nb);
744 txq->completed = completed;
747 sfc_ef10_ev_qclear(txq->evq_hw_ring, ptr_mask, old_read_ptr,
751 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
753 sfc_ef10_simple_prepare_pkts(__rte_unused void *tx_queue,
754 struct rte_mbuf **tx_pkts,
759 for (i = 0; i < nb_pkts; i++) {
760 struct rte_mbuf *m = tx_pkts[i];
763 ret = rte_validate_tx_offload(m);
764 if (unlikely(ret != 0)) {
766 * Negative error code is returned by
767 * rte_validate_tx_offload(), but positive are used
768 * inside net/sfc PMD.
775 /* ef10_simple does not support TSO and VLAN insertion */
776 if (unlikely(m->ol_flags &
777 (PKT_TX_TCP_SEG | PKT_TX_VLAN_PKT))) {
782 /* ef10_simple does not support scattered packets */
783 if (unlikely(m->nb_segs != 1)) {
789 * ef10_simple requires fast-free which ignores reference
792 if (unlikely(rte_mbuf_refcnt_read(m) != 1)) {
797 /* ef10_simple requires single pool for all packets */
798 if (unlikely(m->pool != tx_pkts[0]->pool)) {
809 sfc_ef10_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
812 struct sfc_ef10_txq * const txq = sfc_ef10_txq_by_dp_txq(tx_queue);
813 unsigned int ptr_mask;
815 unsigned int dma_desc_space;
817 struct rte_mbuf **pktp;
818 struct rte_mbuf **pktp_end;
820 if (unlikely(txq->flags &
821 (SFC_EF10_TXQ_NOT_RUNNING | SFC_EF10_TXQ_EXCEPTION)))
824 ptr_mask = txq->ptr_mask;
826 dma_desc_space = txq->max_fill_level - (added - txq->completed);
828 reap_done = (dma_desc_space < RTE_MAX(txq->free_thresh, nb_pkts));
830 sfc_ef10_simple_tx_reap(txq);
831 dma_desc_space = txq->max_fill_level - (added - txq->completed);
834 pktp_end = &tx_pkts[MIN(nb_pkts, dma_desc_space)];
835 for (pktp = &tx_pkts[0]; pktp != pktp_end; ++pktp) {
836 struct rte_mbuf *pkt = *pktp;
837 unsigned int id = added & ptr_mask;
839 SFC_ASSERT(rte_pktmbuf_data_len(pkt) <=
840 SFC_EF10_TX_DMA_DESC_LEN_MAX);
842 sfc_ef10_tx_qdesc_dma_create(rte_mbuf_data_iova(pkt),
843 rte_pktmbuf_data_len(pkt),
844 true, &txq->txq_hw_ring[id]);
846 txq->sw_ring[id].mbuf = pkt;
851 if (likely(added != txq->added)) {
852 sfc_ef10_tx_qpush(txq, added, txq->added);
856 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
858 sfc_ef10_simple_tx_reap(txq);
861 return pktp - &tx_pkts[0];
864 static sfc_dp_tx_get_dev_info_t sfc_ef10_get_dev_info;
866 sfc_ef10_get_dev_info(struct rte_eth_dev_info *dev_info)
869 * Number of descriptors just defines maximum number of pushed
870 * descriptors (fill level).
872 dev_info->tx_desc_lim.nb_min = 1;
873 dev_info->tx_desc_lim.nb_align = 1;
876 static sfc_dp_tx_qsize_up_rings_t sfc_ef10_tx_qsize_up_rings;
878 sfc_ef10_tx_qsize_up_rings(uint16_t nb_tx_desc,
879 struct sfc_dp_tx_hw_limits *limits,
880 unsigned int *txq_entries,
881 unsigned int *evq_entries,
882 unsigned int *txq_max_fill_level)
885 * rte_ethdev API guarantees that the number meets min, max and
886 * alignment requirements.
888 if (nb_tx_desc <= limits->txq_min_entries)
889 *txq_entries = limits->txq_min_entries;
891 *txq_entries = rte_align32pow2(nb_tx_desc);
893 *evq_entries = *txq_entries;
895 *txq_max_fill_level = RTE_MIN(nb_tx_desc,
896 SFC_EF10_TXQ_LIMIT(*evq_entries));
900 static sfc_dp_tx_qcreate_t sfc_ef10_tx_qcreate;
902 sfc_ef10_tx_qcreate(uint16_t port_id, uint16_t queue_id,
903 const struct rte_pci_addr *pci_addr, int socket_id,
904 const struct sfc_dp_tx_qcreate_info *info,
905 struct sfc_dp_txq **dp_txqp)
907 struct sfc_ef10_txq *txq;
911 if (info->txq_entries != info->evq_entries)
915 txq = rte_zmalloc_socket("sfc-ef10-txq", sizeof(*txq),
916 RTE_CACHE_LINE_SIZE, socket_id);
920 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
923 txq->sw_ring = rte_calloc_socket("sfc-ef10-txq-sw_ring",
925 sizeof(*txq->sw_ring),
926 RTE_CACHE_LINE_SIZE, socket_id);
927 if (txq->sw_ring == NULL)
928 goto fail_sw_ring_alloc;
930 if (info->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
931 txq->tsoh = rte_calloc_socket("sfc-ef10-txq-tsoh",
936 if (txq->tsoh == NULL)
937 goto fail_tsoh_alloc;
939 txq->tsoh_iova = rte_malloc_virt2iova(txq->tsoh);
942 txq->flags = SFC_EF10_TXQ_NOT_RUNNING;
943 txq->ptr_mask = info->txq_entries - 1;
944 txq->max_fill_level = info->max_fill_level;
945 txq->free_thresh = info->free_thresh;
946 txq->txq_hw_ring = info->txq_hw_ring;
947 txq->doorbell = (volatile uint8_t *)info->mem_bar +
948 ER_DZ_TX_DESC_UPD_REG_OFST +
949 (info->hw_index << info->vi_window_shift);
950 txq->evq_hw_ring = info->evq_hw_ring;
951 txq->tso_tcp_header_offset_limit = info->tso_tcp_header_offset_limit;
957 rte_free(txq->sw_ring);
967 static sfc_dp_tx_qdestroy_t sfc_ef10_tx_qdestroy;
969 sfc_ef10_tx_qdestroy(struct sfc_dp_txq *dp_txq)
971 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
974 rte_free(txq->sw_ring);
978 static sfc_dp_tx_qstart_t sfc_ef10_tx_qstart;
980 sfc_ef10_tx_qstart(struct sfc_dp_txq *dp_txq, unsigned int evq_read_ptr,
981 unsigned int txq_desc_index)
983 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
985 txq->evq_read_ptr = evq_read_ptr;
986 txq->added = txq->completed = txq_desc_index;
988 txq->flags |= SFC_EF10_TXQ_STARTED;
989 txq->flags &= ~(SFC_EF10_TXQ_NOT_RUNNING | SFC_EF10_TXQ_EXCEPTION);
994 static sfc_dp_tx_qstop_t sfc_ef10_tx_qstop;
996 sfc_ef10_tx_qstop(struct sfc_dp_txq *dp_txq, unsigned int *evq_read_ptr)
998 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
1000 txq->flags |= SFC_EF10_TXQ_NOT_RUNNING;
1002 *evq_read_ptr = txq->evq_read_ptr;
1005 static sfc_dp_tx_qtx_ev_t sfc_ef10_tx_qtx_ev;
1007 sfc_ef10_tx_qtx_ev(struct sfc_dp_txq *dp_txq, __rte_unused unsigned int id)
1009 __rte_unused struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
1011 SFC_ASSERT(txq->flags & SFC_EF10_TXQ_NOT_RUNNING);
1014 * It is safe to ignore Tx event since we reap all mbufs on
1015 * queue purge anyway.
1021 static sfc_dp_tx_qreap_t sfc_ef10_tx_qreap;
1023 sfc_ef10_tx_qreap(struct sfc_dp_txq *dp_txq)
1025 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
1026 unsigned int completed;
1028 for (completed = txq->completed; completed != txq->added; ++completed) {
1029 struct sfc_ef10_tx_sw_desc *txd;
1031 txd = &txq->sw_ring[completed & txq->ptr_mask];
1032 if (txd->mbuf != NULL) {
1033 rte_pktmbuf_free_seg(txd->mbuf);
1038 txq->flags &= ~SFC_EF10_TXQ_STARTED;
1042 sfc_ef10_tx_qdesc_npending(struct sfc_ef10_txq *txq)
1044 const unsigned int curr_done = txq->completed - 1;
1045 unsigned int anew_done = curr_done;
1047 const unsigned int evq_old_read_ptr = txq->evq_read_ptr;
1049 if (unlikely(txq->flags &
1050 (SFC_EF10_TXQ_NOT_RUNNING | SFC_EF10_TXQ_EXCEPTION)))
1053 while (sfc_ef10_tx_get_event(txq, &tx_ev))
1054 anew_done = EFX_QWORD_FIELD(tx_ev, ESF_DZ_TX_DESCR_INDX);
1057 * The function does not process events, so return event queue read
1058 * pointer to the original position to allow the events that were
1059 * read to be processed later
1061 txq->evq_read_ptr = evq_old_read_ptr;
1063 return (anew_done - curr_done) & txq->ptr_mask;
1066 static sfc_dp_tx_qdesc_status_t sfc_ef10_tx_qdesc_status;
1068 sfc_ef10_tx_qdesc_status(struct sfc_dp_txq *dp_txq,
1071 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
1072 unsigned int npending = sfc_ef10_tx_qdesc_npending(txq);
1074 if (unlikely(offset > txq->ptr_mask))
1077 if (unlikely(offset >= txq->max_fill_level))
1078 return RTE_ETH_TX_DESC_UNAVAIL;
1080 if (unlikely(offset < npending))
1081 return RTE_ETH_TX_DESC_FULL;
1083 return RTE_ETH_TX_DESC_DONE;
1086 struct sfc_dp_tx sfc_ef10_tx = {
1088 .name = SFC_KVARG_DATAPATH_EF10,
1090 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF10,
1092 .features = SFC_DP_TX_FEAT_TSO |
1093 SFC_DP_TX_FEAT_MULTI_SEG |
1094 SFC_DP_TX_FEAT_MULTI_POOL |
1095 SFC_DP_TX_FEAT_REFCNT |
1096 SFC_DP_TX_FEAT_MULTI_PROCESS,
1097 .get_dev_info = sfc_ef10_get_dev_info,
1098 .qsize_up_rings = sfc_ef10_tx_qsize_up_rings,
1099 .qcreate = sfc_ef10_tx_qcreate,
1100 .qdestroy = sfc_ef10_tx_qdestroy,
1101 .qstart = sfc_ef10_tx_qstart,
1102 .qtx_ev = sfc_ef10_tx_qtx_ev,
1103 .qstop = sfc_ef10_tx_qstop,
1104 .qreap = sfc_ef10_tx_qreap,
1105 .qdesc_status = sfc_ef10_tx_qdesc_status,
1106 .pkt_prepare = sfc_ef10_prepare_pkts,
1107 .pkt_burst = sfc_ef10_xmit_pkts,
1110 struct sfc_dp_tx sfc_ef10_simple_tx = {
1112 .name = SFC_KVARG_DATAPATH_EF10_SIMPLE,
1115 .features = SFC_DP_TX_FEAT_MULTI_PROCESS,
1116 .get_dev_info = sfc_ef10_get_dev_info,
1117 .qsize_up_rings = sfc_ef10_tx_qsize_up_rings,
1118 .qcreate = sfc_ef10_tx_qcreate,
1119 .qdestroy = sfc_ef10_tx_qdestroy,
1120 .qstart = sfc_ef10_tx_qstart,
1121 .qtx_ev = sfc_ef10_tx_qtx_ev,
1122 .qstop = sfc_ef10_tx_qstop,
1123 .qreap = sfc_ef10_tx_qreap,
1124 .qdesc_status = sfc_ef10_tx_qdesc_status,
1125 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
1126 .pkt_prepare = sfc_ef10_simple_prepare_pkts,
1128 .pkt_burst = sfc_ef10_simple_xmit_pkts,