drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2021 Xilinx, Inc.
   4  * Copyright(c) 2016-2019 Solarflare Communications Inc.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_mae_counter.h"
  20 #include "sfc_kvargs.h"
  21 #include "sfc_tweak.h"
  22
  23 /*
  24  * Maximum number of Rx queue flush attempt in the case of failure or
  25  * flush timeout
  26  */
  27 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  28
  29 /*
  30  * Time to wait between event queue polling attempts when waiting for Rx
  31  * queue flush done or failed events.
  32  */
  33 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  34
  35 /*
  36  * Maximum number of event queue polling attempts when waiting for Rx queue
  37  * flush done or failed events. It defines Rx queue flush attempt timeout
  38  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  39  */
  40 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  41
  42 void
  43 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
  44 {
  45         rxq_info->state |= SFC_RXQ_FLUSHED;
  46         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  47 }
  48
  49 void
  50 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
  51 {
  52         rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
  53         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  54 }
  55
  56 static int
  57 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq)
  58 {
  59         int rc = 0;
  60
  61         if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) {
  62                 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr);
  63                 if (rc == 0)
  64                         rxq->evq->read_ptr_primed = rxq->evq->read_ptr;
  65         }
  66         return rc;
  67 }
  68
  69 static void
  70 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  71 {
  72         unsigned int free_space;
  73         unsigned int bulks;
  74         void *objs[SFC_RX_REFILL_BULK];
  75         efsys_dma_addr_t addr[RTE_DIM(objs)];
  76         unsigned int added = rxq->added;
  77         unsigned int id;
  78         unsigned int i;
  79         struct sfc_efx_rx_sw_desc *rxd;
  80         struct rte_mbuf *m;
  81         uint16_t port_id = rxq->dp.dpq.port_id;
  82
  83         free_space = rxq->max_fill_level - (added - rxq->completed);
  84
  85         if (free_space < rxq->refill_threshold)
  86                 return;
  87
  88         bulks = free_space / RTE_DIM(objs);
  89         /* refill_threshold guarantees that bulks is positive */
  90         SFC_ASSERT(bulks > 0);
  91
  92         id = added & rxq->ptr_mask;
  93         do {
  94                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
  95                                                   RTE_DIM(objs)) < 0)) {
  96                         /*
  97                          * It is hardly a safe way to increment counter
  98                          * from different contexts, but all PMDs do it.
  99                          */
 100                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
 101                                 RTE_DIM(objs);
 102                         /* Return if we have posted nothing yet */
 103                         if (added == rxq->added)
 104                                 return;
 105                         /* Push posted */
 106                         break;
 107                 }
 108
 109                 for (i = 0; i < RTE_DIM(objs);
 110                      ++i, id = (id + 1) & rxq->ptr_mask) {
 111                         m = objs[i];
 112
 113                         __rte_mbuf_raw_sanity_check(m);
 114
 115                         rxd = &rxq->sw_desc[id];
 116                         rxd->mbuf = m;
 117
 118                         m->data_off = RTE_PKTMBUF_HEADROOM;
 119                         m->port = port_id;
 120
 121                         addr[i] = rte_pktmbuf_iova(m);
 122                 }
 123
 124                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 125                              RTE_DIM(objs), rxq->completed, added);
 126                 added += RTE_DIM(objs);
 127         } while (--bulks > 0);
 128
 129         SFC_ASSERT(added != rxq->added);
 130         rxq->added = added;
 131         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 132 }
 133
 134 static uint64_t
 135 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 136 {
 137         uint64_t mbuf_flags = 0;
 138
 139         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 140         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 141                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 142                 break;
 143         case EFX_PKT_IPV4:
 144                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 145                 break;
 146         default:
 147                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 148                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 149                            PKT_RX_IP_CKSUM_UNKNOWN);
 150                 break;
 151         }
 152
 153         switch ((desc_flags &
 154                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 155         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 156         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 157                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 158                 break;
 159         case EFX_PKT_TCP:
 160         case EFX_PKT_UDP:
 161                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 162                 break;
 163         default:
 164                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 165                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 166                            PKT_RX_L4_CKSUM_UNKNOWN);
 167                 break;
 168         }
 169
 170         return mbuf_flags;
 171 }
 172
 173 static uint32_t
 174 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 175 {
 176         return RTE_PTYPE_L2_ETHER |
 177                 ((desc_flags & EFX_PKT_IPV4) ?
 178                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 179                 ((desc_flags & EFX_PKT_IPV6) ?
 180                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 181                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 182                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 183 }
 184
 185 static const uint32_t *
 186 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 187 {
 188         static const uint32_t ptypes[] = {
 189                 RTE_PTYPE_L2_ETHER,
 190                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 191                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 192                 RTE_PTYPE_L4_TCP,
 193                 RTE_PTYPE_L4_UDP,
 194                 RTE_PTYPE_UNKNOWN
 195         };
 196
 197         return ptypes;
 198 }
 199
 200 static void
 201 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 202                         struct rte_mbuf *m)
 203 {
 204         uint8_t *mbuf_data;
 205
 206
 207         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 208                 return;
 209
 210         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 211
 212         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 213                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 214                                                       EFX_RX_HASHALG_TOEPLITZ,
 215                                                       mbuf_data);
 216
 217                 m->ol_flags |= PKT_RX_RSS_HASH;
 218         }
 219 }
 220
 221 static uint16_t
 222 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 223 {
 224         struct sfc_dp_rxq *dp_rxq = rx_queue;
 225         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 226         unsigned int completed;
 227         unsigned int prefix_size = rxq->prefix_size;
 228         unsigned int done_pkts = 0;
 229         boolean_t discard_next = B_FALSE;
 230         struct rte_mbuf *scatter_pkt = NULL;
 231
 232         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 233                 return 0;
 234
 235         sfc_ev_qpoll(rxq->evq);
 236
 237         completed = rxq->completed;
 238         while (completed != rxq->pending && done_pkts < nb_pkts) {
 239                 unsigned int id;
 240                 struct sfc_efx_rx_sw_desc *rxd;
 241                 struct rte_mbuf *m;
 242                 unsigned int seg_len;
 243                 unsigned int desc_flags;
 244
 245                 id = completed++ & rxq->ptr_mask;
 246                 rxd = &rxq->sw_desc[id];
 247                 m = rxd->mbuf;
 248                 desc_flags = rxd->flags;
 249
 250                 if (discard_next)
 251                         goto discard;
 252
 253                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 254                         goto discard;
 255
 256                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 257                         uint16_t tmp_size;
 258                         int rc __rte_unused;
 259
 260                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 261                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 262                         SFC_ASSERT(rc == 0);
 263                         seg_len = tmp_size;
 264                 } else {
 265                         seg_len = rxd->size - prefix_size;
 266                 }
 267
 268                 rte_pktmbuf_data_len(m) = seg_len;
 269                 rte_pktmbuf_pkt_len(m) = seg_len;
 270
 271                 if (scatter_pkt != NULL) {
 272                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 273                                 rte_pktmbuf_free(scatter_pkt);
 274                                 goto discard;
 275                         }
 276                         /* The packet to deliver */
 277                         m = scatter_pkt;
 278                 }
 279
 280                 if (desc_flags & EFX_PKT_CONT) {
 281                         /* The packet is scattered, more fragments to come */
 282                         scatter_pkt = m;
 283                         /* Further fragments have no prefix */
 284                         prefix_size = 0;
 285                         continue;
 286                 }
 287
 288                 /* Scattered packet is done */
 289                 scatter_pkt = NULL;
 290                 /* The first fragment of the packet has prefix */
 291                 prefix_size = rxq->prefix_size;
 292
 293                 m->ol_flags =
 294                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 295                 m->packet_type =
 296                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 297
 298                 /*
 299                  * Extract RSS hash from the packet prefix and
 300                  * set the corresponding field (if needed and possible)
 301                  */
 302                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 303
 304                 m->data_off += prefix_size;
 305
 306                 *rx_pkts++ = m;
 307                 done_pkts++;
 308                 continue;
 309
 310 discard:
 311                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 312                 rte_mbuf_raw_free(m);
 313                 rxd->mbuf = NULL;
 314         }
 315
 316         /* pending is only moved when entire packet is received */
 317         SFC_ASSERT(scatter_pkt == NULL);
 318
 319         rxq->completed = completed;
 320
 321         sfc_efx_rx_qrefill(rxq);
 322
 323         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN)
 324                 sfc_efx_rx_qprime(rxq);
 325
 326         return done_pkts;
 327 }
 328
 329 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 330 static unsigned int
 331 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 332 {
 333         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 334
 335         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 336                 return 0;
 337
 338         sfc_ev_qpoll(rxq->evq);
 339
 340         return rxq->pending - rxq->completed;
 341 }
 342
 343 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 344 static int
 345 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 346 {
 347         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 348
 349         if (unlikely(offset > rxq->ptr_mask))
 350                 return -EINVAL;
 351
 352         /*
 353          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 354          * it is required for the queue to be running, but the
 355          * check is omitted because API design assumes that it
 356          * is the duty of the caller to satisfy all conditions
 357          */
 358         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 359                    SFC_EFX_RXQ_FLAG_RUNNING);
 360         sfc_ev_qpoll(rxq->evq);
 361
 362         /*
 363          * There is a handful of reserved entries in the ring,
 364          * but an explicit check whether the offset points to
 365          * a reserved entry is neglected since the two checks
 366          * below rely on the figures which take the HW limits
 367          * into account and thus if an entry is reserved, the
 368          * checks will fail and UNAVAIL code will be returned
 369          */
 370
 371         if (offset < (rxq->pending - rxq->completed))
 372                 return RTE_ETH_RX_DESC_DONE;
 373
 374         if (offset < (rxq->added - rxq->completed))
 375                 return RTE_ETH_RX_DESC_AVAIL;
 376
 377         return RTE_ETH_RX_DESC_UNAVAIL;
 378 }
 379
 380 boolean_t
 381 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size,
 382                      boolean_t rx_scatter_enabled, uint32_t rx_scatter_max,
 383                      const char **error)
 384 {
 385         uint32_t effective_rx_scatter_max;
 386         uint32_t rx_scatter_bufs;
 387
 388         effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1;
 389         rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size);
 390
 391         if (rx_scatter_bufs > effective_rx_scatter_max) {
 392                 if (rx_scatter_enabled)
 393                         *error = "Possible number of Rx scatter buffers exceeds maximum number";
 394                 else
 395                         *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small";
 396                 return B_FALSE;
 397         }
 398
 399         return B_TRUE;
 400 }
 401
 402 /** Get Rx datapath ops by the datapath RxQ handle */
 403 const struct sfc_dp_rx *
 404 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 405 {
 406         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 407         struct rte_eth_dev *eth_dev;
 408         struct sfc_adapter_priv *sap;
 409
 410         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 411         eth_dev = &rte_eth_devices[dpq->port_id];
 412
 413         sap = sfc_adapter_priv_by_eth_dev(eth_dev);
 414
 415         return sap->dp_rx;
 416 }
 417
 418 struct sfc_rxq_info *
 419 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 420 {
 421         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 422         struct rte_eth_dev *eth_dev;
 423         struct sfc_adapter_shared *sas;
 424
 425         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 426         eth_dev = &rte_eth_devices[dpq->port_id];
 427
 428         sas = sfc_adapter_shared_by_eth_dev(eth_dev);
 429
 430         SFC_ASSERT(dpq->queue_id < sas->rxq_count);
 431         return &sas->rxq_info[dpq->queue_id];
 432 }
 433
 434 struct sfc_rxq *
 435 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 436 {
 437         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 438         struct rte_eth_dev *eth_dev;
 439         struct sfc_adapter *sa;
 440
 441         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 442         eth_dev = &rte_eth_devices[dpq->port_id];
 443
 444         sa = sfc_adapter_by_eth_dev(eth_dev);
 445
 446         SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count);
 447         return &sa->rxq_ctrl[dpq->queue_id];
 448 }
 449
 450 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 451 static int
 452 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 453                           __rte_unused struct sfc_dp_rx_hw_limits *limits,
 454                           __rte_unused struct rte_mempool *mb_pool,
 455                           unsigned int *rxq_entries,
 456                           unsigned int *evq_entries,
 457                           unsigned int *rxq_max_fill_level)
 458 {
 459         *rxq_entries = nb_rx_desc;
 460         *evq_entries = nb_rx_desc;
 461         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 462         return 0;
 463 }
 464
 465 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 466 static int
 467 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 468                    const struct rte_pci_addr *pci_addr, int socket_id,
 469                    const struct sfc_dp_rx_qcreate_info *info,
 470                    struct sfc_dp_rxq **dp_rxqp)
 471 {
 472         struct sfc_efx_rxq *rxq;
 473         int rc;
 474
 475         rc = ENOMEM;
 476         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 477                                  RTE_CACHE_LINE_SIZE, socket_id);
 478         if (rxq == NULL)
 479                 goto fail_rxq_alloc;
 480
 481         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 482
 483         rc = ENOMEM;
 484         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 485                                          info->rxq_entries,
 486                                          sizeof(*rxq->sw_desc),
 487                                          RTE_CACHE_LINE_SIZE, socket_id);
 488         if (rxq->sw_desc == NULL)
 489                 goto fail_desc_alloc;
 490
 491         /* efx datapath is bound to efx control path */
 492         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 493         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 494                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 495         rxq->ptr_mask = info->rxq_entries - 1;
 496         rxq->batch_max = info->batch_max;
 497         rxq->prefix_size = info->prefix_size;
 498         rxq->max_fill_level = info->max_fill_level;
 499         rxq->refill_threshold = info->refill_threshold;
 500         rxq->buf_size = info->buf_size;
 501         rxq->refill_mb_pool = info->refill_mb_pool;
 502
 503         *dp_rxqp = &rxq->dp;
 504         return 0;
 505
 506 fail_desc_alloc:
 507         rte_free(rxq);
 508
 509 fail_rxq_alloc:
 510         return rc;
 511 }
 512
 513 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 514 static void
 515 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 516 {
 517         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 518
 519         rte_free(rxq->sw_desc);
 520         rte_free(rxq);
 521 }
 522
 523
 524 /* Use qstop and qstart functions in the case of qstart failure */
 525 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 526 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 527
 528
 529 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 530 static int
 531 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 532                   __rte_unused unsigned int evq_read_ptr,
 533                   const efx_rx_prefix_layout_t *pinfo)
 534 {
 535         /* libefx-based datapath is specific to libefx-based PMD */
 536         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 537         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 538         int rc;
 539
 540         /*
 541          * libefx API is used to extract information from Rx prefix and
 542          * it guarantees consistency. Just do length check to ensure
 543          * that we reserved space in Rx buffers correctly.
 544          */
 545         if (rxq->prefix_size != pinfo->erpl_length)
 546                 return ENOTSUP;
 547
 548         rxq->common = crxq->common;
 549
 550         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 551
 552         sfc_efx_rx_qrefill(rxq);
 553
 554         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 555
 556         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) {
 557                 rc = sfc_efx_rx_qprime(rxq);
 558                 if (rc != 0)
 559                         goto fail_rx_qprime;
 560         }
 561
 562         return 0;
 563
 564 fail_rx_qprime:
 565         sfc_efx_rx_qstop(dp_rxq, NULL);
 566         sfc_efx_rx_qpurge(dp_rxq);
 567         return rc;
 568 }
 569
 570 static void
 571 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 572                  __rte_unused unsigned int *evq_read_ptr)
 573 {
 574         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 575
 576         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 577
 578         /* libefx-based datapath is bound to libefx-based PMD and uses
 579          * event queue structure directly. So, there is no necessity to
 580          * return EvQ read pointer.
 581          */
 582 }
 583
 584 static void
 585 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 586 {
 587         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 588         unsigned int i;
 589         struct sfc_efx_rx_sw_desc *rxd;
 590
 591         for (i = rxq->completed; i != rxq->added; ++i) {
 592                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 593                 rte_mbuf_raw_free(rxd->mbuf);
 594                 rxd->mbuf = NULL;
 595                 /* Packed stream relies on 0 in inactive SW desc.
 596                  * Rx queue stop is not performance critical, so
 597                  * there is no harm to do it always.
 598                  */
 599                 rxd->flags = 0;
 600                 rxd->size = 0;
 601         }
 602
 603         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 604 }
 605
 606 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable;
 607 static int
 608 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
 609 {
 610         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 611         int rc = 0;
 612
 613         rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN;
 614         if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) {
 615                 rc = sfc_efx_rx_qprime(rxq);
 616                 if (rc != 0)
 617                         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 618         }
 619         return rc;
 620 }
 621
 622 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable;
 623 static int
 624 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
 625 {
 626         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 627
 628         /* Cannot disarm, just disable rearm */
 629         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 630         return 0;
 631 }
 632
 633 struct sfc_dp_rx sfc_efx_rx = {
 634         .dp = {
 635                 .name           = SFC_KVARG_DATAPATH_EFX,
 636                 .type           = SFC_DP_RX,
 637                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_RX_EFX,
 638         },
 639         .features               = SFC_DP_RX_FEAT_INTR,
 640         .dev_offload_capa       = DEV_RX_OFFLOAD_CHECKSUM |
 641                                   DEV_RX_OFFLOAD_RSS_HASH,
 642         .queue_offload_capa     = DEV_RX_OFFLOAD_SCATTER,
 643         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 644         .qcreate                = sfc_efx_rx_qcreate,
 645         .qdestroy               = sfc_efx_rx_qdestroy,
 646         .qstart                 = sfc_efx_rx_qstart,
 647         .qstop                  = sfc_efx_rx_qstop,
 648         .qpurge                 = sfc_efx_rx_qpurge,
 649         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 650         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 651         .qdesc_status           = sfc_efx_rx_qdesc_status,
 652         .intr_enable            = sfc_efx_rx_intr_enable,
 653         .intr_disable           = sfc_efx_rx_intr_disable,
 654         .pkt_burst              = sfc_efx_recv_pkts,
 655 };
 656
 657 static void
 658 sfc_rx_qflush(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 659 {
 660         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 661         sfc_ethdev_qid_t ethdev_qid;
 662         struct sfc_rxq_info *rxq_info;
 663         struct sfc_rxq *rxq;
 664         unsigned int retry_count;
 665         unsigned int wait_count;
 666         int rc;
 667
 668         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 669         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 670         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 671
 672         rxq = &sa->rxq_ctrl[sw_index];
 673
 674         /*
 675          * Retry Rx queue flushing in the case of flush failed or
 676          * timeout. In the worst case it can delay for 6 seconds.
 677          */
 678         for (retry_count = 0;
 679              ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
 680              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 681              ++retry_count) {
 682                 rc = efx_rx_qflush(rxq->common);
 683                 if (rc != 0) {
 684                         rxq_info->state |= (rc == EALREADY) ?
 685                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 686                         break;
 687                 }
 688                 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
 689                 rxq_info->state |= SFC_RXQ_FLUSHING;
 690
 691                 /*
 692                  * Wait for Rx queue flush done or failed event at least
 693                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 694                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 695                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 696                  */
 697                 wait_count = 0;
 698                 do {
 699                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 700                         sfc_ev_qpoll(rxq->evq);
 701                 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
 702                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 703
 704                 if (rxq_info->state & SFC_RXQ_FLUSHING)
 705                         sfc_err(sa, "RxQ %d (internal %u) flush timed out",
 706                                 ethdev_qid, sw_index);
 707
 708                 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
 709                         sfc_err(sa, "RxQ %d (internal %u) flush failed",
 710                                 ethdev_qid, sw_index);
 711
 712                 if (rxq_info->state & SFC_RXQ_FLUSHED)
 713                         sfc_notice(sa, "RxQ %d (internal %u) flushed",
 714                                    ethdev_qid, sw_index);
 715         }
 716
 717         sa->priv.dp_rx->qpurge(rxq_info->dp);
 718 }
 719
 720 static int
 721 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 722 {
 723         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
 724         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 725         struct sfc_port *port = &sa->port;
 726         int rc;
 727
 728         /*
 729          * If promiscuous or all-multicast mode has been requested, setting
 730          * filter for the default Rx queue might fail, in particular, while
 731          * running over PCI function which is not a member of corresponding
 732          * privilege groups; if this occurs, few iterations will be made to
 733          * repeat this step without promiscuous and all-multicast flags set
 734          */
 735 retry:
 736         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 737         if (rc == 0)
 738                 return 0;
 739         else if (rc != EOPNOTSUPP)
 740                 return rc;
 741
 742         if (port->promisc) {
 743                 sfc_warn(sa, "promiscuous mode has been requested, "
 744                              "but the HW rejects it");
 745                 sfc_warn(sa, "promiscuous mode will be disabled");
 746
 747                 port->promisc = B_FALSE;
 748                 sa->eth_dev->data->promiscuous = 0;
 749                 rc = sfc_set_rx_mode_unchecked(sa);
 750                 if (rc != 0)
 751                         return rc;
 752
 753                 goto retry;
 754         }
 755
 756         if (port->allmulti) {
 757                 sfc_warn(sa, "all-multicast mode has been requested, "
 758                              "but the HW rejects it");
 759                 sfc_warn(sa, "all-multicast mode will be disabled");
 760
 761                 port->allmulti = B_FALSE;
 762                 sa->eth_dev->data->all_multicast = 0;
 763                 rc = sfc_set_rx_mode_unchecked(sa);
 764                 if (rc != 0)
 765                         return rc;
 766
 767                 goto retry;
 768         }
 769
 770         return rc;
 771 }
 772
 773 int
 774 sfc_rx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 775 {
 776         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 777         sfc_ethdev_qid_t ethdev_qid;
 778         struct sfc_rxq_info *rxq_info;
 779         struct sfc_rxq *rxq;
 780         struct sfc_evq *evq;
 781         efx_rx_prefix_layout_t pinfo;
 782         int rc;
 783
 784         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 785         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 786
 787         sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
 788
 789         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 790         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
 791
 792         rxq = &sa->rxq_ctrl[sw_index];
 793         evq = rxq->evq;
 794
 795         rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index));
 796         if (rc != 0)
 797                 goto fail_ev_qstart;
 798
 799         switch (rxq_info->type) {
 800         case EFX_RXQ_TYPE_DEFAULT:
 801                 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 802                         rxq->buf_size,
 803                         &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
 804                         rxq_info->type_flags, evq->common, &rxq->common);
 805                 break;
 806         case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
 807                 struct rte_mempool *mp = rxq_info->refill_mb_pool;
 808                 struct rte_mempool_info mp_info;
 809
 810                 rc = rte_mempool_ops_get_info(mp, &mp_info);
 811                 if (rc != 0) {
 812                         /* Positive errno is used in the driver */
 813                         rc = -rc;
 814                         goto fail_mp_get_info;
 815                 }
 816                 if (mp_info.contig_block_size <= 0) {
 817                         rc = EINVAL;
 818                         goto fail_bad_contig_block_size;
 819                 }
 820                 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
 821                         mp_info.contig_block_size, rxq->buf_size,
 822                         mp->header_size + mp->elt_size + mp->trailer_size,
 823                         sa->rxd_wait_timeout_ns,
 824                         &rxq->mem, rxq_info->entries, rxq_info->type_flags,
 825                         evq->common, &rxq->common);
 826                 break;
 827         }
 828         default:
 829                 rc = ENOTSUP;
 830         }
 831         if (rc != 0)
 832                 goto fail_rx_qcreate;
 833
 834         rc = efx_rx_prefix_get_layout(rxq->common, &pinfo);
 835         if (rc != 0)
 836                 goto fail_prefix_get_layout;
 837
 838         efx_rx_qenable(rxq->common);
 839
 840         rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr, &pinfo);
 841         if (rc != 0)
 842                 goto fail_dp_qstart;
 843
 844         rxq_info->state |= SFC_RXQ_STARTED;
 845
 846         if (ethdev_qid == 0 && !sfc_sa2shared(sa)->isolated) {
 847                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 848                 if (rc != 0)
 849                         goto fail_mac_filter_default_rxq_set;
 850         }
 851
 852         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 853         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
 854                 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
 855                         RTE_ETH_QUEUE_STATE_STARTED;
 856
 857         return 0;
 858
 859 fail_mac_filter_default_rxq_set:
 860         sfc_rx_qflush(sa, sw_index);
 861         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 862         rxq_info->state = SFC_RXQ_INITIALIZED;
 863
 864 fail_dp_qstart:
 865         efx_rx_qdestroy(rxq->common);
 866
 867 fail_prefix_get_layout:
 868 fail_rx_qcreate:
 869 fail_bad_contig_block_size:
 870 fail_mp_get_info:
 871         sfc_ev_qstop(evq);
 872
 873 fail_ev_qstart:
 874         return rc;
 875 }
 876
 877 void
 878 sfc_rx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 879 {
 880         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 881         sfc_ethdev_qid_t ethdev_qid;
 882         struct sfc_rxq_info *rxq_info;
 883         struct sfc_rxq *rxq;
 884
 885         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 886         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 887
 888         sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
 889
 890         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 891
 892         if (rxq_info->state == SFC_RXQ_INITIALIZED)
 893                 return;
 894         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 895
 896         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 897         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
 898                 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
 899                         RTE_ETH_QUEUE_STATE_STOPPED;
 900
 901         rxq = &sa->rxq_ctrl[sw_index];
 902         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 903
 904         if (ethdev_qid == 0)
 905                 efx_mac_filter_default_rxq_clear(sa->nic);
 906
 907         sfc_rx_qflush(sa, sw_index);
 908
 909         rxq_info->state = SFC_RXQ_INITIALIZED;
 910
 911         efx_rx_qdestroy(rxq->common);
 912
 913         sfc_ev_qstop(rxq->evq);
 914 }
 915
 916 static uint64_t
 917 sfc_rx_get_offload_mask(struct sfc_adapter *sa)
 918 {
 919         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 920         uint64_t no_caps = 0;
 921
 922         if (encp->enc_tunnel_encapsulations_supported == 0)
 923                 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 924
 925         return ~no_caps;
 926 }
 927
 928 uint64_t
 929 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 930 {
 931         uint64_t caps = sa->priv.dp_rx->dev_offload_capa;
 932
 933         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 934
 935         return caps & sfc_rx_get_offload_mask(sa);
 936 }
 937
 938 uint64_t
 939 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 940 {
 941         return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa);
 942 }
 943
 944 static int
 945 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 946                    const struct rte_eth_rxconf *rx_conf,
 947                    __rte_unused uint64_t offloads)
 948 {
 949         int rc = 0;
 950
 951         if (rx_conf->rx_thresh.pthresh != 0 ||
 952             rx_conf->rx_thresh.hthresh != 0 ||
 953             rx_conf->rx_thresh.wthresh != 0) {
 954                 sfc_warn(sa,
 955                         "RxQ prefetch/host/writeback thresholds are not supported");
 956         }
 957
 958         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 959                 sfc_err(sa,
 960                         "RxQ free threshold too large: %u vs maximum %u",
 961                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 962                 rc = EINVAL;
 963         }
 964
 965         if (rx_conf->rx_drop_en == 0) {
 966                 sfc_err(sa, "RxQ drop disable is not supported");
 967                 rc = EINVAL;
 968         }
 969
 970         return rc;
 971 }
 972
 973 static unsigned int
 974 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 975 {
 976         uint32_t data_off;
 977         uint32_t order;
 978
 979         /* The mbuf object itself is always cache line aligned */
 980         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 981
 982         /* Data offset from mbuf object start */
 983         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 984                 RTE_PKTMBUF_HEADROOM;
 985
 986         order = MIN(order, rte_bsf32(data_off));
 987
 988         return 1u << order;
 989 }
 990
 991 static uint16_t
 992 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
 993 {
 994         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 995         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
 996         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
 997         uint16_t buf_size;
 998         unsigned int buf_aligned;
 999         unsigned int start_alignment;
1000         unsigned int end_padding_alignment;
1001
1002         /* Below it is assumed that both alignments are power of 2 */
1003         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
1004         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
1005
1006         /*
1007          * mbuf is always cache line aligned, double-check
1008          * that it meets rx buffer start alignment requirements.
1009          */
1010
1011         /* Start from mbuf pool data room size */
1012         buf_size = rte_pktmbuf_data_room_size(mb_pool);
1013
1014         /* Remove headroom */
1015         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
1016                 sfc_err(sa,
1017                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
1018                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
1019                 return 0;
1020         }
1021         buf_size -= RTE_PKTMBUF_HEADROOM;
1022
1023         /* Calculate guaranteed data start alignment */
1024         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
1025
1026         /* Reserve space for start alignment */
1027         if (buf_aligned < nic_align_start) {
1028                 start_alignment = nic_align_start - buf_aligned;
1029                 if (buf_size <= start_alignment) {
1030                         sfc_err(sa,
1031                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
1032                                 mb_pool->name,
1033                                 rte_pktmbuf_data_room_size(mb_pool),
1034                                 RTE_PKTMBUF_HEADROOM, start_alignment);
1035                         return 0;
1036                 }
1037                 buf_aligned = nic_align_start;
1038                 buf_size -= start_alignment;
1039         } else {
1040                 start_alignment = 0;
1041         }
1042
1043         /* Make sure that end padding does not write beyond the buffer */
1044         if (buf_aligned < nic_align_end) {
1045                 /*
1046                  * Estimate space which can be lost. If guarnteed buffer
1047                  * size is odd, lost space is (nic_align_end - 1). More
1048                  * accurate formula is below.
1049                  */
1050                 end_padding_alignment = nic_align_end -
1051                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
1052                 if (buf_size <= end_padding_alignment) {
1053                         sfc_err(sa,
1054                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
1055                                 mb_pool->name,
1056                                 rte_pktmbuf_data_room_size(mb_pool),
1057                                 RTE_PKTMBUF_HEADROOM, start_alignment,
1058                                 end_padding_alignment);
1059                         return 0;
1060                 }
1061                 buf_size -= end_padding_alignment;
1062         } else {
1063                 /*
1064                  * Start is aligned the same or better than end,
1065                  * just align length.
1066                  */
1067                 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end);
1068         }
1069
1070         return buf_size;
1071 }
1072
1073 int
1074 sfc_rx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1075              uint16_t nb_rx_desc, unsigned int socket_id,
1076              const struct rte_eth_rxconf *rx_conf,
1077              struct rte_mempool *mb_pool)
1078 {
1079         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1080         sfc_ethdev_qid_t ethdev_qid;
1081         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1082         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1083         int rc;
1084         unsigned int rxq_entries;
1085         unsigned int evq_entries;
1086         unsigned int rxq_max_fill_level;
1087         uint64_t offloads;
1088         uint16_t buf_size;
1089         struct sfc_rxq_info *rxq_info;
1090         struct sfc_evq *evq;
1091         struct sfc_rxq *rxq;
1092         struct sfc_dp_rx_qcreate_info info;
1093         struct sfc_dp_rx_hw_limits hw_limits;
1094         uint16_t rx_free_thresh;
1095         const char *error;
1096
1097         memset(&hw_limits, 0, sizeof(hw_limits));
1098         hw_limits.rxq_max_entries = sa->rxq_max_entries;
1099         hw_limits.rxq_min_entries = sa->rxq_min_entries;
1100         hw_limits.evq_max_entries = sa->evq_max_entries;
1101         hw_limits.evq_min_entries = sa->evq_min_entries;
1102
1103         rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool,
1104                                             &rxq_entries, &evq_entries,
1105                                             &rxq_max_fill_level);
1106         if (rc != 0)
1107                 goto fail_size_up_rings;
1108         SFC_ASSERT(rxq_entries >= sa->rxq_min_entries);
1109         SFC_ASSERT(rxq_entries <= sa->rxq_max_entries);
1110         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
1111
1112         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1113
1114         offloads = rx_conf->offloads;
1115         /* Add device level Rx offloads if the queue is an ethdev Rx queue */
1116         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1117                 offloads |= sa->eth_dev->data->dev_conf.rxmode.offloads;
1118
1119         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
1120         if (rc != 0)
1121                 goto fail_bad_conf;
1122
1123         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1124         if (buf_size == 0) {
1125                 sfc_err(sa,
1126                         "RxQ %d (internal %u) mbuf pool object size is too small",
1127                         ethdev_qid, sw_index);
1128                 rc = EINVAL;
1129                 goto fail_bad_conf;
1130         }
1131
1132         if (!sfc_rx_check_scatter(sa->port.pdu, buf_size,
1133                                   encp->enc_rx_prefix_size,
1134                                   (offloads & DEV_RX_OFFLOAD_SCATTER),
1135                                   encp->enc_rx_scatter_max,
1136                                   &error)) {
1137                 sfc_err(sa, "RxQ %d (internal %u) MTU check failed: %s",
1138                         ethdev_qid, sw_index, error);
1139                 sfc_err(sa,
1140                         "RxQ %d (internal %u) calculated Rx buffer size is %u vs "
1141                         "PDU size %u plus Rx prefix %u bytes",
1142                         ethdev_qid, sw_index, buf_size,
1143                         (unsigned int)sa->port.pdu, encp->enc_rx_prefix_size);
1144                 rc = EINVAL;
1145                 goto fail_bad_conf;
1146         }
1147
1148         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1149         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1150
1151         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1152         rxq_info->entries = rxq_entries;
1153
1154         if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1155                 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1156         else
1157                 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1158
1159         rxq_info->type_flags |=
1160                 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1161                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1162
1163         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1164             (sfc_dp_rx_offload_capa(sa->priv.dp_rx) &
1165              DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0)
1166                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1167
1168         if (offloads & DEV_RX_OFFLOAD_RSS_HASH)
1169                 rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH;
1170
1171         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1172                           evq_entries, socket_id, &evq);
1173         if (rc != 0)
1174                 goto fail_ev_qinit;
1175
1176         rxq = &sa->rxq_ctrl[sw_index];
1177         rxq->evq = evq;
1178         rxq->hw_index = sw_index;
1179         /*
1180          * If Rx refill threshold is specified (its value is non zero) in
1181          * Rx configuration, use specified value. Otherwise use 1/8 of
1182          * the Rx descriptors number as the default. It allows to keep
1183          * Rx ring full-enough and does not refill too aggressive if
1184          * packet rate is high.
1185          *
1186          * Since PMD refills in bulks waiting for full bulk may be
1187          * refilled (basically round down), it is better to round up
1188          * here to mitigate it a bit.
1189          */
1190         rx_free_thresh = (rx_conf->rx_free_thresh != 0) ?
1191                 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8);
1192         /* Rx refill threshold cannot be smaller than refill bulk */
1193         rxq_info->refill_threshold =
1194                 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK);
1195         rxq_info->refill_mb_pool = mb_pool;
1196
1197         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 &&
1198             (offloads & DEV_RX_OFFLOAD_RSS_HASH))
1199                 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH;
1200         else
1201                 rxq_info->rxq_flags = 0;
1202
1203         rxq->buf_size = buf_size;
1204
1205         rc = sfc_dma_alloc(sa, "rxq", sw_index,
1206                            efx_rxq_size(sa->nic, rxq_info->entries),
1207                            socket_id, &rxq->mem);
1208         if (rc != 0)
1209                 goto fail_dma_alloc;
1210
1211         memset(&info, 0, sizeof(info));
1212         info.refill_mb_pool = rxq_info->refill_mb_pool;
1213         info.max_fill_level = rxq_max_fill_level;
1214         info.refill_threshold = rxq_info->refill_threshold;
1215         info.buf_size = buf_size;
1216         info.batch_max = encp->enc_rx_batch_max;
1217         info.prefix_size = encp->enc_rx_prefix_size;
1218         info.flags = rxq_info->rxq_flags;
1219         info.rxq_entries = rxq_info->entries;
1220         info.rxq_hw_ring = rxq->mem.esm_base;
1221         info.evq_hw_index = sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index);
1222         info.evq_entries = evq_entries;
1223         info.evq_hw_ring = evq->mem.esm_base;
1224         info.hw_index = rxq->hw_index;
1225         info.mem_bar = sa->mem_bar.esb_base;
1226         info.vi_window_shift = encp->enc_vi_window_shift;
1227         info.fcw_offset = sa->fcw_offset;
1228
1229         rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1230                                      &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1231                                      socket_id, &info, &rxq_info->dp);
1232         if (rc != 0)
1233                 goto fail_dp_rx_qcreate;
1234
1235         evq->dp_rxq = rxq_info->dp;
1236
1237         rxq_info->state = SFC_RXQ_INITIALIZED;
1238
1239         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1240
1241         return 0;
1242
1243 fail_dp_rx_qcreate:
1244         sfc_dma_free(sa, &rxq->mem);
1245
1246 fail_dma_alloc:
1247         sfc_ev_qfini(evq);
1248
1249 fail_ev_qinit:
1250         rxq_info->entries = 0;
1251
1252 fail_bad_conf:
1253 fail_size_up_rings:
1254         sfc_log_init(sa, "failed %d", rc);
1255         return rc;
1256 }
1257
1258 void
1259 sfc_rx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
1260 {
1261         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1262         sfc_ethdev_qid_t ethdev_qid;
1263         struct sfc_rxq_info *rxq_info;
1264         struct sfc_rxq *rxq;
1265
1266         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1267         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1268
1269         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1270                 sa->eth_dev->data->rx_queues[ethdev_qid] = NULL;
1271
1272         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1273
1274         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1275
1276         sa->priv.dp_rx->qdestroy(rxq_info->dp);
1277         rxq_info->dp = NULL;
1278
1279         rxq_info->state &= ~SFC_RXQ_INITIALIZED;
1280         rxq_info->entries = 0;
1281
1282         rxq = &sa->rxq_ctrl[sw_index];
1283
1284         sfc_dma_free(sa, &rxq->mem);
1285
1286         sfc_ev_qfini(rxq->evq);
1287         rxq->evq = NULL;
1288 }
1289
1290 /*
1291  * Mapping between RTE RSS hash functions and their EFX counterparts.
1292  */
1293 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1294         { ETH_RSS_NONFRAG_IPV4_TCP,
1295           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1296         { ETH_RSS_NONFRAG_IPV4_UDP,
1297           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1298         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1299           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1300         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1301           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1302         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1303           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1304           EFX_RX_HASH(IPV4, 2TUPLE) },
1305         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1306           ETH_RSS_IPV6_EX,
1307           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1308           EFX_RX_HASH(IPV6, 2TUPLE) }
1309 };
1310
1311 static efx_rx_hash_type_t
1312 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1313                             unsigned int *hash_type_flags_supported,
1314                             unsigned int nb_hash_type_flags_supported)
1315 {
1316         efx_rx_hash_type_t hash_type_masked = 0;
1317         unsigned int i, j;
1318
1319         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1320                 unsigned int class_tuple_lbn[] = {
1321                         EFX_RX_CLASS_IPV4_TCP_LBN,
1322                         EFX_RX_CLASS_IPV4_UDP_LBN,
1323                         EFX_RX_CLASS_IPV4_LBN,
1324                         EFX_RX_CLASS_IPV6_TCP_LBN,
1325                         EFX_RX_CLASS_IPV6_UDP_LBN,
1326                         EFX_RX_CLASS_IPV6_LBN
1327                 };
1328
1329                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1330                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1331                         unsigned int flag;
1332
1333                         tuple_mask <<= class_tuple_lbn[j];
1334                         flag = hash_type & tuple_mask;
1335
1336                         if (flag == hash_type_flags_supported[i])
1337                                 hash_type_masked |= flag;
1338                 }
1339         }
1340
1341         return hash_type_masked;
1342 }
1343
1344 int
1345 sfc_rx_hash_init(struct sfc_adapter *sa)
1346 {
1347         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1348         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1349         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1350         efx_rx_hash_alg_t alg;
1351         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1352         unsigned int nb_flags_supp;
1353         struct sfc_rss_hf_rte_to_efx *hf_map;
1354         struct sfc_rss_hf_rte_to_efx *entry;
1355         efx_rx_hash_type_t efx_hash_types;
1356         unsigned int i;
1357         int rc;
1358
1359         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1360                 alg = EFX_RX_HASHALG_TOEPLITZ;
1361         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1362                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1363         else
1364                 return EINVAL;
1365
1366         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1367                                          RTE_DIM(flags_supp), &nb_flags_supp);
1368         if (rc != 0)
1369                 return rc;
1370
1371         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1372                                    RTE_DIM(sfc_rss_hf_map),
1373                                    sizeof(*hf_map), 0, sa->socket_id);
1374         if (hf_map == NULL)
1375                 return ENOMEM;
1376
1377         entry = hf_map;
1378         efx_hash_types = 0;
1379         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1380                 efx_rx_hash_type_t ht;
1381
1382                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1383                                                  flags_supp, nb_flags_supp);
1384                 if (ht != 0) {
1385                         entry->rte = sfc_rss_hf_map[i].rte;
1386                         entry->efx = ht;
1387                         efx_hash_types |= ht;
1388                         ++entry;
1389                 }
1390         }
1391
1392         rss->hash_alg = alg;
1393         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1394         rss->hf_map = hf_map;
1395         rss->hash_types = efx_hash_types;
1396
1397         return 0;
1398 }
1399
1400 void
1401 sfc_rx_hash_fini(struct sfc_adapter *sa)
1402 {
1403         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1404
1405         rte_free(rss->hf_map);
1406 }
1407
1408 int
1409 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1410                      efx_rx_hash_type_t *efx)
1411 {
1412         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1413         efx_rx_hash_type_t hash_types = 0;
1414         unsigned int i;
1415
1416         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1417                 uint64_t rte_mask = rss->hf_map[i].rte;
1418
1419                 if ((rte & rte_mask) != 0) {
1420                         rte &= ~rte_mask;
1421                         hash_types |= rss->hf_map[i].efx;
1422                 }
1423         }
1424
1425         if (rte != 0) {
1426                 sfc_err(sa, "unsupported hash functions requested");
1427                 return EINVAL;
1428         }
1429
1430         *efx = hash_types;
1431
1432         return 0;
1433 }
1434
1435 uint64_t
1436 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx)
1437 {
1438         uint64_t rte = 0;
1439         unsigned int i;
1440
1441         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1442                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1443
1444                 if ((efx & hash_type) == hash_type)
1445                         rte |= rss->hf_map[i].rte;
1446         }
1447
1448         return rte;
1449 }
1450
1451 static int
1452 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1453                             struct rte_eth_rss_conf *conf)
1454 {
1455         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1456         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1457         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types);
1458         int rc;
1459
1460         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1461                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1462                     conf->rss_key != NULL)
1463                         return EINVAL;
1464         }
1465
1466         if (conf->rss_hf != 0) {
1467                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1468                 if (rc != 0)
1469                         return rc;
1470         }
1471
1472         if (conf->rss_key != NULL) {
1473                 if (conf->rss_key_len != sizeof(rss->key)) {
1474                         sfc_err(sa, "RSS key size is wrong (should be %zu)",
1475                                 sizeof(rss->key));
1476                         return EINVAL;
1477                 }
1478                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1479         }
1480
1481         rss->hash_types = efx_hash_types;
1482
1483         return 0;
1484 }
1485
1486 static int
1487 sfc_rx_rss_config(struct sfc_adapter *sa)
1488 {
1489         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1490         int rc = 0;
1491
1492         if (rss->channels > 0) {
1493                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1494                                            rss->hash_alg, rss->hash_types,
1495                                            B_TRUE);
1496                 if (rc != 0)
1497                         goto finish;
1498
1499                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1500                                           rss->key, sizeof(rss->key));
1501                 if (rc != 0)
1502                         goto finish;
1503
1504                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1505                                           rss->tbl, RTE_DIM(rss->tbl));
1506         }
1507
1508 finish:
1509         return rc;
1510 }
1511
1512 struct sfc_rxq_info *
1513 sfc_rxq_info_by_ethdev_qid(struct sfc_adapter_shared *sas,
1514                            sfc_ethdev_qid_t ethdev_qid)
1515 {
1516         sfc_sw_index_t sw_index;
1517
1518         SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1519         SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1520
1521         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1522         return &sas->rxq_info[sw_index];
1523 }
1524
1525 struct sfc_rxq *
1526 sfc_rxq_ctrl_by_ethdev_qid(struct sfc_adapter *sa, sfc_ethdev_qid_t ethdev_qid)
1527 {
1528         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1529         sfc_sw_index_t sw_index;
1530
1531         SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1532         SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1533
1534         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1535         return &sa->rxq_ctrl[sw_index];
1536 }
1537
1538 int
1539 sfc_rx_start(struct sfc_adapter *sa)
1540 {
1541         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1542         sfc_sw_index_t sw_index;
1543         int rc;
1544
1545         sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1546                      sas->rxq_count);
1547
1548         rc = efx_rx_init(sa->nic);
1549         if (rc != 0)
1550                 goto fail_rx_init;
1551
1552         rc = sfc_rx_rss_config(sa);
1553         if (rc != 0)
1554                 goto fail_rss_config;
1555
1556         for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) {
1557                 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED &&
1558                     (!sas->rxq_info[sw_index].deferred_start ||
1559                      sas->rxq_info[sw_index].deferred_started)) {
1560                         rc = sfc_rx_qstart(sa, sw_index);
1561                         if (rc != 0)
1562                                 goto fail_rx_qstart;
1563                 }
1564         }
1565
1566         return 0;
1567
1568 fail_rx_qstart:
1569         while (sw_index-- > 0)
1570                 sfc_rx_qstop(sa, sw_index);
1571
1572 fail_rss_config:
1573         efx_rx_fini(sa->nic);
1574
1575 fail_rx_init:
1576         sfc_log_init(sa, "failed %d", rc);
1577         return rc;
1578 }
1579
1580 void
1581 sfc_rx_stop(struct sfc_adapter *sa)
1582 {
1583         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1584         sfc_sw_index_t sw_index;
1585
1586         sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1587                      sas->rxq_count);
1588
1589         sw_index = sas->rxq_count;
1590         while (sw_index-- > 0) {
1591                 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED)
1592                         sfc_rx_qstop(sa, sw_index);
1593         }
1594
1595         efx_rx_fini(sa->nic);
1596 }
1597
1598 int
1599 sfc_rx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1600                   unsigned int extra_efx_type_flags)
1601 {
1602         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1603         struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index];
1604         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1605         unsigned int max_entries;
1606
1607         max_entries = encp->enc_rxq_max_ndescs;
1608         SFC_ASSERT(rte_is_power_of_2(max_entries));
1609
1610         rxq_info->max_entries = max_entries;
1611         rxq_info->type_flags = extra_efx_type_flags;
1612
1613         return 0;
1614 }
1615
1616 static int
1617 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1618 {
1619         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1620         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1621                                       sfc_rx_get_queue_offload_caps(sa);
1622         struct sfc_rss *rss = &sas->rss;
1623         int rc = 0;
1624
1625         switch (rxmode->mq_mode) {
1626         case ETH_MQ_RX_NONE:
1627                 /* No special checks are required */
1628                 break;
1629         case ETH_MQ_RX_RSS:
1630                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1631                         sfc_err(sa, "RSS is not available");
1632                         rc = EINVAL;
1633                 }
1634                 break;
1635         default:
1636                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1637                         rxmode->mq_mode);
1638                 rc = EINVAL;
1639         }
1640
1641         /*
1642          * Requested offloads are validated against supported by ethdev,
1643          * so unsupported offloads cannot be added as the result of
1644          * below check.
1645          */
1646         if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1647             (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1648                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1649                 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1650         }
1651
1652         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1653             (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1654                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1655                 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1656         }
1657
1658         return rc;
1659 }
1660
1661 /**
1662  * Destroy excess queues that are no longer needed after reconfiguration
1663  * or complete close.
1664  */
1665 static void
1666 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1667 {
1668         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1669         sfc_sw_index_t sw_index;
1670         sfc_ethdev_qid_t ethdev_qid;
1671
1672         SFC_ASSERT(nb_rx_queues <= sas->ethdev_rxq_count);
1673
1674         /*
1675          * Finalize only ethdev queues since other ones are finalized only
1676          * on device close and they may require additional deinitializaton.
1677          */
1678         ethdev_qid = sas->ethdev_rxq_count;
1679         while (--ethdev_qid >= (int)nb_rx_queues) {
1680                 struct sfc_rxq_info *rxq_info;
1681
1682                 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, ethdev_qid);
1683                 if (rxq_info->state & SFC_RXQ_INITIALIZED) {
1684                         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1685                                                                 ethdev_qid);
1686                         sfc_rx_qfini(sa, sw_index);
1687                 }
1688
1689         }
1690
1691         sas->ethdev_rxq_count = nb_rx_queues;
1692 }
1693
1694 /**
1695  * Initialize Rx subsystem.
1696  *
1697  * Called at device (re)configuration stage when number of receive queues is
1698  * specified together with other device level receive configuration.
1699  *
1700  * It should be used to allocate NUMA-unaware resources.
1701  */
1702 int
1703 sfc_rx_configure(struct sfc_adapter *sa)
1704 {
1705         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1706         struct sfc_rss *rss = &sas->rss;
1707         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1708         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1709         const unsigned int nb_rsrv_rx_queues = sfc_nb_reserved_rxq(sas);
1710         const unsigned int nb_rxq_total = nb_rx_queues + nb_rsrv_rx_queues;
1711         bool reconfigure;
1712         int rc;
1713
1714         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1715                      nb_rx_queues, sas->ethdev_rxq_count);
1716
1717         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1718         if (rc != 0)
1719                 goto fail_check_mode;
1720
1721         if (nb_rxq_total == sas->rxq_count) {
1722                 reconfigure = true;
1723                 goto configure_rss;
1724         }
1725
1726         if (sas->rxq_info == NULL) {
1727                 reconfigure = false;
1728                 rc = ENOMEM;
1729                 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rxq_total,
1730                                                   sizeof(sas->rxq_info[0]), 0,
1731                                                   sa->socket_id);
1732                 if (sas->rxq_info == NULL)
1733                         goto fail_rxqs_alloc;
1734
1735                 /*
1736                  * Allocate primary process only RxQ control from heap
1737                  * since it should not be shared.
1738                  */
1739                 rc = ENOMEM;
1740                 sa->rxq_ctrl = calloc(nb_rxq_total, sizeof(sa->rxq_ctrl[0]));
1741                 if (sa->rxq_ctrl == NULL)
1742                         goto fail_rxqs_ctrl_alloc;
1743         } else {
1744                 struct sfc_rxq_info *new_rxq_info;
1745                 struct sfc_rxq *new_rxq_ctrl;
1746
1747                 reconfigure = true;
1748
1749                 /* Do not ununitialize reserved queues */
1750                 if (nb_rx_queues < sas->ethdev_rxq_count)
1751                         sfc_rx_fini_queues(sa, nb_rx_queues);
1752
1753                 rc = ENOMEM;
1754                 new_rxq_info =
1755                         rte_realloc(sas->rxq_info,
1756                                     nb_rxq_total * sizeof(sas->rxq_info[0]), 0);
1757                 if (new_rxq_info == NULL && nb_rxq_total > 0)
1758                         goto fail_rxqs_realloc;
1759
1760                 rc = ENOMEM;
1761                 new_rxq_ctrl = realloc(sa->rxq_ctrl,
1762                                        nb_rxq_total * sizeof(sa->rxq_ctrl[0]));
1763                 if (new_rxq_ctrl == NULL && nb_rxq_total > 0)
1764                         goto fail_rxqs_ctrl_realloc;
1765
1766                 sas->rxq_info = new_rxq_info;
1767                 sa->rxq_ctrl = new_rxq_ctrl;
1768                 if (nb_rxq_total > sas->rxq_count) {
1769                         unsigned int rxq_count = sas->rxq_count;
1770
1771                         memset(&sas->rxq_info[rxq_count], 0,
1772                                (nb_rxq_total - rxq_count) *
1773                                sizeof(sas->rxq_info[0]));
1774                         memset(&sa->rxq_ctrl[rxq_count], 0,
1775                                (nb_rxq_total - rxq_count) *
1776                                sizeof(sa->rxq_ctrl[0]));
1777                 }
1778         }
1779
1780         while (sas->ethdev_rxq_count < nb_rx_queues) {
1781                 sfc_sw_index_t sw_index;
1782
1783                 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1784                                                         sas->ethdev_rxq_count);
1785                 rc = sfc_rx_qinit_info(sa, sw_index, 0);
1786                 if (rc != 0)
1787                         goto fail_rx_qinit_info;
1788
1789                 sas->ethdev_rxq_count++;
1790         }
1791
1792         sas->rxq_count = sas->ethdev_rxq_count + nb_rsrv_rx_queues;
1793
1794         if (!reconfigure) {
1795                 rc = sfc_mae_counter_rxq_init(sa);
1796                 if (rc != 0)
1797                         goto fail_count_rxq_init;
1798         }
1799
1800 configure_rss:
1801         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1802                          MIN(sas->ethdev_rxq_count, EFX_MAXRSS) : 0;
1803
1804         if (rss->channels > 0) {
1805                 struct rte_eth_rss_conf *adv_conf_rss;
1806                 sfc_sw_index_t sw_index;
1807
1808                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1809                         rss->tbl[sw_index] = sw_index % rss->channels;
1810
1811                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1812                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1813                 if (rc != 0)
1814                         goto fail_rx_process_adv_conf_rss;
1815         }
1816
1817         return 0;
1818
1819 fail_rx_process_adv_conf_rss:
1820         if (!reconfigure)
1821                 sfc_mae_counter_rxq_fini(sa);
1822
1823 fail_count_rxq_init:
1824 fail_rx_qinit_info:
1825 fail_rxqs_ctrl_realloc:
1826 fail_rxqs_realloc:
1827 fail_rxqs_ctrl_alloc:
1828 fail_rxqs_alloc:
1829         sfc_rx_close(sa);
1830
1831 fail_check_mode:
1832         sfc_log_init(sa, "failed %d", rc);
1833         return rc;
1834 }
1835
1836 /**
1837  * Shutdown Rx subsystem.
1838  *
1839  * Called at device close stage, for example, before device shutdown.
1840  */
1841 void
1842 sfc_rx_close(struct sfc_adapter *sa)
1843 {
1844         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1845
1846         sfc_rx_fini_queues(sa, 0);
1847         sfc_mae_counter_rxq_fini(sa);
1848
1849         rss->channels = 0;
1850
1851         free(sa->rxq_ctrl);
1852         sa->rxq_ctrl = NULL;
1853
1854         rte_free(sfc_sa2shared(sa)->rxq_info);
1855         sfc_sa2shared(sa)->rxq_info = NULL;
1856 }