1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 #include <rte_mempool.h>
15 #include "sfc_debug.h"
19 #include "sfc_kvargs.h"
20 #include "sfc_tweak.h"
23 * Maximum number of Rx queue flush attempt in the case of failure or
26 #define SFC_RX_QFLUSH_ATTEMPTS (3)
29 * Time to wait between event queue polling attempts when waiting for Rx
30 * queue flush done or failed events.
32 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1)
35 * Maximum number of event queue polling attempts when waiting for Rx queue
36 * flush done or failed events. It defines Rx queue flush attempt timeout
37 * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000)
42 sfc_rx_qflush_done(struct sfc_rxq *rxq)
44 rxq->state |= SFC_RXQ_FLUSHED;
45 rxq->state &= ~SFC_RXQ_FLUSHING;
49 sfc_rx_qflush_failed(struct sfc_rxq *rxq)
51 rxq->state |= SFC_RXQ_FLUSH_FAILED;
52 rxq->state &= ~SFC_RXQ_FLUSHING;
56 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
58 unsigned int free_space;
60 void *objs[SFC_RX_REFILL_BULK];
61 efsys_dma_addr_t addr[RTE_DIM(objs)];
62 unsigned int added = rxq->added;
65 struct sfc_efx_rx_sw_desc *rxd;
67 uint16_t port_id = rxq->dp.dpq.port_id;
69 free_space = rxq->max_fill_level - (added - rxq->completed);
71 if (free_space < rxq->refill_threshold)
74 bulks = free_space / RTE_DIM(objs);
75 /* refill_threshold guarantees that bulks is positive */
76 SFC_ASSERT(bulks > 0);
78 id = added & rxq->ptr_mask;
80 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
81 RTE_DIM(objs)) < 0)) {
83 * It is hardly a safe way to increment counter
84 * from different contexts, but all PMDs do it.
86 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
88 /* Return if we have posted nothing yet */
89 if (added == rxq->added)
95 for (i = 0; i < RTE_DIM(objs);
96 ++i, id = (id + 1) & rxq->ptr_mask) {
99 MBUF_RAW_ALLOC_CHECK(m);
101 rxd = &rxq->sw_desc[id];
104 m->data_off = RTE_PKTMBUF_HEADROOM;
107 addr[i] = rte_pktmbuf_iova(m);
110 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
111 RTE_DIM(objs), rxq->completed, added);
112 added += RTE_DIM(objs);
113 } while (--bulks > 0);
115 SFC_ASSERT(added != rxq->added);
117 efx_rx_qpush(rxq->common, added, &rxq->pushed);
121 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
123 uint64_t mbuf_flags = 0;
125 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
126 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
127 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
130 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
133 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
134 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
135 PKT_RX_IP_CKSUM_UNKNOWN);
139 switch ((desc_flags &
140 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
141 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
142 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
143 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
147 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
150 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
151 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
152 PKT_RX_L4_CKSUM_UNKNOWN);
160 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
162 return RTE_PTYPE_L2_ETHER |
163 ((desc_flags & EFX_PKT_IPV4) ?
164 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
165 ((desc_flags & EFX_PKT_IPV6) ?
166 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
167 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
168 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
171 static const uint32_t *
172 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
174 static const uint32_t ptypes[] = {
176 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
177 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
187 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
193 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
196 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
198 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
199 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
200 EFX_RX_HASHALG_TOEPLITZ,
203 m->ol_flags |= PKT_RX_RSS_HASH;
208 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
210 struct sfc_dp_rxq *dp_rxq = rx_queue;
211 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
212 unsigned int completed;
213 unsigned int prefix_size = rxq->prefix_size;
214 unsigned int done_pkts = 0;
215 boolean_t discard_next = B_FALSE;
216 struct rte_mbuf *scatter_pkt = NULL;
218 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
221 sfc_ev_qpoll(rxq->evq);
223 completed = rxq->completed;
224 while (completed != rxq->pending && done_pkts < nb_pkts) {
226 struct sfc_efx_rx_sw_desc *rxd;
228 unsigned int seg_len;
229 unsigned int desc_flags;
231 id = completed++ & rxq->ptr_mask;
232 rxd = &rxq->sw_desc[id];
234 desc_flags = rxd->flags;
239 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
242 if (desc_flags & EFX_PKT_PREFIX_LEN) {
246 rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
247 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
251 seg_len = rxd->size - prefix_size;
254 rte_pktmbuf_data_len(m) = seg_len;
255 rte_pktmbuf_pkt_len(m) = seg_len;
257 if (scatter_pkt != NULL) {
258 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
259 rte_pktmbuf_free(scatter_pkt);
262 /* The packet to deliver */
266 if (desc_flags & EFX_PKT_CONT) {
267 /* The packet is scattered, more fragments to come */
269 /* Further fragments have no prefix */
274 /* Scattered packet is done */
276 /* The first fragment of the packet has prefix */
277 prefix_size = rxq->prefix_size;
280 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
282 sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
285 * Extract RSS hash from the packet prefix and
286 * set the corresponding field (if needed and possible)
288 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
290 m->data_off += prefix_size;
297 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
298 rte_mbuf_raw_free(m);
302 /* pending is only moved when entire packet is received */
303 SFC_ASSERT(scatter_pkt == NULL);
305 rxq->completed = completed;
307 sfc_efx_rx_qrefill(rxq);
312 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
314 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
316 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
318 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
321 sfc_ev_qpoll(rxq->evq);
323 return rxq->pending - rxq->completed;
326 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
328 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
330 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
332 if (unlikely(offset > rxq->ptr_mask))
336 * Poll EvQ to derive up-to-date 'rxq->pending' figure;
337 * it is required for the queue to be running, but the
338 * check is omitted because API design assumes that it
339 * is the duty of the caller to satisfy all conditions
341 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
342 SFC_EFX_RXQ_FLAG_RUNNING);
343 sfc_ev_qpoll(rxq->evq);
346 * There is a handful of reserved entries in the ring,
347 * but an explicit check whether the offset points to
348 * a reserved entry is neglected since the two checks
349 * below rely on the figures which take the HW limits
350 * into account and thus if an entry is reserved, the
351 * checks will fail and UNAVAIL code will be returned
354 if (offset < (rxq->pending - rxq->completed))
355 return RTE_ETH_RX_DESC_DONE;
357 if (offset < (rxq->added - rxq->completed))
358 return RTE_ETH_RX_DESC_AVAIL;
360 return RTE_ETH_RX_DESC_UNAVAIL;
364 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
366 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
367 struct rte_eth_dev *eth_dev;
368 struct sfc_adapter *sa;
371 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
372 eth_dev = &rte_eth_devices[dpq->port_id];
374 sa = eth_dev->data->dev_private;
376 SFC_ASSERT(dpq->queue_id < sa->rxq_count);
377 rxq = sa->rxq_info[dpq->queue_id].rxq;
379 SFC_ASSERT(rxq != NULL);
383 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
385 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
386 __rte_unused struct rte_mempool *mb_pool,
387 unsigned int *rxq_entries,
388 unsigned int *evq_entries,
389 unsigned int *rxq_max_fill_level)
391 *rxq_entries = nb_rx_desc;
392 *evq_entries = nb_rx_desc;
393 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
397 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
399 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
400 const struct rte_pci_addr *pci_addr, int socket_id,
401 const struct sfc_dp_rx_qcreate_info *info,
402 struct sfc_dp_rxq **dp_rxqp)
404 struct sfc_efx_rxq *rxq;
408 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
409 RTE_CACHE_LINE_SIZE, socket_id);
413 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
416 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
418 sizeof(*rxq->sw_desc),
419 RTE_CACHE_LINE_SIZE, socket_id);
420 if (rxq->sw_desc == NULL)
421 goto fail_desc_alloc;
423 /* efx datapath is bound to efx control path */
424 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
425 if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
426 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
427 rxq->ptr_mask = info->rxq_entries - 1;
428 rxq->batch_max = info->batch_max;
429 rxq->prefix_size = info->prefix_size;
430 rxq->max_fill_level = info->max_fill_level;
431 rxq->refill_threshold = info->refill_threshold;
432 rxq->buf_size = info->buf_size;
433 rxq->refill_mb_pool = info->refill_mb_pool;
445 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
447 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
449 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
451 rte_free(rxq->sw_desc);
455 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
457 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
458 __rte_unused unsigned int evq_read_ptr)
460 /* libefx-based datapath is specific to libefx-based PMD */
461 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
462 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
464 rxq->common = crxq->common;
466 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
468 sfc_efx_rx_qrefill(rxq);
470 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
475 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
477 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
478 __rte_unused unsigned int *evq_read_ptr)
480 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
482 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
484 /* libefx-based datapath is bound to libefx-based PMD and uses
485 * event queue structure directly. So, there is no necessity to
486 * return EvQ read pointer.
490 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
492 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
494 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
496 struct sfc_efx_rx_sw_desc *rxd;
498 for (i = rxq->completed; i != rxq->added; ++i) {
499 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
500 rte_mbuf_raw_free(rxd->mbuf);
502 /* Packed stream relies on 0 in inactive SW desc.
503 * Rx queue stop is not performance critical, so
504 * there is no harm to do it always.
510 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
513 struct sfc_dp_rx sfc_efx_rx = {
515 .name = SFC_KVARG_DATAPATH_EFX,
519 .features = SFC_DP_RX_FEAT_SCATTER |
520 SFC_DP_RX_FEAT_CHECKSUM,
521 .qsize_up_rings = sfc_efx_rx_qsize_up_rings,
522 .qcreate = sfc_efx_rx_qcreate,
523 .qdestroy = sfc_efx_rx_qdestroy,
524 .qstart = sfc_efx_rx_qstart,
525 .qstop = sfc_efx_rx_qstop,
526 .qpurge = sfc_efx_rx_qpurge,
527 .supported_ptypes_get = sfc_efx_supported_ptypes_get,
528 .qdesc_npending = sfc_efx_rx_qdesc_npending,
529 .qdesc_status = sfc_efx_rx_qdesc_status,
530 .pkt_burst = sfc_efx_recv_pkts,
534 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
537 unsigned int retry_count;
538 unsigned int wait_count;
541 rxq = sa->rxq_info[sw_index].rxq;
542 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
545 * Retry Rx queue flushing in the case of flush failed or
546 * timeout. In the worst case it can delay for 6 seconds.
548 for (retry_count = 0;
549 ((rxq->state & SFC_RXQ_FLUSHED) == 0) &&
550 (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
552 rc = efx_rx_qflush(rxq->common);
554 rxq->state |= (rc == EALREADY) ?
555 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
558 rxq->state &= ~SFC_RXQ_FLUSH_FAILED;
559 rxq->state |= SFC_RXQ_FLUSHING;
562 * Wait for Rx queue flush done or failed event at least
563 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
564 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
565 * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
569 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
570 sfc_ev_qpoll(rxq->evq);
571 } while ((rxq->state & SFC_RXQ_FLUSHING) &&
572 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
574 if (rxq->state & SFC_RXQ_FLUSHING)
575 sfc_err(sa, "RxQ %u flush timed out", sw_index);
577 if (rxq->state & SFC_RXQ_FLUSH_FAILED)
578 sfc_err(sa, "RxQ %u flush failed", sw_index);
580 if (rxq->state & SFC_RXQ_FLUSHED)
581 sfc_notice(sa, "RxQ %u flushed", sw_index);
584 sa->priv.dp_rx->qpurge(rxq->dp);
588 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
590 struct sfc_rss *rss = &sa->rss;
591 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
592 struct sfc_port *port = &sa->port;
596 * If promiscuous or all-multicast mode has been requested, setting
597 * filter for the default Rx queue might fail, in particular, while
598 * running over PCI function which is not a member of corresponding
599 * privilege groups; if this occurs, few iterations will be made to
600 * repeat this step without promiscuous and all-multicast flags set
603 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
606 else if (rc != EOPNOTSUPP)
610 sfc_warn(sa, "promiscuous mode has been requested, "
611 "but the HW rejects it");
612 sfc_warn(sa, "promiscuous mode will be disabled");
614 port->promisc = B_FALSE;
615 rc = sfc_set_rx_mode(sa);
622 if (port->allmulti) {
623 sfc_warn(sa, "all-multicast mode has been requested, "
624 "but the HW rejects it");
625 sfc_warn(sa, "all-multicast mode will be disabled");
627 port->allmulti = B_FALSE;
628 rc = sfc_set_rx_mode(sa);
639 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
641 struct sfc_port *port = &sa->port;
642 struct sfc_rxq_info *rxq_info;
647 sfc_log_init(sa, "sw_index=%u", sw_index);
649 SFC_ASSERT(sw_index < sa->rxq_count);
651 rxq_info = &sa->rxq_info[sw_index];
653 SFC_ASSERT(rxq != NULL);
654 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
658 rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
662 switch (rxq_info->type) {
663 case EFX_RXQ_TYPE_DEFAULT:
664 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
665 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
666 rxq_info->type_flags, evq->common, &rxq->common);
668 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
669 struct rte_mempool *mp = rxq_info->refill_mb_pool;
670 struct rte_mempool_info mp_info;
672 rc = rte_mempool_ops_get_info(mp, &mp_info);
674 /* Positive errno is used in the driver */
676 goto fail_mp_get_info;
678 if (mp_info.contig_block_size <= 0) {
680 goto fail_bad_contig_block_size;
682 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
683 mp_info.contig_block_size, rxq->buf_size,
684 mp->header_size + mp->elt_size + mp->trailer_size,
685 sa->rxd_wait_timeout_ns,
686 &rxq->mem, rxq_info->entries, rxq_info->type_flags,
687 evq->common, &rxq->common);
694 goto fail_rx_qcreate;
696 efx_rx_qenable(rxq->common);
698 rc = sa->priv.dp_rx->qstart(rxq->dp, evq->read_ptr);
702 rxq->state |= SFC_RXQ_STARTED;
704 if ((sw_index == 0) && !port->isolated) {
705 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
707 goto fail_mac_filter_default_rxq_set;
710 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
711 sa->eth_dev->data->rx_queue_state[sw_index] =
712 RTE_ETH_QUEUE_STATE_STARTED;
716 fail_mac_filter_default_rxq_set:
717 sa->priv.dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
720 sfc_rx_qflush(sa, sw_index);
723 fail_bad_contig_block_size:
732 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
734 struct sfc_rxq_info *rxq_info;
737 sfc_log_init(sa, "sw_index=%u", sw_index);
739 SFC_ASSERT(sw_index < sa->rxq_count);
741 rxq_info = &sa->rxq_info[sw_index];
744 if (rxq == NULL || rxq->state == SFC_RXQ_INITIALIZED)
746 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
748 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
749 sa->eth_dev->data->rx_queue_state[sw_index] =
750 RTE_ETH_QUEUE_STATE_STOPPED;
752 sa->priv.dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
755 efx_mac_filter_default_rxq_clear(sa->nic);
757 sfc_rx_qflush(sa, sw_index);
759 rxq->state = SFC_RXQ_INITIALIZED;
761 efx_rx_qdestroy(rxq->common);
763 sfc_ev_qstop(rxq->evq);
767 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
769 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
772 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
774 if (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_CHECKSUM) {
775 caps |= DEV_RX_OFFLOAD_IPV4_CKSUM;
776 caps |= DEV_RX_OFFLOAD_UDP_CKSUM;
777 caps |= DEV_RX_OFFLOAD_TCP_CKSUM;
780 if (encp->enc_tunnel_encapsulations_supported &&
781 (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
782 caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
788 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
792 if (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_SCATTER)
793 caps |= DEV_RX_OFFLOAD_SCATTER;
799 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
800 const struct rte_eth_rxconf *rx_conf,
801 __rte_unused uint64_t offloads)
805 if (rx_conf->rx_thresh.pthresh != 0 ||
806 rx_conf->rx_thresh.hthresh != 0 ||
807 rx_conf->rx_thresh.wthresh != 0) {
809 "RxQ prefetch/host/writeback thresholds are not supported");
812 if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
814 "RxQ free threshold too large: %u vs maximum %u",
815 rx_conf->rx_free_thresh, rxq_max_fill_level);
819 if (rx_conf->rx_drop_en == 0) {
820 sfc_err(sa, "RxQ drop disable is not supported");
828 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
833 /* The mbuf object itself is always cache line aligned */
834 order = rte_bsf32(RTE_CACHE_LINE_SIZE);
836 /* Data offset from mbuf object start */
837 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
838 RTE_PKTMBUF_HEADROOM;
840 order = MIN(order, rte_bsf32(data_off));
846 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
848 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
849 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
850 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
852 unsigned int buf_aligned;
853 unsigned int start_alignment;
854 unsigned int end_padding_alignment;
856 /* Below it is assumed that both alignments are power of 2 */
857 SFC_ASSERT(rte_is_power_of_2(nic_align_start));
858 SFC_ASSERT(rte_is_power_of_2(nic_align_end));
861 * mbuf is always cache line aligned, double-check
862 * that it meets rx buffer start alignment requirements.
865 /* Start from mbuf pool data room size */
866 buf_size = rte_pktmbuf_data_room_size(mb_pool);
868 /* Remove headroom */
869 if (buf_size <= RTE_PKTMBUF_HEADROOM) {
871 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
872 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
875 buf_size -= RTE_PKTMBUF_HEADROOM;
877 /* Calculate guaranteed data start alignment */
878 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
880 /* Reserve space for start alignment */
881 if (buf_aligned < nic_align_start) {
882 start_alignment = nic_align_start - buf_aligned;
883 if (buf_size <= start_alignment) {
885 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
887 rte_pktmbuf_data_room_size(mb_pool),
888 RTE_PKTMBUF_HEADROOM, start_alignment);
891 buf_aligned = nic_align_start;
892 buf_size -= start_alignment;
897 /* Make sure that end padding does not write beyond the buffer */
898 if (buf_aligned < nic_align_end) {
900 * Estimate space which can be lost. If guarnteed buffer
901 * size is odd, lost space is (nic_align_end - 1). More
902 * accurate formula is below.
904 end_padding_alignment = nic_align_end -
905 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
906 if (buf_size <= end_padding_alignment) {
908 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
910 rte_pktmbuf_data_room_size(mb_pool),
911 RTE_PKTMBUF_HEADROOM, start_alignment,
912 end_padding_alignment);
915 buf_size -= end_padding_alignment;
918 * Start is aligned the same or better than end,
921 buf_size = P2ALIGN(buf_size, nic_align_end);
928 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
929 uint16_t nb_rx_desc, unsigned int socket_id,
930 const struct rte_eth_rxconf *rx_conf,
931 struct rte_mempool *mb_pool)
933 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
934 struct sfc_rss *rss = &sa->rss;
936 unsigned int rxq_entries;
937 unsigned int evq_entries;
938 unsigned int rxq_max_fill_level;
941 struct sfc_rxq_info *rxq_info;
944 struct sfc_dp_rx_qcreate_info info;
946 rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, mb_pool, &rxq_entries,
947 &evq_entries, &rxq_max_fill_level);
949 goto fail_size_up_rings;
950 SFC_ASSERT(rxq_entries >= EFX_RXQ_MINNDESCS);
951 SFC_ASSERT(rxq_entries <= EFX_RXQ_MAXNDESCS);
952 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
954 offloads = rx_conf->offloads |
955 sa->eth_dev->data->dev_conf.rxmode.offloads;
956 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
960 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
962 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
968 if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) &&
969 (~offloads & DEV_RX_OFFLOAD_SCATTER)) {
970 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool "
971 "object size is too small", sw_index);
972 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
973 "PDU size %u plus Rx prefix %u bytes",
974 sw_index, buf_size, (unsigned int)sa->port.pdu,
975 encp->enc_rx_prefix_size);
980 SFC_ASSERT(sw_index < sa->rxq_count);
981 rxq_info = &sa->rxq_info[sw_index];
983 SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
984 rxq_info->entries = rxq_entries;
986 if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
987 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
989 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
991 rxq_info->type_flags =
992 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
993 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
995 if ((encp->enc_tunnel_encapsulations_supported != 0) &&
996 (sa->priv.dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
997 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
999 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1000 evq_entries, socket_id, &evq);
1005 rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE,
1008 goto fail_rxq_alloc;
1010 rxq_info->rxq = rxq;
1013 rxq->hw_index = sw_index;
1014 rxq_info->refill_threshold =
1015 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK);
1016 rxq_info->refill_mb_pool = mb_pool;
1017 rxq->buf_size = buf_size;
1019 rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries),
1020 socket_id, &rxq->mem);
1022 goto fail_dma_alloc;
1024 memset(&info, 0, sizeof(info));
1025 info.refill_mb_pool = rxq_info->refill_mb_pool;
1026 info.max_fill_level = rxq_max_fill_level;
1027 info.refill_threshold = rxq_info->refill_threshold;
1028 info.buf_size = buf_size;
1029 info.batch_max = encp->enc_rx_batch_max;
1030 info.prefix_size = encp->enc_rx_prefix_size;
1032 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0)
1033 info.flags |= SFC_RXQ_FLAG_RSS_HASH;
1035 info.rxq_entries = rxq_info->entries;
1036 info.rxq_hw_ring = rxq->mem.esm_base;
1037 info.evq_entries = evq_entries;
1038 info.evq_hw_ring = evq->mem.esm_base;
1039 info.hw_index = rxq->hw_index;
1040 info.mem_bar = sa->mem_bar.esb_base;
1041 info.vi_window_shift = encp->enc_vi_window_shift;
1043 rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1044 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1045 socket_id, &info, &rxq->dp);
1047 goto fail_dp_rx_qcreate;
1049 evq->dp_rxq = rxq->dp;
1051 rxq->state = SFC_RXQ_INITIALIZED;
1053 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1058 sfc_dma_free(sa, &rxq->mem);
1061 rxq_info->rxq = NULL;
1068 rxq_info->entries = 0;
1072 sfc_log_init(sa, "failed %d", rc);
1077 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
1079 struct sfc_rxq_info *rxq_info;
1080 struct sfc_rxq *rxq;
1082 SFC_ASSERT(sw_index < sa->rxq_count);
1083 sa->eth_dev->data->rx_queues[sw_index] = NULL;
1085 rxq_info = &sa->rxq_info[sw_index];
1087 rxq = rxq_info->rxq;
1088 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
1090 sa->priv.dp_rx->qdestroy(rxq->dp);
1093 rxq_info->rxq = NULL;
1094 rxq_info->entries = 0;
1096 sfc_dma_free(sa, &rxq->mem);
1098 sfc_ev_qfini(rxq->evq);
1105 * Mapping between RTE RSS hash functions and their EFX counterparts.
1107 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1108 { ETH_RSS_NONFRAG_IPV4_TCP,
1109 EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1110 { ETH_RSS_NONFRAG_IPV4_UDP,
1111 EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1112 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1113 EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1114 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1115 EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1116 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1117 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1118 EFX_RX_HASH(IPV4, 2TUPLE) },
1119 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1121 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1122 EFX_RX_HASH(IPV6, 2TUPLE) }
1125 static efx_rx_hash_type_t
1126 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1127 unsigned int *hash_type_flags_supported,
1128 unsigned int nb_hash_type_flags_supported)
1130 efx_rx_hash_type_t hash_type_masked = 0;
1133 for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1134 unsigned int class_tuple_lbn[] = {
1135 EFX_RX_CLASS_IPV4_TCP_LBN,
1136 EFX_RX_CLASS_IPV4_UDP_LBN,
1137 EFX_RX_CLASS_IPV4_LBN,
1138 EFX_RX_CLASS_IPV6_TCP_LBN,
1139 EFX_RX_CLASS_IPV6_UDP_LBN,
1140 EFX_RX_CLASS_IPV6_LBN
1143 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1144 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1147 tuple_mask <<= class_tuple_lbn[j];
1148 flag = hash_type & tuple_mask;
1150 if (flag == hash_type_flags_supported[i])
1151 hash_type_masked |= flag;
1155 return hash_type_masked;
1159 sfc_rx_hash_init(struct sfc_adapter *sa)
1161 struct sfc_rss *rss = &sa->rss;
1162 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1163 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1164 efx_rx_hash_alg_t alg;
1165 unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1166 unsigned int nb_flags_supp;
1167 struct sfc_rss_hf_rte_to_efx *hf_map;
1168 struct sfc_rss_hf_rte_to_efx *entry;
1169 efx_rx_hash_type_t efx_hash_types;
1173 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1174 alg = EFX_RX_HASHALG_TOEPLITZ;
1175 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1176 alg = EFX_RX_HASHALG_PACKED_STREAM;
1180 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1181 RTE_DIM(flags_supp), &nb_flags_supp);
1185 hf_map = rte_calloc_socket("sfc-rss-hf-map",
1186 RTE_DIM(sfc_rss_hf_map),
1187 sizeof(*hf_map), 0, sa->socket_id);
1193 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1194 efx_rx_hash_type_t ht;
1196 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1197 flags_supp, nb_flags_supp);
1199 entry->rte = sfc_rss_hf_map[i].rte;
1201 efx_hash_types |= ht;
1206 rss->hash_alg = alg;
1207 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1208 rss->hf_map = hf_map;
1209 rss->hash_types = efx_hash_types;
1215 sfc_rx_hash_fini(struct sfc_adapter *sa)
1217 struct sfc_rss *rss = &sa->rss;
1219 rte_free(rss->hf_map);
1223 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1224 efx_rx_hash_type_t *efx)
1226 struct sfc_rss *rss = &sa->rss;
1227 efx_rx_hash_type_t hash_types = 0;
1230 for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1231 uint64_t rte_mask = rss->hf_map[i].rte;
1233 if ((rte & rte_mask) != 0) {
1235 hash_types |= rss->hf_map[i].efx;
1240 sfc_err(sa, "unsupported hash functions requested");
1250 sfc_rx_hf_efx_to_rte(struct sfc_adapter *sa, efx_rx_hash_type_t efx)
1252 struct sfc_rss *rss = &sa->rss;
1256 for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1257 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1259 if ((efx & hash_type) == hash_type)
1260 rte |= rss->hf_map[i].rte;
1267 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1268 struct rte_eth_rss_conf *conf)
1270 struct sfc_rss *rss = &sa->rss;
1271 efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1272 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(sa, efx_hash_types);
1275 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1276 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1277 conf->rss_key != NULL)
1281 if (conf->rss_hf != 0) {
1282 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1287 if (conf->rss_key != NULL) {
1288 if (conf->rss_key_len != sizeof(rss->key)) {
1289 sfc_err(sa, "RSS key size is wrong (should be %lu)",
1293 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1296 rss->hash_types = efx_hash_types;
1302 sfc_rx_rss_config(struct sfc_adapter *sa)
1304 struct sfc_rss *rss = &sa->rss;
1307 if (rss->channels > 0) {
1308 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1309 rss->hash_alg, rss->hash_types,
1314 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1315 rss->key, sizeof(rss->key));
1319 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1320 rss->tbl, RTE_DIM(rss->tbl));
1328 sfc_rx_start(struct sfc_adapter *sa)
1330 unsigned int sw_index;
1333 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1335 rc = efx_rx_init(sa->nic);
1339 rc = sfc_rx_rss_config(sa);
1341 goto fail_rss_config;
1343 for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1344 if (sa->rxq_info[sw_index].rxq != NULL &&
1345 (!sa->rxq_info[sw_index].deferred_start ||
1346 sa->rxq_info[sw_index].deferred_started)) {
1347 rc = sfc_rx_qstart(sa, sw_index);
1349 goto fail_rx_qstart;
1356 while (sw_index-- > 0)
1357 sfc_rx_qstop(sa, sw_index);
1360 efx_rx_fini(sa->nic);
1363 sfc_log_init(sa, "failed %d", rc);
1368 sfc_rx_stop(struct sfc_adapter *sa)
1370 unsigned int sw_index;
1372 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1374 sw_index = sa->rxq_count;
1375 while (sw_index-- > 0) {
1376 if (sa->rxq_info[sw_index].rxq != NULL)
1377 sfc_rx_qstop(sa, sw_index);
1380 efx_rx_fini(sa->nic);
1384 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1386 struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];
1387 unsigned int max_entries;
1389 max_entries = EFX_RXQ_MAXNDESCS;
1390 SFC_ASSERT(rte_is_power_of_2(max_entries));
1392 rxq_info->max_entries = max_entries;
1398 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1400 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1401 sfc_rx_get_queue_offload_caps(sa);
1402 struct sfc_rss *rss = &sa->rss;
1405 switch (rxmode->mq_mode) {
1406 case ETH_MQ_RX_NONE:
1407 /* No special checks are required */
1410 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1411 sfc_err(sa, "RSS is not available");
1416 sfc_err(sa, "Rx multi-queue mode %u not supported",
1422 * Requested offloads are validated against supported by ethdev,
1423 * so unsupported offloads cannot be added as the result of
1426 if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1427 (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1428 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1429 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1432 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1433 (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1434 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1435 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1442 * Destroy excess queues that are no longer needed after reconfiguration
1443 * or complete close.
1446 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1450 SFC_ASSERT(nb_rx_queues <= sa->rxq_count);
1452 sw_index = sa->rxq_count;
1453 while (--sw_index >= (int)nb_rx_queues) {
1454 if (sa->rxq_info[sw_index].rxq != NULL)
1455 sfc_rx_qfini(sa, sw_index);
1458 sa->rxq_count = nb_rx_queues;
1462 * Initialize Rx subsystem.
1464 * Called at device (re)configuration stage when number of receive queues is
1465 * specified together with other device level receive configuration.
1467 * It should be used to allocate NUMA-unaware resources.
1470 sfc_rx_configure(struct sfc_adapter *sa)
1472 struct sfc_rss *rss = &sa->rss;
1473 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1474 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1477 sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1478 nb_rx_queues, sa->rxq_count);
1480 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1482 goto fail_check_mode;
1484 if (nb_rx_queues == sa->rxq_count)
1487 if (sa->rxq_info == NULL) {
1489 sa->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1490 sizeof(sa->rxq_info[0]), 0,
1492 if (sa->rxq_info == NULL)
1493 goto fail_rxqs_alloc;
1495 struct sfc_rxq_info *new_rxq_info;
1497 if (nb_rx_queues < sa->rxq_count)
1498 sfc_rx_fini_queues(sa, nb_rx_queues);
1502 rte_realloc(sa->rxq_info,
1503 nb_rx_queues * sizeof(sa->rxq_info[0]), 0);
1504 if (new_rxq_info == NULL && nb_rx_queues > 0)
1505 goto fail_rxqs_realloc;
1507 sa->rxq_info = new_rxq_info;
1508 if (nb_rx_queues > sa->rxq_count)
1509 memset(&sa->rxq_info[sa->rxq_count], 0,
1510 (nb_rx_queues - sa->rxq_count) *
1511 sizeof(sa->rxq_info[0]));
1514 while (sa->rxq_count < nb_rx_queues) {
1515 rc = sfc_rx_qinit_info(sa, sa->rxq_count);
1517 goto fail_rx_qinit_info;
1523 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1524 MIN(sa->rxq_count, EFX_MAXRSS) : 0;
1526 if (rss->channels > 0) {
1527 struct rte_eth_rss_conf *adv_conf_rss;
1528 unsigned int sw_index;
1530 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1531 rss->tbl[sw_index] = sw_index % rss->channels;
1533 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1534 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1536 goto fail_rx_process_adv_conf_rss;
1541 fail_rx_process_adv_conf_rss:
1548 sfc_log_init(sa, "failed %d", rc);
1553 * Shutdown Rx subsystem.
1555 * Called at device close stage, for example, before device shutdown.
1558 sfc_rx_close(struct sfc_adapter *sa)
1560 struct sfc_rss *rss = &sa->rss;
1562 sfc_rx_fini_queues(sa, 0);
1566 rte_free(sa->rxq_info);
1567 sa->rxq_info = NULL;