drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2016-2019 Solarflare Communications Inc.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_kvargs.h"
  20 #include "sfc_tweak.h"
  21
  22 /*
  23  * Maximum number of Rx queue flush attempt in the case of failure or
  24  * flush timeout
  25  */
  26 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  27
  28 /*
  29  * Time to wait between event queue polling attempts when waiting for Rx
  30  * queue flush done or failed events.
  31  */
  32 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  33
  34 /*
  35  * Maximum number of event queue polling attempts when waiting for Rx queue
  36  * flush done or failed events. It defines Rx queue flush attempt timeout
  37  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  38  */
  39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  40
  41 void
  42 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
  43 {
  44         rxq_info->state |= SFC_RXQ_FLUSHED;
  45         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  46 }
  47
  48 void
  49 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
  50 {
  51         rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
  52         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  53 }
  54
  55 static int
  56 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq)
  57 {
  58         int rc = 0;
  59
  60         if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) {
  61                 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr);
  62                 if (rc == 0)
  63                         rxq->evq->read_ptr_primed = rxq->evq->read_ptr;
  64         }
  65         return rc;
  66 }
  67
  68 static void
  69 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  70 {
  71         unsigned int free_space;
  72         unsigned int bulks;
  73         void *objs[SFC_RX_REFILL_BULK];
  74         efsys_dma_addr_t addr[RTE_DIM(objs)];
  75         unsigned int added = rxq->added;
  76         unsigned int id;
  77         unsigned int i;
  78         struct sfc_efx_rx_sw_desc *rxd;
  79         struct rte_mbuf *m;
  80         uint16_t port_id = rxq->dp.dpq.port_id;
  81
  82         free_space = rxq->max_fill_level - (added - rxq->completed);
  83
  84         if (free_space < rxq->refill_threshold)
  85                 return;
  86
  87         bulks = free_space / RTE_DIM(objs);
  88         /* refill_threshold guarantees that bulks is positive */
  89         SFC_ASSERT(bulks > 0);
  90
  91         id = added & rxq->ptr_mask;
  92         do {
  93                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
  94                                                   RTE_DIM(objs)) < 0)) {
  95                         /*
  96                          * It is hardly a safe way to increment counter
  97                          * from different contexts, but all PMDs do it.
  98                          */
  99                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
 100                                 RTE_DIM(objs);
 101                         /* Return if we have posted nothing yet */
 102                         if (added == rxq->added)
 103                                 return;
 104                         /* Push posted */
 105                         break;
 106                 }
 107
 108                 for (i = 0; i < RTE_DIM(objs);
 109                      ++i, id = (id + 1) & rxq->ptr_mask) {
 110                         m = objs[i];
 111
 112                         __rte_mbuf_raw_sanity_check(m);
 113
 114                         rxd = &rxq->sw_desc[id];
 115                         rxd->mbuf = m;
 116
 117                         m->data_off = RTE_PKTMBUF_HEADROOM;
 118                         m->port = port_id;
 119
 120                         addr[i] = rte_pktmbuf_iova(m);
 121                 }
 122
 123                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 124                              RTE_DIM(objs), rxq->completed, added);
 125                 added += RTE_DIM(objs);
 126         } while (--bulks > 0);
 127
 128         SFC_ASSERT(added != rxq->added);
 129         rxq->added = added;
 130         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 131 }
 132
 133 static uint64_t
 134 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 135 {
 136         uint64_t mbuf_flags = 0;
 137
 138         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 139         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 140                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 141                 break;
 142         case EFX_PKT_IPV4:
 143                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 144                 break;
 145         default:
 146                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 147                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 148                            PKT_RX_IP_CKSUM_UNKNOWN);
 149                 break;
 150         }
 151
 152         switch ((desc_flags &
 153                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 154         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 155         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 156                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 157                 break;
 158         case EFX_PKT_TCP:
 159         case EFX_PKT_UDP:
 160                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 161                 break;
 162         default:
 163                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 164                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 165                            PKT_RX_L4_CKSUM_UNKNOWN);
 166                 break;
 167         }
 168
 169         return mbuf_flags;
 170 }
 171
 172 static uint32_t
 173 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 174 {
 175         return RTE_PTYPE_L2_ETHER |
 176                 ((desc_flags & EFX_PKT_IPV4) ?
 177                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 178                 ((desc_flags & EFX_PKT_IPV6) ?
 179                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 180                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 181                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 182 }
 183
 184 static const uint32_t *
 185 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 186 {
 187         static const uint32_t ptypes[] = {
 188                 RTE_PTYPE_L2_ETHER,
 189                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 190                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 191                 RTE_PTYPE_L4_TCP,
 192                 RTE_PTYPE_L4_UDP,
 193                 RTE_PTYPE_UNKNOWN
 194         };
 195
 196         return ptypes;
 197 }
 198
 199 static void
 200 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 201                         struct rte_mbuf *m)
 202 {
 203         uint8_t *mbuf_data;
 204
 205
 206         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 207                 return;
 208
 209         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 210
 211         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 212                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 213                                                       EFX_RX_HASHALG_TOEPLITZ,
 214                                                       mbuf_data);
 215
 216                 m->ol_flags |= PKT_RX_RSS_HASH;
 217         }
 218 }
 219
 220 static uint16_t
 221 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 222 {
 223         struct sfc_dp_rxq *dp_rxq = rx_queue;
 224         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 225         unsigned int completed;
 226         unsigned int prefix_size = rxq->prefix_size;
 227         unsigned int done_pkts = 0;
 228         boolean_t discard_next = B_FALSE;
 229         struct rte_mbuf *scatter_pkt = NULL;
 230
 231         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 232                 return 0;
 233
 234         sfc_ev_qpoll(rxq->evq);
 235
 236         completed = rxq->completed;
 237         while (completed != rxq->pending && done_pkts < nb_pkts) {
 238                 unsigned int id;
 239                 struct sfc_efx_rx_sw_desc *rxd;
 240                 struct rte_mbuf *m;
 241                 unsigned int seg_len;
 242                 unsigned int desc_flags;
 243
 244                 id = completed++ & rxq->ptr_mask;
 245                 rxd = &rxq->sw_desc[id];
 246                 m = rxd->mbuf;
 247                 desc_flags = rxd->flags;
 248
 249                 if (discard_next)
 250                         goto discard;
 251
 252                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 253                         goto discard;
 254
 255                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 256                         uint16_t tmp_size;
 257                         int rc __rte_unused;
 258
 259                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 260                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 261                         SFC_ASSERT(rc == 0);
 262                         seg_len = tmp_size;
 263                 } else {
 264                         seg_len = rxd->size - prefix_size;
 265                 }
 266
 267                 rte_pktmbuf_data_len(m) = seg_len;
 268                 rte_pktmbuf_pkt_len(m) = seg_len;
 269
 270                 if (scatter_pkt != NULL) {
 271                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 272                                 rte_pktmbuf_free(scatter_pkt);
 273                                 goto discard;
 274                         }
 275                         /* The packet to deliver */
 276                         m = scatter_pkt;
 277                 }
 278
 279                 if (desc_flags & EFX_PKT_CONT) {
 280                         /* The packet is scattered, more fragments to come */
 281                         scatter_pkt = m;
 282                         /* Further fragments have no prefix */
 283                         prefix_size = 0;
 284                         continue;
 285                 }
 286
 287                 /* Scattered packet is done */
 288                 scatter_pkt = NULL;
 289                 /* The first fragment of the packet has prefix */
 290                 prefix_size = rxq->prefix_size;
 291
 292                 m->ol_flags =
 293                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 294                 m->packet_type =
 295                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 296
 297                 /*
 298                  * Extract RSS hash from the packet prefix and
 299                  * set the corresponding field (if needed and possible)
 300                  */
 301                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 302
 303                 m->data_off += prefix_size;
 304
 305                 *rx_pkts++ = m;
 306                 done_pkts++;
 307                 continue;
 308
 309 discard:
 310                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 311                 rte_mbuf_raw_free(m);
 312                 rxd->mbuf = NULL;
 313         }
 314
 315         /* pending is only moved when entire packet is received */
 316         SFC_ASSERT(scatter_pkt == NULL);
 317
 318         rxq->completed = completed;
 319
 320         sfc_efx_rx_qrefill(rxq);
 321
 322         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN)
 323                 sfc_efx_rx_qprime(rxq);
 324
 325         return done_pkts;
 326 }
 327
 328 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 329 static unsigned int
 330 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 331 {
 332         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 333
 334         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 335                 return 0;
 336
 337         sfc_ev_qpoll(rxq->evq);
 338
 339         return rxq->pending - rxq->completed;
 340 }
 341
 342 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 343 static int
 344 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 345 {
 346         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 347
 348         if (unlikely(offset > rxq->ptr_mask))
 349                 return -EINVAL;
 350
 351         /*
 352          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 353          * it is required for the queue to be running, but the
 354          * check is omitted because API design assumes that it
 355          * is the duty of the caller to satisfy all conditions
 356          */
 357         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 358                    SFC_EFX_RXQ_FLAG_RUNNING);
 359         sfc_ev_qpoll(rxq->evq);
 360
 361         /*
 362          * There is a handful of reserved entries in the ring,
 363          * but an explicit check whether the offset points to
 364          * a reserved entry is neglected since the two checks
 365          * below rely on the figures which take the HW limits
 366          * into account and thus if an entry is reserved, the
 367          * checks will fail and UNAVAIL code will be returned
 368          */
 369
 370         if (offset < (rxq->pending - rxq->completed))
 371                 return RTE_ETH_RX_DESC_DONE;
 372
 373         if (offset < (rxq->added - rxq->completed))
 374                 return RTE_ETH_RX_DESC_AVAIL;
 375
 376         return RTE_ETH_RX_DESC_UNAVAIL;
 377 }
 378
 379 boolean_t
 380 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size,
 381                      boolean_t rx_scatter_enabled, uint32_t rx_scatter_max,
 382                      const char **error)
 383 {
 384         uint32_t effective_rx_scatter_max;
 385         uint32_t rx_scatter_bufs;
 386
 387         effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1;
 388         rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size);
 389
 390         if (rx_scatter_bufs > effective_rx_scatter_max) {
 391                 if (rx_scatter_enabled)
 392                         *error = "Possible number of Rx scatter buffers exceeds maximum number";
 393                 else
 394                         *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small";
 395                 return B_FALSE;
 396         }
 397
 398         return B_TRUE;
 399 }
 400
 401 /** Get Rx datapath ops by the datapath RxQ handle */
 402 const struct sfc_dp_rx *
 403 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 404 {
 405         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 406         struct rte_eth_dev *eth_dev;
 407         struct sfc_adapter_priv *sap;
 408
 409         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 410         eth_dev = &rte_eth_devices[dpq->port_id];
 411
 412         sap = sfc_adapter_priv_by_eth_dev(eth_dev);
 413
 414         return sap->dp_rx;
 415 }
 416
 417 struct sfc_rxq_info *
 418 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 419 {
 420         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 421         struct rte_eth_dev *eth_dev;
 422         struct sfc_adapter_shared *sas;
 423
 424         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 425         eth_dev = &rte_eth_devices[dpq->port_id];
 426
 427         sas = sfc_adapter_shared_by_eth_dev(eth_dev);
 428
 429         SFC_ASSERT(dpq->queue_id < sas->rxq_count);
 430         return &sas->rxq_info[dpq->queue_id];
 431 }
 432
 433 struct sfc_rxq *
 434 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 435 {
 436         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 437         struct rte_eth_dev *eth_dev;
 438         struct sfc_adapter *sa;
 439
 440         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 441         eth_dev = &rte_eth_devices[dpq->port_id];
 442
 443         sa = sfc_adapter_by_eth_dev(eth_dev);
 444
 445         SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count);
 446         return &sa->rxq_ctrl[dpq->queue_id];
 447 }
 448
 449 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 450 static int
 451 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 452                           __rte_unused struct sfc_dp_rx_hw_limits *limits,
 453                           __rte_unused struct rte_mempool *mb_pool,
 454                           unsigned int *rxq_entries,
 455                           unsigned int *evq_entries,
 456                           unsigned int *rxq_max_fill_level)
 457 {
 458         *rxq_entries = nb_rx_desc;
 459         *evq_entries = nb_rx_desc;
 460         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 461         return 0;
 462 }
 463
 464 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 465 static int
 466 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 467                    const struct rte_pci_addr *pci_addr, int socket_id,
 468                    const struct sfc_dp_rx_qcreate_info *info,
 469                    struct sfc_dp_rxq **dp_rxqp)
 470 {
 471         struct sfc_efx_rxq *rxq;
 472         int rc;
 473
 474         rc = ENOMEM;
 475         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 476                                  RTE_CACHE_LINE_SIZE, socket_id);
 477         if (rxq == NULL)
 478                 goto fail_rxq_alloc;
 479
 480         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 481
 482         rc = ENOMEM;
 483         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 484                                          info->rxq_entries,
 485                                          sizeof(*rxq->sw_desc),
 486                                          RTE_CACHE_LINE_SIZE, socket_id);
 487         if (rxq->sw_desc == NULL)
 488                 goto fail_desc_alloc;
 489
 490         /* efx datapath is bound to efx control path */
 491         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 492         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 493                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 494         rxq->ptr_mask = info->rxq_entries - 1;
 495         rxq->batch_max = info->batch_max;
 496         rxq->prefix_size = info->prefix_size;
 497         rxq->max_fill_level = info->max_fill_level;
 498         rxq->refill_threshold = info->refill_threshold;
 499         rxq->buf_size = info->buf_size;
 500         rxq->refill_mb_pool = info->refill_mb_pool;
 501
 502         *dp_rxqp = &rxq->dp;
 503         return 0;
 504
 505 fail_desc_alloc:
 506         rte_free(rxq);
 507
 508 fail_rxq_alloc:
 509         return rc;
 510 }
 511
 512 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 513 static void
 514 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 515 {
 516         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 517
 518         rte_free(rxq->sw_desc);
 519         rte_free(rxq);
 520 }
 521
 522
 523 /* Use qstop and qstart functions in the case of qstart failure */
 524 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 525 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 526
 527
 528 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 529 static int
 530 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 531                   __rte_unused unsigned int evq_read_ptr,
 532                   const efx_rx_prefix_layout_t *pinfo)
 533 {
 534         /* libefx-based datapath is specific to libefx-based PMD */
 535         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 536         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 537         int rc;
 538
 539         /*
 540          * libefx API is used to extract information from Rx prefix and
 541          * it guarantees consistency. Just do length check to ensure
 542          * that we reserved space in Rx buffers correctly.
 543          */
 544         if (rxq->prefix_size != pinfo->erpl_length)
 545                 return ENOTSUP;
 546
 547         rxq->common = crxq->common;
 548
 549         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 550
 551         sfc_efx_rx_qrefill(rxq);
 552
 553         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 554
 555         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) {
 556                 rc = sfc_efx_rx_qprime(rxq);
 557                 if (rc != 0)
 558                         goto fail_rx_qprime;
 559         }
 560
 561         return 0;
 562
 563 fail_rx_qprime:
 564         sfc_efx_rx_qstop(dp_rxq, NULL);
 565         sfc_efx_rx_qpurge(dp_rxq);
 566         return rc;
 567 }
 568
 569 static void
 570 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 571                  __rte_unused unsigned int *evq_read_ptr)
 572 {
 573         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 574
 575         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 576
 577         /* libefx-based datapath is bound to libefx-based PMD and uses
 578          * event queue structure directly. So, there is no necessity to
 579          * return EvQ read pointer.
 580          */
 581 }
 582
 583 static void
 584 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 585 {
 586         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 587         unsigned int i;
 588         struct sfc_efx_rx_sw_desc *rxd;
 589
 590         for (i = rxq->completed; i != rxq->added; ++i) {
 591                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 592                 rte_mbuf_raw_free(rxd->mbuf);
 593                 rxd->mbuf = NULL;
 594                 /* Packed stream relies on 0 in inactive SW desc.
 595                  * Rx queue stop is not performance critical, so
 596                  * there is no harm to do it always.
 597                  */
 598                 rxd->flags = 0;
 599                 rxd->size = 0;
 600         }
 601
 602         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 603 }
 604
 605 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable;
 606 static int
 607 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
 608 {
 609         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 610         int rc = 0;
 611
 612         rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN;
 613         if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) {
 614                 rc = sfc_efx_rx_qprime(rxq);
 615                 if (rc != 0)
 616                         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 617         }
 618         return rc;
 619 }
 620
 621 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable;
 622 static int
 623 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
 624 {
 625         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 626
 627         /* Cannot disarm, just disable rearm */
 628         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 629         return 0;
 630 }
 631
 632 struct sfc_dp_rx sfc_efx_rx = {
 633         .dp = {
 634                 .name           = SFC_KVARG_DATAPATH_EFX,
 635                 .type           = SFC_DP_RX,
 636                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_RX_EFX,
 637         },
 638         .features               = SFC_DP_RX_FEAT_INTR,
 639         .dev_offload_capa       = DEV_RX_OFFLOAD_CHECKSUM |
 640                                   DEV_RX_OFFLOAD_RSS_HASH,
 641         .queue_offload_capa     = DEV_RX_OFFLOAD_SCATTER,
 642         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 643         .qcreate                = sfc_efx_rx_qcreate,
 644         .qdestroy               = sfc_efx_rx_qdestroy,
 645         .qstart                 = sfc_efx_rx_qstart,
 646         .qstop                  = sfc_efx_rx_qstop,
 647         .qpurge                 = sfc_efx_rx_qpurge,
 648         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 649         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 650         .qdesc_status           = sfc_efx_rx_qdesc_status,
 651         .intr_enable            = sfc_efx_rx_intr_enable,
 652         .intr_disable           = sfc_efx_rx_intr_disable,
 653         .pkt_burst              = sfc_efx_recv_pkts,
 654 };
 655
 656 static void
 657 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
 658 {
 659         struct sfc_rxq_info *rxq_info;
 660         struct sfc_rxq *rxq;
 661         unsigned int retry_count;
 662         unsigned int wait_count;
 663         int rc;
 664
 665         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 666         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 667
 668         rxq = &sa->rxq_ctrl[sw_index];
 669
 670         /*
 671          * Retry Rx queue flushing in the case of flush failed or
 672          * timeout. In the worst case it can delay for 6 seconds.
 673          */
 674         for (retry_count = 0;
 675              ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
 676              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 677              ++retry_count) {
 678                 rc = efx_rx_qflush(rxq->common);
 679                 if (rc != 0) {
 680                         rxq_info->state |= (rc == EALREADY) ?
 681                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 682                         break;
 683                 }
 684                 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
 685                 rxq_info->state |= SFC_RXQ_FLUSHING;
 686
 687                 /*
 688                  * Wait for Rx queue flush done or failed event at least
 689                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 690                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 691                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 692                  */
 693                 wait_count = 0;
 694                 do {
 695                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 696                         sfc_ev_qpoll(rxq->evq);
 697                 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
 698                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 699
 700                 if (rxq_info->state & SFC_RXQ_FLUSHING)
 701                         sfc_err(sa, "RxQ %u flush timed out", sw_index);
 702
 703                 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
 704                         sfc_err(sa, "RxQ %u flush failed", sw_index);
 705
 706                 if (rxq_info->state & SFC_RXQ_FLUSHED)
 707                         sfc_notice(sa, "RxQ %u flushed", sw_index);
 708         }
 709
 710         sa->priv.dp_rx->qpurge(rxq_info->dp);
 711 }
 712
 713 static int
 714 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 715 {
 716         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
 717         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 718         struct sfc_port *port = &sa->port;
 719         int rc;
 720
 721         /*
 722          * If promiscuous or all-multicast mode has been requested, setting
 723          * filter for the default Rx queue might fail, in particular, while
 724          * running over PCI function which is not a member of corresponding
 725          * privilege groups; if this occurs, few iterations will be made to
 726          * repeat this step without promiscuous and all-multicast flags set
 727          */
 728 retry:
 729         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 730         if (rc == 0)
 731                 return 0;
 732         else if (rc != EOPNOTSUPP)
 733                 return rc;
 734
 735         if (port->promisc) {
 736                 sfc_warn(sa, "promiscuous mode has been requested, "
 737                              "but the HW rejects it");
 738                 sfc_warn(sa, "promiscuous mode will be disabled");
 739
 740                 port->promisc = B_FALSE;
 741                 sa->eth_dev->data->promiscuous = 0;
 742                 rc = sfc_set_rx_mode_unchecked(sa);
 743                 if (rc != 0)
 744                         return rc;
 745
 746                 goto retry;
 747         }
 748
 749         if (port->allmulti) {
 750                 sfc_warn(sa, "all-multicast mode has been requested, "
 751                              "but the HW rejects it");
 752                 sfc_warn(sa, "all-multicast mode will be disabled");
 753
 754                 port->allmulti = B_FALSE;
 755                 sa->eth_dev->data->all_multicast = 0;
 756                 rc = sfc_set_rx_mode_unchecked(sa);
 757                 if (rc != 0)
 758                         return rc;
 759
 760                 goto retry;
 761         }
 762
 763         return rc;
 764 }
 765
 766 int
 767 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
 768 {
 769         struct sfc_rxq_info *rxq_info;
 770         struct sfc_rxq *rxq;
 771         struct sfc_evq *evq;
 772         efx_rx_prefix_layout_t pinfo;
 773         int rc;
 774
 775         sfc_log_init(sa, "sw_index=%u", sw_index);
 776
 777         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 778
 779         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 780         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
 781
 782         rxq = &sa->rxq_ctrl[sw_index];
 783         evq = rxq->evq;
 784
 785         rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
 786         if (rc != 0)
 787                 goto fail_ev_qstart;
 788
 789         switch (rxq_info->type) {
 790         case EFX_RXQ_TYPE_DEFAULT:
 791                 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 792                         rxq->buf_size,
 793                         &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
 794                         rxq_info->type_flags, evq->common, &rxq->common);
 795                 break;
 796         case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
 797                 struct rte_mempool *mp = rxq_info->refill_mb_pool;
 798                 struct rte_mempool_info mp_info;
 799
 800                 rc = rte_mempool_ops_get_info(mp, &mp_info);
 801                 if (rc != 0) {
 802                         /* Positive errno is used in the driver */
 803                         rc = -rc;
 804                         goto fail_mp_get_info;
 805                 }
 806                 if (mp_info.contig_block_size <= 0) {
 807                         rc = EINVAL;
 808                         goto fail_bad_contig_block_size;
 809                 }
 810                 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
 811                         mp_info.contig_block_size, rxq->buf_size,
 812                         mp->header_size + mp->elt_size + mp->trailer_size,
 813                         sa->rxd_wait_timeout_ns,
 814                         &rxq->mem, rxq_info->entries, rxq_info->type_flags,
 815                         evq->common, &rxq->common);
 816                 break;
 817         }
 818         default:
 819                 rc = ENOTSUP;
 820         }
 821         if (rc != 0)
 822                 goto fail_rx_qcreate;
 823
 824         rc = efx_rx_prefix_get_layout(rxq->common, &pinfo);
 825         if (rc != 0)
 826                 goto fail_prefix_get_layout;
 827
 828         efx_rx_qenable(rxq->common);
 829
 830         rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr, &pinfo);
 831         if (rc != 0)
 832                 goto fail_dp_qstart;
 833
 834         rxq_info->state |= SFC_RXQ_STARTED;
 835
 836         if (sw_index == 0 && !sfc_sa2shared(sa)->isolated) {
 837                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 838                 if (rc != 0)
 839                         goto fail_mac_filter_default_rxq_set;
 840         }
 841
 842         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 843         sa->eth_dev->data->rx_queue_state[sw_index] =
 844                 RTE_ETH_QUEUE_STATE_STARTED;
 845
 846         return 0;
 847
 848 fail_mac_filter_default_rxq_set:
 849         sfc_rx_qflush(sa, sw_index);
 850         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 851         rxq_info->state = SFC_RXQ_INITIALIZED;
 852
 853 fail_dp_qstart:
 854         efx_rx_qdestroy(rxq->common);
 855
 856 fail_prefix_get_layout:
 857 fail_rx_qcreate:
 858 fail_bad_contig_block_size:
 859 fail_mp_get_info:
 860         sfc_ev_qstop(evq);
 861
 862 fail_ev_qstart:
 863         return rc;
 864 }
 865
 866 void
 867 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
 868 {
 869         struct sfc_rxq_info *rxq_info;
 870         struct sfc_rxq *rxq;
 871
 872         sfc_log_init(sa, "sw_index=%u", sw_index);
 873
 874         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 875
 876         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 877
 878         if (rxq_info->state == SFC_RXQ_INITIALIZED)
 879                 return;
 880         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 881
 882         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 883         sa->eth_dev->data->rx_queue_state[sw_index] =
 884                 RTE_ETH_QUEUE_STATE_STOPPED;
 885
 886         rxq = &sa->rxq_ctrl[sw_index];
 887         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 888
 889         if (sw_index == 0)
 890                 efx_mac_filter_default_rxq_clear(sa->nic);
 891
 892         sfc_rx_qflush(sa, sw_index);
 893
 894         rxq_info->state = SFC_RXQ_INITIALIZED;
 895
 896         efx_rx_qdestroy(rxq->common);
 897
 898         sfc_ev_qstop(rxq->evq);
 899 }
 900
 901 static uint64_t
 902 sfc_rx_get_offload_mask(struct sfc_adapter *sa)
 903 {
 904         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 905         uint64_t no_caps = 0;
 906
 907         if (encp->enc_tunnel_encapsulations_supported == 0)
 908                 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 909
 910         return ~no_caps;
 911 }
 912
 913 uint64_t
 914 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 915 {
 916         uint64_t caps = sa->priv.dp_rx->dev_offload_capa;
 917
 918         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 919
 920         return caps & sfc_rx_get_offload_mask(sa);
 921 }
 922
 923 uint64_t
 924 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 925 {
 926         return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa);
 927 }
 928
 929 static int
 930 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 931                    const struct rte_eth_rxconf *rx_conf,
 932                    __rte_unused uint64_t offloads)
 933 {
 934         int rc = 0;
 935
 936         if (rx_conf->rx_thresh.pthresh != 0 ||
 937             rx_conf->rx_thresh.hthresh != 0 ||
 938             rx_conf->rx_thresh.wthresh != 0) {
 939                 sfc_warn(sa,
 940                         "RxQ prefetch/host/writeback thresholds are not supported");
 941         }
 942
 943         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 944                 sfc_err(sa,
 945                         "RxQ free threshold too large: %u vs maximum %u",
 946                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 947                 rc = EINVAL;
 948         }
 949
 950         if (rx_conf->rx_drop_en == 0) {
 951                 sfc_err(sa, "RxQ drop disable is not supported");
 952                 rc = EINVAL;
 953         }
 954
 955         return rc;
 956 }
 957
 958 static unsigned int
 959 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 960 {
 961         uint32_t data_off;
 962         uint32_t order;
 963
 964         /* The mbuf object itself is always cache line aligned */
 965         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 966
 967         /* Data offset from mbuf object start */
 968         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 969                 RTE_PKTMBUF_HEADROOM;
 970
 971         order = MIN(order, rte_bsf32(data_off));
 972
 973         return 1u << order;
 974 }
 975
 976 static uint16_t
 977 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
 978 {
 979         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 980         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
 981         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
 982         uint16_t buf_size;
 983         unsigned int buf_aligned;
 984         unsigned int start_alignment;
 985         unsigned int end_padding_alignment;
 986
 987         /* Below it is assumed that both alignments are power of 2 */
 988         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
 989         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
 990
 991         /*
 992          * mbuf is always cache line aligned, double-check
 993          * that it meets rx buffer start alignment requirements.
 994          */
 995
 996         /* Start from mbuf pool data room size */
 997         buf_size = rte_pktmbuf_data_room_size(mb_pool);
 998
 999         /* Remove headroom */
1000         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
1001                 sfc_err(sa,
1002                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
1003                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
1004                 return 0;
1005         }
1006         buf_size -= RTE_PKTMBUF_HEADROOM;
1007
1008         /* Calculate guaranteed data start alignment */
1009         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
1010
1011         /* Reserve space for start alignment */
1012         if (buf_aligned < nic_align_start) {
1013                 start_alignment = nic_align_start - buf_aligned;
1014                 if (buf_size <= start_alignment) {
1015                         sfc_err(sa,
1016                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
1017                                 mb_pool->name,
1018                                 rte_pktmbuf_data_room_size(mb_pool),
1019                                 RTE_PKTMBUF_HEADROOM, start_alignment);
1020                         return 0;
1021                 }
1022                 buf_aligned = nic_align_start;
1023                 buf_size -= start_alignment;
1024         } else {
1025                 start_alignment = 0;
1026         }
1027
1028         /* Make sure that end padding does not write beyond the buffer */
1029         if (buf_aligned < nic_align_end) {
1030                 /*
1031                  * Estimate space which can be lost. If guarnteed buffer
1032                  * size is odd, lost space is (nic_align_end - 1). More
1033                  * accurate formula is below.
1034                  */
1035                 end_padding_alignment = nic_align_end -
1036                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
1037                 if (buf_size <= end_padding_alignment) {
1038                         sfc_err(sa,
1039                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
1040                                 mb_pool->name,
1041                                 rte_pktmbuf_data_room_size(mb_pool),
1042                                 RTE_PKTMBUF_HEADROOM, start_alignment,
1043                                 end_padding_alignment);
1044                         return 0;
1045                 }
1046                 buf_size -= end_padding_alignment;
1047         } else {
1048                 /*
1049                  * Start is aligned the same or better than end,
1050                  * just align length.
1051                  */
1052                 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end);
1053         }
1054
1055         return buf_size;
1056 }
1057
1058 int
1059 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
1060              uint16_t nb_rx_desc, unsigned int socket_id,
1061              const struct rte_eth_rxconf *rx_conf,
1062              struct rte_mempool *mb_pool)
1063 {
1064         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1065         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1066         int rc;
1067         unsigned int rxq_entries;
1068         unsigned int evq_entries;
1069         unsigned int rxq_max_fill_level;
1070         uint64_t offloads;
1071         uint16_t buf_size;
1072         struct sfc_rxq_info *rxq_info;
1073         struct sfc_evq *evq;
1074         struct sfc_rxq *rxq;
1075         struct sfc_dp_rx_qcreate_info info;
1076         struct sfc_dp_rx_hw_limits hw_limits;
1077         uint16_t rx_free_thresh;
1078         const char *error;
1079
1080         memset(&hw_limits, 0, sizeof(hw_limits));
1081         hw_limits.rxq_max_entries = sa->rxq_max_entries;
1082         hw_limits.rxq_min_entries = sa->rxq_min_entries;
1083         hw_limits.evq_max_entries = sa->evq_max_entries;
1084         hw_limits.evq_min_entries = sa->evq_min_entries;
1085
1086         rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool,
1087                                             &rxq_entries, &evq_entries,
1088                                             &rxq_max_fill_level);
1089         if (rc != 0)
1090                 goto fail_size_up_rings;
1091         SFC_ASSERT(rxq_entries >= sa->rxq_min_entries);
1092         SFC_ASSERT(rxq_entries <= sa->rxq_max_entries);
1093         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
1094
1095         offloads = rx_conf->offloads |
1096                 sa->eth_dev->data->dev_conf.rxmode.offloads;
1097         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
1098         if (rc != 0)
1099                 goto fail_bad_conf;
1100
1101         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1102         if (buf_size == 0) {
1103                 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
1104                         sw_index);
1105                 rc = EINVAL;
1106                 goto fail_bad_conf;
1107         }
1108
1109         if (!sfc_rx_check_scatter(sa->port.pdu, buf_size,
1110                                   encp->enc_rx_prefix_size,
1111                                   (offloads & DEV_RX_OFFLOAD_SCATTER),
1112                                   encp->enc_rx_scatter_max,
1113                                   &error)) {
1114                 sfc_err(sa, "RxQ %u MTU check failed: %s", sw_index, error);
1115                 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
1116                         "PDU size %u plus Rx prefix %u bytes",
1117                         sw_index, buf_size, (unsigned int)sa->port.pdu,
1118                         encp->enc_rx_prefix_size);
1119                 rc = EINVAL;
1120                 goto fail_bad_conf;
1121         }
1122
1123         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1124         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1125
1126         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1127         rxq_info->entries = rxq_entries;
1128
1129         if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1130                 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1131         else
1132                 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1133
1134         rxq_info->type_flags =
1135                 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1136                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1137
1138         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1139             (sfc_dp_rx_offload_capa(sa->priv.dp_rx) &
1140              DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0)
1141                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1142
1143         if (offloads & DEV_RX_OFFLOAD_RSS_HASH)
1144                 rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH;
1145
1146         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1147                           evq_entries, socket_id, &evq);
1148         if (rc != 0)
1149                 goto fail_ev_qinit;
1150
1151         rxq = &sa->rxq_ctrl[sw_index];
1152         rxq->evq = evq;
1153         rxq->hw_index = sw_index;
1154         /*
1155          * If Rx refill threshold is specified (its value is non zero) in
1156          * Rx configuration, use specified value. Otherwise use 1/8 of
1157          * the Rx descriptors number as the default. It allows to keep
1158          * Rx ring full-enough and does not refill too aggressive if
1159          * packet rate is high.
1160          *
1161          * Since PMD refills in bulks waiting for full bulk may be
1162          * refilled (basically round down), it is better to round up
1163          * here to mitigate it a bit.
1164          */
1165         rx_free_thresh = (rx_conf->rx_free_thresh != 0) ?
1166                 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8);
1167         /* Rx refill threshold cannot be smaller than refill bulk */
1168         rxq_info->refill_threshold =
1169                 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK);
1170         rxq_info->refill_mb_pool = mb_pool;
1171
1172         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 &&
1173             (offloads & DEV_RX_OFFLOAD_RSS_HASH))
1174                 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH;
1175         else
1176                 rxq_info->rxq_flags = 0;
1177
1178         rxq->buf_size = buf_size;
1179
1180         rc = sfc_dma_alloc(sa, "rxq", sw_index,
1181                            efx_rxq_size(sa->nic, rxq_info->entries),
1182                            socket_id, &rxq->mem);
1183         if (rc != 0)
1184                 goto fail_dma_alloc;
1185
1186         memset(&info, 0, sizeof(info));
1187         info.refill_mb_pool = rxq_info->refill_mb_pool;
1188         info.max_fill_level = rxq_max_fill_level;
1189         info.refill_threshold = rxq_info->refill_threshold;
1190         info.buf_size = buf_size;
1191         info.batch_max = encp->enc_rx_batch_max;
1192         info.prefix_size = encp->enc_rx_prefix_size;
1193         info.flags = rxq_info->rxq_flags;
1194         info.rxq_entries = rxq_info->entries;
1195         info.rxq_hw_ring = rxq->mem.esm_base;
1196         info.evq_hw_index = sfc_evq_index_by_rxq_sw_index(sa, sw_index);
1197         info.evq_entries = evq_entries;
1198         info.evq_hw_ring = evq->mem.esm_base;
1199         info.hw_index = rxq->hw_index;
1200         info.mem_bar = sa->mem_bar.esb_base;
1201         info.vi_window_shift = encp->enc_vi_window_shift;
1202         info.fcw_offset = sa->fcw_offset;
1203
1204         rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1205                                      &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1206                                      socket_id, &info, &rxq_info->dp);
1207         if (rc != 0)
1208                 goto fail_dp_rx_qcreate;
1209
1210         evq->dp_rxq = rxq_info->dp;
1211
1212         rxq_info->state = SFC_RXQ_INITIALIZED;
1213
1214         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1215
1216         return 0;
1217
1218 fail_dp_rx_qcreate:
1219         sfc_dma_free(sa, &rxq->mem);
1220
1221 fail_dma_alloc:
1222         sfc_ev_qfini(evq);
1223
1224 fail_ev_qinit:
1225         rxq_info->entries = 0;
1226
1227 fail_bad_conf:
1228 fail_size_up_rings:
1229         sfc_log_init(sa, "failed %d", rc);
1230         return rc;
1231 }
1232
1233 void
1234 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
1235 {
1236         struct sfc_rxq_info *rxq_info;
1237         struct sfc_rxq *rxq;
1238
1239         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1240         sa->eth_dev->data->rx_queues[sw_index] = NULL;
1241
1242         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1243
1244         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1245
1246         sa->priv.dp_rx->qdestroy(rxq_info->dp);
1247         rxq_info->dp = NULL;
1248
1249         rxq_info->state &= ~SFC_RXQ_INITIALIZED;
1250         rxq_info->entries = 0;
1251
1252         rxq = &sa->rxq_ctrl[sw_index];
1253
1254         sfc_dma_free(sa, &rxq->mem);
1255
1256         sfc_ev_qfini(rxq->evq);
1257         rxq->evq = NULL;
1258 }
1259
1260 /*
1261  * Mapping between RTE RSS hash functions and their EFX counterparts.
1262  */
1263 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1264         { ETH_RSS_NONFRAG_IPV4_TCP,
1265           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1266         { ETH_RSS_NONFRAG_IPV4_UDP,
1267           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1268         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1269           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1270         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1271           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1272         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1273           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1274           EFX_RX_HASH(IPV4, 2TUPLE) },
1275         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1276           ETH_RSS_IPV6_EX,
1277           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1278           EFX_RX_HASH(IPV6, 2TUPLE) }
1279 };
1280
1281 static efx_rx_hash_type_t
1282 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1283                             unsigned int *hash_type_flags_supported,
1284                             unsigned int nb_hash_type_flags_supported)
1285 {
1286         efx_rx_hash_type_t hash_type_masked = 0;
1287         unsigned int i, j;
1288
1289         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1290                 unsigned int class_tuple_lbn[] = {
1291                         EFX_RX_CLASS_IPV4_TCP_LBN,
1292                         EFX_RX_CLASS_IPV4_UDP_LBN,
1293                         EFX_RX_CLASS_IPV4_LBN,
1294                         EFX_RX_CLASS_IPV6_TCP_LBN,
1295                         EFX_RX_CLASS_IPV6_UDP_LBN,
1296                         EFX_RX_CLASS_IPV6_LBN
1297                 };
1298
1299                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1300                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1301                         unsigned int flag;
1302
1303                         tuple_mask <<= class_tuple_lbn[j];
1304                         flag = hash_type & tuple_mask;
1305
1306                         if (flag == hash_type_flags_supported[i])
1307                                 hash_type_masked |= flag;
1308                 }
1309         }
1310
1311         return hash_type_masked;
1312 }
1313
1314 int
1315 sfc_rx_hash_init(struct sfc_adapter *sa)
1316 {
1317         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1318         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1319         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1320         efx_rx_hash_alg_t alg;
1321         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1322         unsigned int nb_flags_supp;
1323         struct sfc_rss_hf_rte_to_efx *hf_map;
1324         struct sfc_rss_hf_rte_to_efx *entry;
1325         efx_rx_hash_type_t efx_hash_types;
1326         unsigned int i;
1327         int rc;
1328
1329         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1330                 alg = EFX_RX_HASHALG_TOEPLITZ;
1331         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1332                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1333         else
1334                 return EINVAL;
1335
1336         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1337                                          RTE_DIM(flags_supp), &nb_flags_supp);
1338         if (rc != 0)
1339                 return rc;
1340
1341         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1342                                    RTE_DIM(sfc_rss_hf_map),
1343                                    sizeof(*hf_map), 0, sa->socket_id);
1344         if (hf_map == NULL)
1345                 return ENOMEM;
1346
1347         entry = hf_map;
1348         efx_hash_types = 0;
1349         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1350                 efx_rx_hash_type_t ht;
1351
1352                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1353                                                  flags_supp, nb_flags_supp);
1354                 if (ht != 0) {
1355                         entry->rte = sfc_rss_hf_map[i].rte;
1356                         entry->efx = ht;
1357                         efx_hash_types |= ht;
1358                         ++entry;
1359                 }
1360         }
1361
1362         rss->hash_alg = alg;
1363         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1364         rss->hf_map = hf_map;
1365         rss->hash_types = efx_hash_types;
1366
1367         return 0;
1368 }
1369
1370 void
1371 sfc_rx_hash_fini(struct sfc_adapter *sa)
1372 {
1373         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1374
1375         rte_free(rss->hf_map);
1376 }
1377
1378 int
1379 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1380                      efx_rx_hash_type_t *efx)
1381 {
1382         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1383         efx_rx_hash_type_t hash_types = 0;
1384         unsigned int i;
1385
1386         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1387                 uint64_t rte_mask = rss->hf_map[i].rte;
1388
1389                 if ((rte & rte_mask) != 0) {
1390                         rte &= ~rte_mask;
1391                         hash_types |= rss->hf_map[i].efx;
1392                 }
1393         }
1394
1395         if (rte != 0) {
1396                 sfc_err(sa, "unsupported hash functions requested");
1397                 return EINVAL;
1398         }
1399
1400         *efx = hash_types;
1401
1402         return 0;
1403 }
1404
1405 uint64_t
1406 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx)
1407 {
1408         uint64_t rte = 0;
1409         unsigned int i;
1410
1411         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1412                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1413
1414                 if ((efx & hash_type) == hash_type)
1415                         rte |= rss->hf_map[i].rte;
1416         }
1417
1418         return rte;
1419 }
1420
1421 static int
1422 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1423                             struct rte_eth_rss_conf *conf)
1424 {
1425         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1426         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1427         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types);
1428         int rc;
1429
1430         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1431                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1432                     conf->rss_key != NULL)
1433                         return EINVAL;
1434         }
1435
1436         if (conf->rss_hf != 0) {
1437                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1438                 if (rc != 0)
1439                         return rc;
1440         }
1441
1442         if (conf->rss_key != NULL) {
1443                 if (conf->rss_key_len != sizeof(rss->key)) {
1444                         sfc_err(sa, "RSS key size is wrong (should be %zu)",
1445                                 sizeof(rss->key));
1446                         return EINVAL;
1447                 }
1448                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1449         }
1450
1451         rss->hash_types = efx_hash_types;
1452
1453         return 0;
1454 }
1455
1456 static int
1457 sfc_rx_rss_config(struct sfc_adapter *sa)
1458 {
1459         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1460         int rc = 0;
1461
1462         if (rss->channels > 0) {
1463                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1464                                            rss->hash_alg, rss->hash_types,
1465                                            B_TRUE);
1466                 if (rc != 0)
1467                         goto finish;
1468
1469                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1470                                           rss->key, sizeof(rss->key));
1471                 if (rc != 0)
1472                         goto finish;
1473
1474                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1475                                           rss->tbl, RTE_DIM(rss->tbl));
1476         }
1477
1478 finish:
1479         return rc;
1480 }
1481
1482 int
1483 sfc_rx_start(struct sfc_adapter *sa)
1484 {
1485         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1486         unsigned int sw_index;
1487         int rc;
1488
1489         sfc_log_init(sa, "rxq_count=%u", sas->rxq_count);
1490
1491         rc = efx_rx_init(sa->nic);
1492         if (rc != 0)
1493                 goto fail_rx_init;
1494
1495         rc = sfc_rx_rss_config(sa);
1496         if (rc != 0)
1497                 goto fail_rss_config;
1498
1499         for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) {
1500                 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED &&
1501                     (!sas->rxq_info[sw_index].deferred_start ||
1502                      sas->rxq_info[sw_index].deferred_started)) {
1503                         rc = sfc_rx_qstart(sa, sw_index);
1504                         if (rc != 0)
1505                                 goto fail_rx_qstart;
1506                 }
1507         }
1508
1509         return 0;
1510
1511 fail_rx_qstart:
1512         while (sw_index-- > 0)
1513                 sfc_rx_qstop(sa, sw_index);
1514
1515 fail_rss_config:
1516         efx_rx_fini(sa->nic);
1517
1518 fail_rx_init:
1519         sfc_log_init(sa, "failed %d", rc);
1520         return rc;
1521 }
1522
1523 void
1524 sfc_rx_stop(struct sfc_adapter *sa)
1525 {
1526         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1527         unsigned int sw_index;
1528
1529         sfc_log_init(sa, "rxq_count=%u", sas->rxq_count);
1530
1531         sw_index = sas->rxq_count;
1532         while (sw_index-- > 0) {
1533                 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED)
1534                         sfc_rx_qstop(sa, sw_index);
1535         }
1536
1537         efx_rx_fini(sa->nic);
1538 }
1539
1540 static int
1541 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1542 {
1543         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1544         struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index];
1545         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1546         unsigned int max_entries;
1547
1548         max_entries = encp->enc_rxq_max_ndescs;
1549         SFC_ASSERT(rte_is_power_of_2(max_entries));
1550
1551         rxq_info->max_entries = max_entries;
1552
1553         return 0;
1554 }
1555
1556 static int
1557 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1558 {
1559         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1560         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1561                                       sfc_rx_get_queue_offload_caps(sa);
1562         struct sfc_rss *rss = &sas->rss;
1563         int rc = 0;
1564
1565         switch (rxmode->mq_mode) {
1566         case ETH_MQ_RX_NONE:
1567                 /* No special checks are required */
1568                 break;
1569         case ETH_MQ_RX_RSS:
1570                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1571                         sfc_err(sa, "RSS is not available");
1572                         rc = EINVAL;
1573                 }
1574                 break;
1575         default:
1576                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1577                         rxmode->mq_mode);
1578                 rc = EINVAL;
1579         }
1580
1581         /*
1582          * Requested offloads are validated against supported by ethdev,
1583          * so unsupported offloads cannot be added as the result of
1584          * below check.
1585          */
1586         if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1587             (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1588                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1589                 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1590         }
1591
1592         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1593             (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1594                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1595                 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1596         }
1597
1598         return rc;
1599 }
1600
1601 /**
1602  * Destroy excess queues that are no longer needed after reconfiguration
1603  * or complete close.
1604  */
1605 static void
1606 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1607 {
1608         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1609         int sw_index;
1610
1611         SFC_ASSERT(nb_rx_queues <= sas->rxq_count);
1612
1613         sw_index = sas->rxq_count;
1614         while (--sw_index >= (int)nb_rx_queues) {
1615                 if (sas->rxq_info[sw_index].state & SFC_RXQ_INITIALIZED)
1616                         sfc_rx_qfini(sa, sw_index);
1617         }
1618
1619         sas->rxq_count = nb_rx_queues;
1620 }
1621
1622 /**
1623  * Initialize Rx subsystem.
1624  *
1625  * Called at device (re)configuration stage when number of receive queues is
1626  * specified together with other device level receive configuration.
1627  *
1628  * It should be used to allocate NUMA-unaware resources.
1629  */
1630 int
1631 sfc_rx_configure(struct sfc_adapter *sa)
1632 {
1633         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1634         struct sfc_rss *rss = &sas->rss;
1635         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1636         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1637         int rc;
1638
1639         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1640                      nb_rx_queues, sas->rxq_count);
1641
1642         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1643         if (rc != 0)
1644                 goto fail_check_mode;
1645
1646         if (nb_rx_queues == sas->rxq_count)
1647                 goto configure_rss;
1648
1649         if (sas->rxq_info == NULL) {
1650                 rc = ENOMEM;
1651                 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1652                                                   sizeof(sas->rxq_info[0]), 0,
1653                                                   sa->socket_id);
1654                 if (sas->rxq_info == NULL)
1655                         goto fail_rxqs_alloc;
1656
1657                 /*
1658                  * Allocate primary process only RxQ control from heap
1659                  * since it should not be shared.
1660                  */
1661                 rc = ENOMEM;
1662                 sa->rxq_ctrl = calloc(nb_rx_queues, sizeof(sa->rxq_ctrl[0]));
1663                 if (sa->rxq_ctrl == NULL)
1664                         goto fail_rxqs_ctrl_alloc;
1665         } else {
1666                 struct sfc_rxq_info *new_rxq_info;
1667                 struct sfc_rxq *new_rxq_ctrl;
1668
1669                 if (nb_rx_queues < sas->rxq_count)
1670                         sfc_rx_fini_queues(sa, nb_rx_queues);
1671
1672                 rc = ENOMEM;
1673                 new_rxq_info =
1674                         rte_realloc(sas->rxq_info,
1675                                     nb_rx_queues * sizeof(sas->rxq_info[0]), 0);
1676                 if (new_rxq_info == NULL && nb_rx_queues > 0)
1677                         goto fail_rxqs_realloc;
1678
1679                 rc = ENOMEM;
1680                 new_rxq_ctrl = realloc(sa->rxq_ctrl,
1681                                        nb_rx_queues * sizeof(sa->rxq_ctrl[0]));
1682                 if (new_rxq_ctrl == NULL && nb_rx_queues > 0)
1683                         goto fail_rxqs_ctrl_realloc;
1684
1685                 sas->rxq_info = new_rxq_info;
1686                 sa->rxq_ctrl = new_rxq_ctrl;
1687                 if (nb_rx_queues > sas->rxq_count) {
1688                         memset(&sas->rxq_info[sas->rxq_count], 0,
1689                                (nb_rx_queues - sas->rxq_count) *
1690                                sizeof(sas->rxq_info[0]));
1691                         memset(&sa->rxq_ctrl[sas->rxq_count], 0,
1692                                (nb_rx_queues - sas->rxq_count) *
1693                                sizeof(sa->rxq_ctrl[0]));
1694                 }
1695         }
1696
1697         while (sas->rxq_count < nb_rx_queues) {
1698                 rc = sfc_rx_qinit_info(sa, sas->rxq_count);
1699                 if (rc != 0)
1700                         goto fail_rx_qinit_info;
1701
1702                 sas->rxq_count++;
1703         }
1704
1705 configure_rss:
1706         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1707                          MIN(sas->rxq_count, EFX_MAXRSS) : 0;
1708
1709         if (rss->channels > 0) {
1710                 struct rte_eth_rss_conf *adv_conf_rss;
1711                 unsigned int sw_index;
1712
1713                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1714                         rss->tbl[sw_index] = sw_index % rss->channels;
1715
1716                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1717                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1718                 if (rc != 0)
1719                         goto fail_rx_process_adv_conf_rss;
1720         }
1721
1722         return 0;
1723
1724 fail_rx_process_adv_conf_rss:
1725 fail_rx_qinit_info:
1726 fail_rxqs_ctrl_realloc:
1727 fail_rxqs_realloc:
1728 fail_rxqs_ctrl_alloc:
1729 fail_rxqs_alloc:
1730         sfc_rx_close(sa);
1731
1732 fail_check_mode:
1733         sfc_log_init(sa, "failed %d", rc);
1734         return rc;
1735 }
1736
1737 /**
1738  * Shutdown Rx subsystem.
1739  *
1740  * Called at device close stage, for example, before device shutdown.
1741  */
1742 void
1743 sfc_rx_close(struct sfc_adapter *sa)
1744 {
1745         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1746
1747         sfc_rx_fini_queues(sa, 0);
1748
1749         rss->channels = 0;
1750
1751         free(sa->rxq_ctrl);
1752         sa->rxq_ctrl = NULL;
1753
1754         rte_free(sfc_sa2shared(sa)->rxq_info);
1755         sfc_sa2shared(sa)->rxq_info = NULL;
1756 }