4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <rte_mempool.h>
37 #include "sfc_debug.h"
41 #include "sfc_kvargs.h"
42 #include "sfc_tweak.h"
45 * Maximum number of Rx queue flush attempt in the case of failure or
48 #define SFC_RX_QFLUSH_ATTEMPTS (3)
51 * Time to wait between event queue polling attempts when waiting for Rx
52 * queue flush done or failed events.
54 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1)
57 * Maximum number of event queue polling attempts when waiting for Rx queue
58 * flush done or failed events. It defines Rx queue flush attempt timeout
59 * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
61 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000)
64 sfc_rx_qflush_done(struct sfc_rxq *rxq)
66 rxq->state |= SFC_RXQ_FLUSHED;
67 rxq->state &= ~SFC_RXQ_FLUSHING;
71 sfc_rx_qflush_failed(struct sfc_rxq *rxq)
73 rxq->state |= SFC_RXQ_FLUSH_FAILED;
74 rxq->state &= ~SFC_RXQ_FLUSHING;
78 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
80 unsigned int free_space;
82 void *objs[SFC_RX_REFILL_BULK];
83 efsys_dma_addr_t addr[RTE_DIM(objs)];
84 unsigned int added = rxq->added;
87 struct sfc_efx_rx_sw_desc *rxd;
89 uint16_t port_id = rxq->dp.dpq.port_id;
91 free_space = EFX_RXQ_LIMIT(rxq->ptr_mask + 1) -
92 (added - rxq->completed);
94 if (free_space < rxq->refill_threshold)
97 bulks = free_space / RTE_DIM(objs);
98 /* refill_threshold guarantees that bulks is positive */
99 SFC_ASSERT(bulks > 0);
101 id = added & rxq->ptr_mask;
103 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
104 RTE_DIM(objs)) < 0)) {
106 * It is hardly a safe way to increment counter
107 * from different contexts, but all PMDs do it.
109 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
111 /* Return if we have posted nothing yet */
112 if (added == rxq->added)
118 for (i = 0; i < RTE_DIM(objs);
119 ++i, id = (id + 1) & rxq->ptr_mask) {
122 rxd = &rxq->sw_desc[id];
125 rte_mbuf_refcnt_set(m, 1);
126 m->data_off = RTE_PKTMBUF_HEADROOM;
131 addr[i] = rte_pktmbuf_mtophys(m);
134 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
135 RTE_DIM(objs), rxq->completed, added);
136 added += RTE_DIM(objs);
137 } while (--bulks > 0);
139 SFC_ASSERT(added != rxq->added);
141 efx_rx_qpush(rxq->common, added, &rxq->pushed);
145 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
147 uint64_t mbuf_flags = 0;
149 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
150 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
151 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
154 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
157 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
158 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
159 PKT_RX_IP_CKSUM_UNKNOWN);
163 switch ((desc_flags &
164 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
165 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
166 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
167 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
171 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
174 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
175 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
176 PKT_RX_L4_CKSUM_UNKNOWN);
184 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
186 return RTE_PTYPE_L2_ETHER |
187 ((desc_flags & EFX_PKT_IPV4) ?
188 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
189 ((desc_flags & EFX_PKT_IPV6) ?
190 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
191 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
192 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
195 static const uint32_t *
196 sfc_efx_supported_ptypes_get(void)
198 static const uint32_t ptypes[] = {
200 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
201 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
211 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
214 #if EFSYS_OPT_RX_SCALE
218 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
221 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
223 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
224 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
225 EFX_RX_HASHALG_TOEPLITZ,
228 m->ol_flags |= PKT_RX_RSS_HASH;
234 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
236 struct sfc_dp_rxq *dp_rxq = rx_queue;
237 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
238 unsigned int completed;
239 unsigned int prefix_size = rxq->prefix_size;
240 unsigned int done_pkts = 0;
241 boolean_t discard_next = B_FALSE;
242 struct rte_mbuf *scatter_pkt = NULL;
244 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
247 sfc_ev_qpoll(rxq->evq);
249 completed = rxq->completed;
250 while (completed != rxq->pending && done_pkts < nb_pkts) {
252 struct sfc_efx_rx_sw_desc *rxd;
254 unsigned int seg_len;
255 unsigned int desc_flags;
257 id = completed++ & rxq->ptr_mask;
258 rxd = &rxq->sw_desc[id];
260 desc_flags = rxd->flags;
265 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
268 if (desc_flags & EFX_PKT_PREFIX_LEN) {
272 rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
273 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
277 seg_len = rxd->size - prefix_size;
280 rte_pktmbuf_data_len(m) = seg_len;
281 rte_pktmbuf_pkt_len(m) = seg_len;
283 if (scatter_pkt != NULL) {
284 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
285 rte_mempool_put(rxq->refill_mb_pool,
289 /* The packet to deliver */
293 if (desc_flags & EFX_PKT_CONT) {
294 /* The packet is scattered, more fragments to come */
296 /* Futher fragments have no prefix */
301 /* Scattered packet is done */
303 /* The first fragment of the packet has prefix */
304 prefix_size = rxq->prefix_size;
307 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
309 sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
312 * Extract RSS hash from the packet prefix and
313 * set the corresponding field (if needed and possible)
315 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
317 m->data_off += prefix_size;
324 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
325 rte_mempool_put(rxq->refill_mb_pool, m);
329 /* pending is only moved when entire packet is received */
330 SFC_ASSERT(scatter_pkt == NULL);
332 rxq->completed = completed;
334 sfc_efx_rx_qrefill(rxq);
339 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
341 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
343 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
345 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
348 sfc_ev_qpoll(rxq->evq);
350 return rxq->pending - rxq->completed;
354 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
356 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
357 struct rte_eth_dev *eth_dev;
358 struct sfc_adapter *sa;
361 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
362 eth_dev = &rte_eth_devices[dpq->port_id];
364 sa = eth_dev->data->dev_private;
366 SFC_ASSERT(dpq->queue_id < sa->rxq_count);
367 rxq = sa->rxq_info[dpq->queue_id].rxq;
369 SFC_ASSERT(rxq != NULL);
373 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
375 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
376 const struct rte_pci_addr *pci_addr, int socket_id,
377 const struct sfc_dp_rx_qcreate_info *info,
378 struct sfc_dp_rxq **dp_rxqp)
380 struct sfc_efx_rxq *rxq;
384 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
385 RTE_CACHE_LINE_SIZE, socket_id);
389 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
392 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
394 sizeof(*rxq->sw_desc),
395 RTE_CACHE_LINE_SIZE, socket_id);
396 if (rxq->sw_desc == NULL)
397 goto fail_desc_alloc;
399 /* efx datapath is bound to efx control path */
400 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
401 if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
402 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
403 rxq->ptr_mask = info->rxq_entries - 1;
404 rxq->batch_max = info->batch_max;
405 rxq->prefix_size = info->prefix_size;
406 rxq->refill_threshold = info->refill_threshold;
407 rxq->buf_size = info->buf_size;
408 rxq->refill_mb_pool = info->refill_mb_pool;
420 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
422 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
424 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
426 rte_free(rxq->sw_desc);
430 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
432 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
433 __rte_unused unsigned int evq_read_ptr)
435 /* libefx-based datapath is specific to libefx-based PMD */
436 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
437 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
439 rxq->common = crxq->common;
441 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
443 sfc_efx_rx_qrefill(rxq);
445 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
450 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
452 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
453 __rte_unused unsigned int *evq_read_ptr)
455 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
457 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
459 /* libefx-based datapath is bound to libefx-based PMD and uses
460 * event queue structure directly. So, there is no necessity to
461 * return EvQ read pointer.
465 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
467 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
469 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
471 struct sfc_efx_rx_sw_desc *rxd;
473 for (i = rxq->completed; i != rxq->added; ++i) {
474 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
475 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
477 /* Packed stream relies on 0 in inactive SW desc.
478 * Rx queue stop is not performance critical, so
479 * there is no harm to do it always.
485 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
488 struct sfc_dp_rx sfc_efx_rx = {
490 .name = SFC_KVARG_DATAPATH_EFX,
494 .features = SFC_DP_RX_FEAT_SCATTER,
495 .qcreate = sfc_efx_rx_qcreate,
496 .qdestroy = sfc_efx_rx_qdestroy,
497 .qstart = sfc_efx_rx_qstart,
498 .qstop = sfc_efx_rx_qstop,
499 .qpurge = sfc_efx_rx_qpurge,
500 .supported_ptypes_get = sfc_efx_supported_ptypes_get,
501 .qdesc_npending = sfc_efx_rx_qdesc_npending,
502 .pkt_burst = sfc_efx_recv_pkts,
506 sfc_rx_qdesc_npending(struct sfc_adapter *sa, unsigned int sw_index)
510 SFC_ASSERT(sw_index < sa->rxq_count);
511 rxq = sa->rxq_info[sw_index].rxq;
513 if (rxq == NULL || (rxq->state & SFC_RXQ_STARTED) == 0)
516 return sa->dp_rx->qdesc_npending(rxq->dp);
520 sfc_rx_qdesc_done(struct sfc_dp_rxq *dp_rxq, unsigned int offset)
522 struct sfc_rxq *rxq = sfc_rxq_by_dp_rxq(dp_rxq);
524 return offset < rxq->evq->sa->dp_rx->qdesc_npending(dp_rxq);
528 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
531 unsigned int retry_count;
532 unsigned int wait_count;
534 rxq = sa->rxq_info[sw_index].rxq;
535 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
538 * Retry Rx queue flushing in the case of flush failed or
539 * timeout. In the worst case it can delay for 6 seconds.
541 for (retry_count = 0;
542 ((rxq->state & SFC_RXQ_FLUSHED) == 0) &&
543 (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
545 if (efx_rx_qflush(rxq->common) != 0) {
546 rxq->state |= SFC_RXQ_FLUSH_FAILED;
549 rxq->state &= ~SFC_RXQ_FLUSH_FAILED;
550 rxq->state |= SFC_RXQ_FLUSHING;
553 * Wait for Rx queue flush done or failed event at least
554 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
555 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
556 * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
560 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
561 sfc_ev_qpoll(rxq->evq);
562 } while ((rxq->state & SFC_RXQ_FLUSHING) &&
563 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
565 if (rxq->state & SFC_RXQ_FLUSHING)
566 sfc_err(sa, "RxQ %u flush timed out", sw_index);
568 if (rxq->state & SFC_RXQ_FLUSH_FAILED)
569 sfc_err(sa, "RxQ %u flush failed", sw_index);
571 if (rxq->state & SFC_RXQ_FLUSHED)
572 sfc_info(sa, "RxQ %u flushed", sw_index);
575 sa->dp_rx->qpurge(rxq->dp);
579 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
581 boolean_t rss = (sa->rss_channels > 1) ? B_TRUE : B_FALSE;
582 struct sfc_port *port = &sa->port;
586 * If promiscuous or all-multicast mode has been requested, setting
587 * filter for the default Rx queue might fail, in particular, while
588 * running over PCI function which is not a member of corresponding
589 * privilege groups; if this occurs, few iterations will be made to
590 * repeat this step without promiscuous and all-multicast flags set
593 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, rss);
596 else if (rc != EOPNOTSUPP)
600 sfc_warn(sa, "promiscuous mode has been requested, "
601 "but the HW rejects it");
602 sfc_warn(sa, "promiscuous mode will be disabled");
604 port->promisc = B_FALSE;
605 rc = sfc_set_rx_mode(sa);
612 if (port->allmulti) {
613 sfc_warn(sa, "all-multicast mode has been requested, "
614 "but the HW rejects it");
615 sfc_warn(sa, "all-multicast mode will be disabled");
617 port->allmulti = B_FALSE;
618 rc = sfc_set_rx_mode(sa);
629 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
631 struct sfc_rxq_info *rxq_info;
636 sfc_log_init(sa, "sw_index=%u", sw_index);
638 SFC_ASSERT(sw_index < sa->rxq_count);
640 rxq_info = &sa->rxq_info[sw_index];
642 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
646 rc = sfc_ev_qstart(sa, evq->evq_index);
650 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
651 &rxq->mem, rxq_info->entries,
652 0 /* not used on EF10 */, evq->common,
655 goto fail_rx_qcreate;
657 efx_rx_qenable(rxq->common);
659 rc = sa->dp_rx->qstart(rxq->dp, evq->read_ptr);
663 rxq->state |= SFC_RXQ_STARTED;
666 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
668 goto fail_mac_filter_default_rxq_set;
671 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
672 sa->eth_dev->data->rx_queue_state[sw_index] =
673 RTE_ETH_QUEUE_STATE_STARTED;
677 fail_mac_filter_default_rxq_set:
678 sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
681 sfc_rx_qflush(sa, sw_index);
684 sfc_ev_qstop(sa, evq->evq_index);
691 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
693 struct sfc_rxq_info *rxq_info;
696 sfc_log_init(sa, "sw_index=%u", sw_index);
698 SFC_ASSERT(sw_index < sa->rxq_count);
700 rxq_info = &sa->rxq_info[sw_index];
703 if (rxq->state == SFC_RXQ_INITIALIZED)
705 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
707 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
708 sa->eth_dev->data->rx_queue_state[sw_index] =
709 RTE_ETH_QUEUE_STATE_STOPPED;
711 sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
714 efx_mac_filter_default_rxq_clear(sa->nic);
716 sfc_rx_qflush(sa, sw_index);
718 rxq->state = SFC_RXQ_INITIALIZED;
720 efx_rx_qdestroy(rxq->common);
722 sfc_ev_qstop(sa, rxq->evq->evq_index);
726 sfc_rx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_rx_desc,
727 const struct rte_eth_rxconf *rx_conf)
729 const uint16_t rx_free_thresh_max = EFX_RXQ_LIMIT(nb_rx_desc);
732 if (rx_conf->rx_thresh.pthresh != 0 ||
733 rx_conf->rx_thresh.hthresh != 0 ||
734 rx_conf->rx_thresh.wthresh != 0) {
736 "RxQ prefetch/host/writeback thresholds are not supported");
740 if (rx_conf->rx_free_thresh > rx_free_thresh_max) {
742 "RxQ free threshold too large: %u vs maximum %u",
743 rx_conf->rx_free_thresh, rx_free_thresh_max);
747 if (rx_conf->rx_drop_en == 0) {
748 sfc_err(sa, "RxQ drop disable is not supported");
756 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
761 /* The mbuf object itself is always cache line aligned */
762 order = rte_bsf32(RTE_CACHE_LINE_SIZE);
764 /* Data offset from mbuf object start */
765 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
766 RTE_PKTMBUF_HEADROOM;
768 order = MIN(order, rte_bsf32(data_off));
770 return 1u << (order - 1);
774 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
776 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
777 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
778 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
780 unsigned int buf_aligned;
781 unsigned int start_alignment;
782 unsigned int end_padding_alignment;
784 /* Below it is assumed that both alignments are power of 2 */
785 SFC_ASSERT(rte_is_power_of_2(nic_align_start));
786 SFC_ASSERT(rte_is_power_of_2(nic_align_end));
789 * mbuf is always cache line aligned, double-check
790 * that it meets rx buffer start alignment requirements.
793 /* Start from mbuf pool data room size */
794 buf_size = rte_pktmbuf_data_room_size(mb_pool);
796 /* Remove headroom */
797 if (buf_size <= RTE_PKTMBUF_HEADROOM) {
799 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
800 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
803 buf_size -= RTE_PKTMBUF_HEADROOM;
805 /* Calculate guaranteed data start alignment */
806 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
808 /* Reserve space for start alignment */
809 if (buf_aligned < nic_align_start) {
810 start_alignment = nic_align_start - buf_aligned;
811 if (buf_size <= start_alignment) {
813 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
815 rte_pktmbuf_data_room_size(mb_pool),
816 RTE_PKTMBUF_HEADROOM, start_alignment);
819 buf_aligned = nic_align_start;
820 buf_size -= start_alignment;
825 /* Make sure that end padding does not write beyond the buffer */
826 if (buf_aligned < nic_align_end) {
828 * Estimate space which can be lost. If guarnteed buffer
829 * size is odd, lost space is (nic_align_end - 1). More
830 * accurate formula is below.
832 end_padding_alignment = nic_align_end -
833 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
834 if (buf_size <= end_padding_alignment) {
836 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
838 rte_pktmbuf_data_room_size(mb_pool),
839 RTE_PKTMBUF_HEADROOM, start_alignment,
840 end_padding_alignment);
843 buf_size -= end_padding_alignment;
846 * Start is aligned the same or better than end,
849 buf_size = P2ALIGN(buf_size, nic_align_end);
856 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
857 uint16_t nb_rx_desc, unsigned int socket_id,
858 const struct rte_eth_rxconf *rx_conf,
859 struct rte_mempool *mb_pool)
861 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
864 struct sfc_rxq_info *rxq_info;
865 unsigned int evq_index;
868 struct sfc_dp_rx_qcreate_info info;
870 rc = sfc_rx_qcheck_conf(sa, nb_rx_desc, rx_conf);
874 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
876 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
882 if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) &&
883 !sa->eth_dev->data->dev_conf.rxmode.enable_scatter) {
884 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool "
885 "object size is too small", sw_index);
886 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
887 "PDU size %u plus Rx prefix %u bytes",
888 sw_index, buf_size, (unsigned int)sa->port.pdu,
889 encp->enc_rx_prefix_size);
894 SFC_ASSERT(sw_index < sa->rxq_count);
895 rxq_info = &sa->rxq_info[sw_index];
897 SFC_ASSERT(nb_rx_desc <= rxq_info->max_entries);
898 rxq_info->entries = nb_rx_desc;
900 sa->eth_dev->data->dev_conf.rxmode.enable_scatter ?
901 EFX_RXQ_TYPE_SCATTER : EFX_RXQ_TYPE_DEFAULT;
903 evq_index = sfc_evq_index_by_rxq_sw_index(sa, sw_index);
905 rc = sfc_ev_qinit(sa, evq_index, rxq_info->entries, socket_id);
909 evq = sa->evq_info[evq_index].evq;
912 rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE,
920 rxq->hw_index = sw_index;
921 rxq->refill_threshold =
922 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK);
923 rxq->refill_mb_pool = mb_pool;
925 rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries),
926 socket_id, &rxq->mem);
930 memset(&info, 0, sizeof(info));
931 info.refill_mb_pool = rxq->refill_mb_pool;
932 info.refill_threshold = rxq->refill_threshold;
933 info.buf_size = buf_size;
934 info.batch_max = encp->enc_rx_batch_max;
935 info.prefix_size = encp->enc_rx_prefix_size;
937 #if EFSYS_OPT_RX_SCALE
938 if (sa->hash_support == EFX_RX_HASH_AVAILABLE)
939 info.flags |= SFC_RXQ_FLAG_RSS_HASH;
942 info.rxq_entries = rxq_info->entries;
943 info.rxq_hw_ring = rxq->mem.esm_base;
944 info.evq_entries = rxq_info->entries;
945 info.evq_hw_ring = evq->mem.esm_base;
946 info.hw_index = rxq->hw_index;
947 info.mem_bar = sa->mem_bar.esb_base;
949 rc = sa->dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
950 &SFC_DEV_TO_PCI(sa->eth_dev)->addr,
951 socket_id, &info, &rxq->dp);
953 goto fail_dp_rx_qcreate;
955 evq->dp_rxq = rxq->dp;
957 rxq->state = SFC_RXQ_INITIALIZED;
959 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
964 sfc_dma_free(sa, &rxq->mem);
967 rxq_info->rxq = NULL;
971 sfc_ev_qfini(sa, evq_index);
974 rxq_info->entries = 0;
977 sfc_log_init(sa, "failed %d", rc);
982 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
984 struct sfc_rxq_info *rxq_info;
987 SFC_ASSERT(sw_index < sa->rxq_count);
989 rxq_info = &sa->rxq_info[sw_index];
992 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
994 sa->dp_rx->qdestroy(rxq->dp);
997 rxq_info->rxq = NULL;
998 rxq_info->entries = 0;
1000 sfc_dma_free(sa, &rxq->mem);
1003 sfc_ev_qfini(sa, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
1006 #if EFSYS_OPT_RX_SCALE
1008 sfc_rte_to_efx_hash_type(uint64_t rss_hf)
1010 efx_rx_hash_type_t efx_hash_types = 0;
1012 if ((rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 |
1013 ETH_RSS_NONFRAG_IPV4_OTHER)) != 0)
1014 efx_hash_types |= EFX_RX_HASH_IPV4;
1016 if ((rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) != 0)
1017 efx_hash_types |= EFX_RX_HASH_TCPIPV4;
1019 if ((rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 |
1020 ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_IPV6_EX)) != 0)
1021 efx_hash_types |= EFX_RX_HASH_IPV6;
1023 if ((rss_hf & (ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX)) != 0)
1024 efx_hash_types |= EFX_RX_HASH_TCPIPV6;
1026 return efx_hash_types;
1030 sfc_efx_to_rte_hash_type(efx_rx_hash_type_t efx_hash_types)
1032 uint64_t rss_hf = 0;
1034 if ((efx_hash_types & EFX_RX_HASH_IPV4) != 0)
1035 rss_hf |= (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 |
1036 ETH_RSS_NONFRAG_IPV4_OTHER);
1038 if ((efx_hash_types & EFX_RX_HASH_TCPIPV4) != 0)
1039 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1041 if ((efx_hash_types & EFX_RX_HASH_IPV6) != 0)
1042 rss_hf |= (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 |
1043 ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_IPV6_EX);
1045 if ((efx_hash_types & EFX_RX_HASH_TCPIPV6) != 0)
1046 rss_hf |= (ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX);
1053 sfc_rx_rss_config(struct sfc_adapter *sa)
1057 #if EFSYS_OPT_RX_SCALE
1058 if (sa->rss_channels > 1) {
1059 rc = efx_rx_scale_mode_set(sa->nic, EFX_RX_HASHALG_TOEPLITZ,
1060 sa->rss_hash_types, B_TRUE);
1064 rc = efx_rx_scale_key_set(sa->nic, sa->rss_key,
1065 sizeof(sa->rss_key));
1069 rc = efx_rx_scale_tbl_set(sa->nic, sa->rss_tbl,
1070 sizeof(sa->rss_tbl));
1079 sfc_rx_start(struct sfc_adapter *sa)
1081 unsigned int sw_index;
1084 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1086 rc = efx_rx_init(sa->nic);
1090 rc = sfc_rx_rss_config(sa);
1092 goto fail_rss_config;
1094 for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1095 if ((!sa->rxq_info[sw_index].deferred_start ||
1096 sa->rxq_info[sw_index].deferred_started)) {
1097 rc = sfc_rx_qstart(sa, sw_index);
1099 goto fail_rx_qstart;
1106 while (sw_index-- > 0)
1107 sfc_rx_qstop(sa, sw_index);
1110 efx_rx_fini(sa->nic);
1113 sfc_log_init(sa, "failed %d", rc);
1118 sfc_rx_stop(struct sfc_adapter *sa)
1120 unsigned int sw_index;
1122 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1124 sw_index = sa->rxq_count;
1125 while (sw_index-- > 0) {
1126 if (sa->rxq_info[sw_index].rxq != NULL)
1127 sfc_rx_qstop(sa, sw_index);
1130 efx_rx_fini(sa->nic);
1134 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1136 struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];
1137 unsigned int max_entries;
1139 max_entries = EFX_RXQ_MAXNDESCS;
1140 SFC_ASSERT(rte_is_power_of_2(max_entries));
1142 rxq_info->max_entries = max_entries;
1148 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1152 switch (rxmode->mq_mode) {
1153 case ETH_MQ_RX_NONE:
1154 /* No special checks are required */
1156 #if EFSYS_OPT_RX_SCALE
1158 if (sa->rss_support == EFX_RX_SCALE_UNAVAILABLE) {
1159 sfc_err(sa, "RSS is not available");
1165 sfc_err(sa, "Rx multi-queue mode %u not supported",
1170 if (rxmode->header_split) {
1171 sfc_err(sa, "Header split on Rx not supported");
1175 if (rxmode->hw_vlan_filter) {
1176 sfc_err(sa, "HW VLAN filtering not supported");
1180 if (rxmode->hw_vlan_strip) {
1181 sfc_err(sa, "HW VLAN stripping not supported");
1185 if (rxmode->hw_vlan_extend) {
1187 "Q-in-Q HW VLAN stripping not supported");
1191 if (!rxmode->hw_strip_crc) {
1193 "FCS stripping control not supported - always stripped");
1194 rxmode->hw_strip_crc = 1;
1197 if (rxmode->enable_scatter &&
1198 (~sa->dp_rx->features & SFC_DP_RX_FEAT_SCATTER)) {
1199 sfc_err(sa, "Rx scatter not supported by %s datapath",
1200 sa->dp_rx->dp.name);
1204 if (rxmode->enable_lro) {
1205 sfc_err(sa, "LRO not supported");
1213 * Initialize Rx subsystem.
1215 * Called at device configuration stage when number of receive queues is
1216 * specified together with other device level receive configuration.
1218 * It should be used to allocate NUMA-unaware resources.
1221 sfc_rx_init(struct sfc_adapter *sa)
1223 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1224 unsigned int sw_index;
1227 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1229 goto fail_check_mode;
1231 sa->rxq_count = sa->eth_dev->data->nb_rx_queues;
1234 sa->rxq_info = rte_calloc_socket("sfc-rxqs", sa->rxq_count,
1235 sizeof(struct sfc_rxq_info), 0,
1237 if (sa->rxq_info == NULL)
1238 goto fail_rxqs_alloc;
1240 for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1241 rc = sfc_rx_qinit_info(sa, sw_index);
1243 goto fail_rx_qinit_info;
1246 #if EFSYS_OPT_RX_SCALE
1247 sa->rss_channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1248 MIN(sa->rxq_count, EFX_MAXRSS) : 1;
1250 if (sa->rss_channels > 1) {
1251 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1252 sa->rss_tbl[sw_index] = sw_index % sa->rss_channels;
1259 rte_free(sa->rxq_info);
1260 sa->rxq_info = NULL;
1265 sfc_log_init(sa, "failed %d", rc);
1270 * Shutdown Rx subsystem.
1272 * Called at device close stage, for example, before device
1273 * reconfiguration or shutdown.
1276 sfc_rx_fini(struct sfc_adapter *sa)
1278 unsigned int sw_index;
1280 sw_index = sa->rxq_count;
1281 while (sw_index-- > 0) {
1282 if (sa->rxq_info[sw_index].rxq != NULL)
1283 sfc_rx_qfini(sa, sw_index);
1286 rte_free(sa->rxq_info);
1287 sa->rxq_info = NULL;