drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2016-2019 Solarflare Communications Inc.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_kvargs.h"
  20 #include "sfc_tweak.h"
  21
  22 /*
  23  * Maximum number of Rx queue flush attempt in the case of failure or
  24  * flush timeout
  25  */
  26 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  27
  28 /*
  29  * Time to wait between event queue polling attempts when waiting for Rx
  30  * queue flush done or failed events.
  31  */
  32 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  33
  34 /*
  35  * Maximum number of event queue polling attempts when waiting for Rx queue
  36  * flush done or failed events. It defines Rx queue flush attempt timeout
  37  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  38  */
  39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  40
  41 void
  42 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
  43 {
  44         rxq_info->state |= SFC_RXQ_FLUSHED;
  45         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  46 }
  47
  48 void
  49 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
  50 {
  51         rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
  52         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  53 }
  54
  55 static int
  56 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq)
  57 {
  58         int rc = 0;
  59
  60         if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) {
  61                 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr);
  62                 if (rc == 0)
  63                         rxq->evq->read_ptr_primed = rxq->evq->read_ptr;
  64         }
  65         return rc;
  66 }
  67
  68 static void
  69 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  70 {
  71         unsigned int free_space;
  72         unsigned int bulks;
  73         void *objs[SFC_RX_REFILL_BULK];
  74         efsys_dma_addr_t addr[RTE_DIM(objs)];
  75         unsigned int added = rxq->added;
  76         unsigned int id;
  77         unsigned int i;
  78         struct sfc_efx_rx_sw_desc *rxd;
  79         struct rte_mbuf *m;
  80         uint16_t port_id = rxq->dp.dpq.port_id;
  81
  82         free_space = rxq->max_fill_level - (added - rxq->completed);
  83
  84         if (free_space < rxq->refill_threshold)
  85                 return;
  86
  87         bulks = free_space / RTE_DIM(objs);
  88         /* refill_threshold guarantees that bulks is positive */
  89         SFC_ASSERT(bulks > 0);
  90
  91         id = added & rxq->ptr_mask;
  92         do {
  93                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
  94                                                   RTE_DIM(objs)) < 0)) {
  95                         /*
  96                          * It is hardly a safe way to increment counter
  97                          * from different contexts, but all PMDs do it.
  98                          */
  99                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
 100                                 RTE_DIM(objs);
 101                         /* Return if we have posted nothing yet */
 102                         if (added == rxq->added)
 103                                 return;
 104                         /* Push posted */
 105                         break;
 106                 }
 107
 108                 for (i = 0; i < RTE_DIM(objs);
 109                      ++i, id = (id + 1) & rxq->ptr_mask) {
 110                         m = objs[i];
 111
 112                         MBUF_RAW_ALLOC_CHECK(m);
 113
 114                         rxd = &rxq->sw_desc[id];
 115                         rxd->mbuf = m;
 116
 117                         m->data_off = RTE_PKTMBUF_HEADROOM;
 118                         m->port = port_id;
 119
 120                         addr[i] = rte_pktmbuf_iova(m);
 121                 }
 122
 123                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 124                              RTE_DIM(objs), rxq->completed, added);
 125                 added += RTE_DIM(objs);
 126         } while (--bulks > 0);
 127
 128         SFC_ASSERT(added != rxq->added);
 129         rxq->added = added;
 130         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 131 }
 132
 133 static uint64_t
 134 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 135 {
 136         uint64_t mbuf_flags = 0;
 137
 138         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 139         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 140                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 141                 break;
 142         case EFX_PKT_IPV4:
 143                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 144                 break;
 145         default:
 146                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 147                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 148                            PKT_RX_IP_CKSUM_UNKNOWN);
 149                 break;
 150         }
 151
 152         switch ((desc_flags &
 153                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 154         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 155         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 156                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 157                 break;
 158         case EFX_PKT_TCP:
 159         case EFX_PKT_UDP:
 160                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 161                 break;
 162         default:
 163                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 164                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 165                            PKT_RX_L4_CKSUM_UNKNOWN);
 166                 break;
 167         }
 168
 169         return mbuf_flags;
 170 }
 171
 172 static uint32_t
 173 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 174 {
 175         return RTE_PTYPE_L2_ETHER |
 176                 ((desc_flags & EFX_PKT_IPV4) ?
 177                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 178                 ((desc_flags & EFX_PKT_IPV6) ?
 179                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 180                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 181                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 182 }
 183
 184 static const uint32_t *
 185 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 186 {
 187         static const uint32_t ptypes[] = {
 188                 RTE_PTYPE_L2_ETHER,
 189                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 190                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 191                 RTE_PTYPE_L4_TCP,
 192                 RTE_PTYPE_L4_UDP,
 193                 RTE_PTYPE_UNKNOWN
 194         };
 195
 196         return ptypes;
 197 }
 198
 199 static void
 200 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 201                         struct rte_mbuf *m)
 202 {
 203         uint8_t *mbuf_data;
 204
 205
 206         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 207                 return;
 208
 209         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 210
 211         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 212                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 213                                                       EFX_RX_HASHALG_TOEPLITZ,
 214                                                       mbuf_data);
 215
 216                 m->ol_flags |= PKT_RX_RSS_HASH;
 217         }
 218 }
 219
 220 static uint16_t
 221 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 222 {
 223         struct sfc_dp_rxq *dp_rxq = rx_queue;
 224         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 225         unsigned int completed;
 226         unsigned int prefix_size = rxq->prefix_size;
 227         unsigned int done_pkts = 0;
 228         boolean_t discard_next = B_FALSE;
 229         struct rte_mbuf *scatter_pkt = NULL;
 230
 231         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 232                 return 0;
 233
 234         sfc_ev_qpoll(rxq->evq);
 235
 236         completed = rxq->completed;
 237         while (completed != rxq->pending && done_pkts < nb_pkts) {
 238                 unsigned int id;
 239                 struct sfc_efx_rx_sw_desc *rxd;
 240                 struct rte_mbuf *m;
 241                 unsigned int seg_len;
 242                 unsigned int desc_flags;
 243
 244                 id = completed++ & rxq->ptr_mask;
 245                 rxd = &rxq->sw_desc[id];
 246                 m = rxd->mbuf;
 247                 desc_flags = rxd->flags;
 248
 249                 if (discard_next)
 250                         goto discard;
 251
 252                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 253                         goto discard;
 254
 255                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 256                         uint16_t tmp_size;
 257                         int rc __rte_unused;
 258
 259                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 260                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 261                         SFC_ASSERT(rc == 0);
 262                         seg_len = tmp_size;
 263                 } else {
 264                         seg_len = rxd->size - prefix_size;
 265                 }
 266
 267                 rte_pktmbuf_data_len(m) = seg_len;
 268                 rte_pktmbuf_pkt_len(m) = seg_len;
 269
 270                 if (scatter_pkt != NULL) {
 271                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 272                                 rte_pktmbuf_free(scatter_pkt);
 273                                 goto discard;
 274                         }
 275                         /* The packet to deliver */
 276                         m = scatter_pkt;
 277                 }
 278
 279                 if (desc_flags & EFX_PKT_CONT) {
 280                         /* The packet is scattered, more fragments to come */
 281                         scatter_pkt = m;
 282                         /* Further fragments have no prefix */
 283                         prefix_size = 0;
 284                         continue;
 285                 }
 286
 287                 /* Scattered packet is done */
 288                 scatter_pkt = NULL;
 289                 /* The first fragment of the packet has prefix */
 290                 prefix_size = rxq->prefix_size;
 291
 292                 m->ol_flags =
 293                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 294                 m->packet_type =
 295                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 296
 297                 /*
 298                  * Extract RSS hash from the packet prefix and
 299                  * set the corresponding field (if needed and possible)
 300                  */
 301                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 302
 303                 m->data_off += prefix_size;
 304
 305                 *rx_pkts++ = m;
 306                 done_pkts++;
 307                 continue;
 308
 309 discard:
 310                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 311                 rte_mbuf_raw_free(m);
 312                 rxd->mbuf = NULL;
 313         }
 314
 315         /* pending is only moved when entire packet is received */
 316         SFC_ASSERT(scatter_pkt == NULL);
 317
 318         rxq->completed = completed;
 319
 320         sfc_efx_rx_qrefill(rxq);
 321
 322         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN)
 323                 sfc_efx_rx_qprime(rxq);
 324
 325         return done_pkts;
 326 }
 327
 328 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 329 static unsigned int
 330 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 331 {
 332         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 333
 334         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 335                 return 0;
 336
 337         sfc_ev_qpoll(rxq->evq);
 338
 339         return rxq->pending - rxq->completed;
 340 }
 341
 342 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 343 static int
 344 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 345 {
 346         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 347
 348         if (unlikely(offset > rxq->ptr_mask))
 349                 return -EINVAL;
 350
 351         /*
 352          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 353          * it is required for the queue to be running, but the
 354          * check is omitted because API design assumes that it
 355          * is the duty of the caller to satisfy all conditions
 356          */
 357         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 358                    SFC_EFX_RXQ_FLAG_RUNNING);
 359         sfc_ev_qpoll(rxq->evq);
 360
 361         /*
 362          * There is a handful of reserved entries in the ring,
 363          * but an explicit check whether the offset points to
 364          * a reserved entry is neglected since the two checks
 365          * below rely on the figures which take the HW limits
 366          * into account and thus if an entry is reserved, the
 367          * checks will fail and UNAVAIL code will be returned
 368          */
 369
 370         if (offset < (rxq->pending - rxq->completed))
 371                 return RTE_ETH_RX_DESC_DONE;
 372
 373         if (offset < (rxq->added - rxq->completed))
 374                 return RTE_ETH_RX_DESC_AVAIL;
 375
 376         return RTE_ETH_RX_DESC_UNAVAIL;
 377 }
 378
 379 boolean_t
 380 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size,
 381                      boolean_t rx_scatter_enabled, uint32_t rx_scatter_max,
 382                      const char **error)
 383 {
 384         uint32_t effective_rx_scatter_max;
 385         uint32_t rx_scatter_bufs;
 386
 387         effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1;
 388         rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size);
 389
 390         if (rx_scatter_bufs > effective_rx_scatter_max) {
 391                 if (rx_scatter_enabled)
 392                         *error = "Possible number of Rx scatter buffers exceeds maximum number";
 393                 else
 394                         *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small";
 395                 return B_FALSE;
 396         }
 397
 398         return B_TRUE;
 399 }
 400
 401 /** Get Rx datapath ops by the datapath RxQ handle */
 402 const struct sfc_dp_rx *
 403 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 404 {
 405         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 406         struct rte_eth_dev *eth_dev;
 407         struct sfc_adapter_priv *sap;
 408
 409         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 410         eth_dev = &rte_eth_devices[dpq->port_id];
 411
 412         sap = sfc_adapter_priv_by_eth_dev(eth_dev);
 413
 414         return sap->dp_rx;
 415 }
 416
 417 struct sfc_rxq_info *
 418 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 419 {
 420         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 421         struct rte_eth_dev *eth_dev;
 422         struct sfc_adapter_shared *sas;
 423
 424         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 425         eth_dev = &rte_eth_devices[dpq->port_id];
 426
 427         sas = sfc_adapter_shared_by_eth_dev(eth_dev);
 428
 429         SFC_ASSERT(dpq->queue_id < sas->rxq_count);
 430         return &sas->rxq_info[dpq->queue_id];
 431 }
 432
 433 struct sfc_rxq *
 434 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 435 {
 436         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 437         struct rte_eth_dev *eth_dev;
 438         struct sfc_adapter *sa;
 439
 440         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 441         eth_dev = &rte_eth_devices[dpq->port_id];
 442
 443         sa = sfc_adapter_by_eth_dev(eth_dev);
 444
 445         SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count);
 446         return &sa->rxq_ctrl[dpq->queue_id];
 447 }
 448
 449 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 450 static int
 451 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 452                           __rte_unused struct sfc_dp_rx_hw_limits *limits,
 453                           __rte_unused struct rte_mempool *mb_pool,
 454                           unsigned int *rxq_entries,
 455                           unsigned int *evq_entries,
 456                           unsigned int *rxq_max_fill_level)
 457 {
 458         *rxq_entries = nb_rx_desc;
 459         *evq_entries = nb_rx_desc;
 460         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 461         return 0;
 462 }
 463
 464 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 465 static int
 466 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 467                    const struct rte_pci_addr *pci_addr, int socket_id,
 468                    const struct sfc_dp_rx_qcreate_info *info,
 469                    struct sfc_dp_rxq **dp_rxqp)
 470 {
 471         struct sfc_efx_rxq *rxq;
 472         int rc;
 473
 474         rc = ENOMEM;
 475         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 476                                  RTE_CACHE_LINE_SIZE, socket_id);
 477         if (rxq == NULL)
 478                 goto fail_rxq_alloc;
 479
 480         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 481
 482         rc = ENOMEM;
 483         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 484                                          info->rxq_entries,
 485                                          sizeof(*rxq->sw_desc),
 486                                          RTE_CACHE_LINE_SIZE, socket_id);
 487         if (rxq->sw_desc == NULL)
 488                 goto fail_desc_alloc;
 489
 490         /* efx datapath is bound to efx control path */
 491         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 492         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 493                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 494         rxq->ptr_mask = info->rxq_entries - 1;
 495         rxq->batch_max = info->batch_max;
 496         rxq->prefix_size = info->prefix_size;
 497         rxq->max_fill_level = info->max_fill_level;
 498         rxq->refill_threshold = info->refill_threshold;
 499         rxq->buf_size = info->buf_size;
 500         rxq->refill_mb_pool = info->refill_mb_pool;
 501
 502         *dp_rxqp = &rxq->dp;
 503         return 0;
 504
 505 fail_desc_alloc:
 506         rte_free(rxq);
 507
 508 fail_rxq_alloc:
 509         return rc;
 510 }
 511
 512 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 513 static void
 514 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 515 {
 516         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 517
 518         rte_free(rxq->sw_desc);
 519         rte_free(rxq);
 520 }
 521
 522
 523 /* Use qstop and qstart functions in the case of qstart failure */
 524 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 525 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 526
 527
 528 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 529 static int
 530 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 531                   __rte_unused unsigned int evq_read_ptr)
 532 {
 533         /* libefx-based datapath is specific to libefx-based PMD */
 534         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 535         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 536         int rc;
 537
 538         rxq->common = crxq->common;
 539
 540         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 541
 542         sfc_efx_rx_qrefill(rxq);
 543
 544         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 545
 546         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) {
 547                 rc = sfc_efx_rx_qprime(rxq);
 548                 if (rc != 0)
 549                         goto fail_rx_qprime;
 550         }
 551
 552         return 0;
 553
 554 fail_rx_qprime:
 555         sfc_efx_rx_qstop(dp_rxq, NULL);
 556         sfc_efx_rx_qpurge(dp_rxq);
 557         return rc;
 558 }
 559
 560 static void
 561 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 562                  __rte_unused unsigned int *evq_read_ptr)
 563 {
 564         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 565
 566         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 567
 568         /* libefx-based datapath is bound to libefx-based PMD and uses
 569          * event queue structure directly. So, there is no necessity to
 570          * return EvQ read pointer.
 571          */
 572 }
 573
 574 static void
 575 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 576 {
 577         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 578         unsigned int i;
 579         struct sfc_efx_rx_sw_desc *rxd;
 580
 581         for (i = rxq->completed; i != rxq->added; ++i) {
 582                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 583                 rte_mbuf_raw_free(rxd->mbuf);
 584                 rxd->mbuf = NULL;
 585                 /* Packed stream relies on 0 in inactive SW desc.
 586                  * Rx queue stop is not performance critical, so
 587                  * there is no harm to do it always.
 588                  */
 589                 rxd->flags = 0;
 590                 rxd->size = 0;
 591         }
 592
 593         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 594 }
 595
 596 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable;
 597 static int
 598 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
 599 {
 600         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 601         int rc = 0;
 602
 603         rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN;
 604         if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) {
 605                 rc = sfc_efx_rx_qprime(rxq);
 606                 if (rc != 0)
 607                         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 608         }
 609         return rc;
 610 }
 611
 612 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable;
 613 static int
 614 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
 615 {
 616         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 617
 618         /* Cannot disarm, just disable rearm */
 619         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 620         return 0;
 621 }
 622
 623 struct sfc_dp_rx sfc_efx_rx = {
 624         .dp = {
 625                 .name           = SFC_KVARG_DATAPATH_EFX,
 626                 .type           = SFC_DP_RX,
 627                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_RX_EFX,
 628         },
 629         .features               = SFC_DP_RX_FEAT_INTR,
 630         .dev_offload_capa       = DEV_RX_OFFLOAD_CHECKSUM |
 631                                   DEV_RX_OFFLOAD_RSS_HASH,
 632         .queue_offload_capa     = DEV_RX_OFFLOAD_SCATTER,
 633         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 634         .qcreate                = sfc_efx_rx_qcreate,
 635         .qdestroy               = sfc_efx_rx_qdestroy,
 636         .qstart                 = sfc_efx_rx_qstart,
 637         .qstop                  = sfc_efx_rx_qstop,
 638         .qpurge                 = sfc_efx_rx_qpurge,
 639         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 640         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 641         .qdesc_status           = sfc_efx_rx_qdesc_status,
 642         .intr_enable            = sfc_efx_rx_intr_enable,
 643         .intr_disable           = sfc_efx_rx_intr_disable,
 644         .pkt_burst              = sfc_efx_recv_pkts,
 645 };
 646
 647 static void
 648 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
 649 {
 650         struct sfc_rxq_info *rxq_info;
 651         struct sfc_rxq *rxq;
 652         unsigned int retry_count;
 653         unsigned int wait_count;
 654         int rc;
 655
 656         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 657         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 658
 659         rxq = &sa->rxq_ctrl[sw_index];
 660
 661         /*
 662          * Retry Rx queue flushing in the case of flush failed or
 663          * timeout. In the worst case it can delay for 6 seconds.
 664          */
 665         for (retry_count = 0;
 666              ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
 667              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 668              ++retry_count) {
 669                 rc = efx_rx_qflush(rxq->common);
 670                 if (rc != 0) {
 671                         rxq_info->state |= (rc == EALREADY) ?
 672                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 673                         break;
 674                 }
 675                 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
 676                 rxq_info->state |= SFC_RXQ_FLUSHING;
 677
 678                 /*
 679                  * Wait for Rx queue flush done or failed event at least
 680                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 681                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 682                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 683                  */
 684                 wait_count = 0;
 685                 do {
 686                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 687                         sfc_ev_qpoll(rxq->evq);
 688                 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
 689                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 690
 691                 if (rxq_info->state & SFC_RXQ_FLUSHING)
 692                         sfc_err(sa, "RxQ %u flush timed out", sw_index);
 693
 694                 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
 695                         sfc_err(sa, "RxQ %u flush failed", sw_index);
 696
 697                 if (rxq_info->state & SFC_RXQ_FLUSHED)
 698                         sfc_notice(sa, "RxQ %u flushed", sw_index);
 699         }
 700
 701         sa->priv.dp_rx->qpurge(rxq_info->dp);
 702 }
 703
 704 static int
 705 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 706 {
 707         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
 708         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 709         struct sfc_port *port = &sa->port;
 710         int rc;
 711
 712         /*
 713          * If promiscuous or all-multicast mode has been requested, setting
 714          * filter for the default Rx queue might fail, in particular, while
 715          * running over PCI function which is not a member of corresponding
 716          * privilege groups; if this occurs, few iterations will be made to
 717          * repeat this step without promiscuous and all-multicast flags set
 718          */
 719 retry:
 720         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 721         if (rc == 0)
 722                 return 0;
 723         else if (rc != EOPNOTSUPP)
 724                 return rc;
 725
 726         if (port->promisc) {
 727                 sfc_warn(sa, "promiscuous mode has been requested, "
 728                              "but the HW rejects it");
 729                 sfc_warn(sa, "promiscuous mode will be disabled");
 730
 731                 port->promisc = B_FALSE;
 732                 sa->eth_dev->data->promiscuous = 0;
 733                 rc = sfc_set_rx_mode_unchecked(sa);
 734                 if (rc != 0)
 735                         return rc;
 736
 737                 goto retry;
 738         }
 739
 740         if (port->allmulti) {
 741                 sfc_warn(sa, "all-multicast mode has been requested, "
 742                              "but the HW rejects it");
 743                 sfc_warn(sa, "all-multicast mode will be disabled");
 744
 745                 port->allmulti = B_FALSE;
 746                 sa->eth_dev->data->all_multicast = 0;
 747                 rc = sfc_set_rx_mode_unchecked(sa);
 748                 if (rc != 0)
 749                         return rc;
 750
 751                 goto retry;
 752         }
 753
 754         return rc;
 755 }
 756
 757 int
 758 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
 759 {
 760         struct sfc_rxq_info *rxq_info;
 761         struct sfc_rxq *rxq;
 762         struct sfc_evq *evq;
 763         int rc;
 764
 765         sfc_log_init(sa, "sw_index=%u", sw_index);
 766
 767         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 768
 769         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 770         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
 771
 772         rxq = &sa->rxq_ctrl[sw_index];
 773         evq = rxq->evq;
 774
 775         rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
 776         if (rc != 0)
 777                 goto fail_ev_qstart;
 778
 779         switch (rxq_info->type) {
 780         case EFX_RXQ_TYPE_DEFAULT:
 781                 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 782                         rxq->buf_size,
 783                         &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
 784                         rxq_info->type_flags, evq->common, &rxq->common);
 785                 break;
 786         case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
 787                 struct rte_mempool *mp = rxq_info->refill_mb_pool;
 788                 struct rte_mempool_info mp_info;
 789
 790                 rc = rte_mempool_ops_get_info(mp, &mp_info);
 791                 if (rc != 0) {
 792                         /* Positive errno is used in the driver */
 793                         rc = -rc;
 794                         goto fail_mp_get_info;
 795                 }
 796                 if (mp_info.contig_block_size <= 0) {
 797                         rc = EINVAL;
 798                         goto fail_bad_contig_block_size;
 799                 }
 800                 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
 801                         mp_info.contig_block_size, rxq->buf_size,
 802                         mp->header_size + mp->elt_size + mp->trailer_size,
 803                         sa->rxd_wait_timeout_ns,
 804                         &rxq->mem, rxq_info->entries, rxq_info->type_flags,
 805                         evq->common, &rxq->common);
 806                 break;
 807         }
 808         default:
 809                 rc = ENOTSUP;
 810         }
 811         if (rc != 0)
 812                 goto fail_rx_qcreate;
 813
 814         efx_rx_qenable(rxq->common);
 815
 816         rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr);
 817         if (rc != 0)
 818                 goto fail_dp_qstart;
 819
 820         rxq_info->state |= SFC_RXQ_STARTED;
 821
 822         if (sw_index == 0 && !sfc_sa2shared(sa)->isolated) {
 823                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 824                 if (rc != 0)
 825                         goto fail_mac_filter_default_rxq_set;
 826         }
 827
 828         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 829         sa->eth_dev->data->rx_queue_state[sw_index] =
 830                 RTE_ETH_QUEUE_STATE_STARTED;
 831
 832         return 0;
 833
 834 fail_mac_filter_default_rxq_set:
 835         sfc_rx_qflush(sa, sw_index);
 836         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 837         rxq_info->state = SFC_RXQ_INITIALIZED;
 838
 839 fail_dp_qstart:
 840         efx_rx_qdestroy(rxq->common);
 841
 842 fail_rx_qcreate:
 843 fail_bad_contig_block_size:
 844 fail_mp_get_info:
 845         sfc_ev_qstop(evq);
 846
 847 fail_ev_qstart:
 848         return rc;
 849 }
 850
 851 void
 852 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
 853 {
 854         struct sfc_rxq_info *rxq_info;
 855         struct sfc_rxq *rxq;
 856
 857         sfc_log_init(sa, "sw_index=%u", sw_index);
 858
 859         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 860
 861         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 862
 863         if (rxq_info->state == SFC_RXQ_INITIALIZED)
 864                 return;
 865         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 866
 867         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 868         sa->eth_dev->data->rx_queue_state[sw_index] =
 869                 RTE_ETH_QUEUE_STATE_STOPPED;
 870
 871         rxq = &sa->rxq_ctrl[sw_index];
 872         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 873
 874         if (sw_index == 0)
 875                 efx_mac_filter_default_rxq_clear(sa->nic);
 876
 877         sfc_rx_qflush(sa, sw_index);
 878
 879         rxq_info->state = SFC_RXQ_INITIALIZED;
 880
 881         efx_rx_qdestroy(rxq->common);
 882
 883         sfc_ev_qstop(rxq->evq);
 884 }
 885
 886 static uint64_t
 887 sfc_rx_get_offload_mask(struct sfc_adapter *sa)
 888 {
 889         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 890         uint64_t no_caps = 0;
 891
 892         if (encp->enc_tunnel_encapsulations_supported == 0)
 893                 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 894
 895         return ~no_caps;
 896 }
 897
 898 uint64_t
 899 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 900 {
 901         uint64_t caps = sa->priv.dp_rx->dev_offload_capa;
 902
 903         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 904
 905         return caps & sfc_rx_get_offload_mask(sa);
 906 }
 907
 908 uint64_t
 909 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 910 {
 911         return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa);
 912 }
 913
 914 static int
 915 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 916                    const struct rte_eth_rxconf *rx_conf,
 917                    __rte_unused uint64_t offloads)
 918 {
 919         int rc = 0;
 920
 921         if (rx_conf->rx_thresh.pthresh != 0 ||
 922             rx_conf->rx_thresh.hthresh != 0 ||
 923             rx_conf->rx_thresh.wthresh != 0) {
 924                 sfc_warn(sa,
 925                         "RxQ prefetch/host/writeback thresholds are not supported");
 926         }
 927
 928         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 929                 sfc_err(sa,
 930                         "RxQ free threshold too large: %u vs maximum %u",
 931                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 932                 rc = EINVAL;
 933         }
 934
 935         if (rx_conf->rx_drop_en == 0) {
 936                 sfc_err(sa, "RxQ drop disable is not supported");
 937                 rc = EINVAL;
 938         }
 939
 940         return rc;
 941 }
 942
 943 static unsigned int
 944 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 945 {
 946         uint32_t data_off;
 947         uint32_t order;
 948
 949         /* The mbuf object itself is always cache line aligned */
 950         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 951
 952         /* Data offset from mbuf object start */
 953         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 954                 RTE_PKTMBUF_HEADROOM;
 955
 956         order = MIN(order, rte_bsf32(data_off));
 957
 958         return 1u << order;
 959 }
 960
 961 static uint16_t
 962 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
 963 {
 964         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 965         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
 966         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
 967         uint16_t buf_size;
 968         unsigned int buf_aligned;
 969         unsigned int start_alignment;
 970         unsigned int end_padding_alignment;
 971
 972         /* Below it is assumed that both alignments are power of 2 */
 973         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
 974         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
 975
 976         /*
 977          * mbuf is always cache line aligned, double-check
 978          * that it meets rx buffer start alignment requirements.
 979          */
 980
 981         /* Start from mbuf pool data room size */
 982         buf_size = rte_pktmbuf_data_room_size(mb_pool);
 983
 984         /* Remove headroom */
 985         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
 986                 sfc_err(sa,
 987                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
 988                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
 989                 return 0;
 990         }
 991         buf_size -= RTE_PKTMBUF_HEADROOM;
 992
 993         /* Calculate guaranteed data start alignment */
 994         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
 995
 996         /* Reserve space for start alignment */
 997         if (buf_aligned < nic_align_start) {
 998                 start_alignment = nic_align_start - buf_aligned;
 999                 if (buf_size <= start_alignment) {
1000                         sfc_err(sa,
1001                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
1002                                 mb_pool->name,
1003                                 rte_pktmbuf_data_room_size(mb_pool),
1004                                 RTE_PKTMBUF_HEADROOM, start_alignment);
1005                         return 0;
1006                 }
1007                 buf_aligned = nic_align_start;
1008                 buf_size -= start_alignment;
1009         } else {
1010                 start_alignment = 0;
1011         }
1012
1013         /* Make sure that end padding does not write beyond the buffer */
1014         if (buf_aligned < nic_align_end) {
1015                 /*
1016                  * Estimate space which can be lost. If guarnteed buffer
1017                  * size is odd, lost space is (nic_align_end - 1). More
1018                  * accurate formula is below.
1019                  */
1020                 end_padding_alignment = nic_align_end -
1021                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
1022                 if (buf_size <= end_padding_alignment) {
1023                         sfc_err(sa,
1024                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
1025                                 mb_pool->name,
1026                                 rte_pktmbuf_data_room_size(mb_pool),
1027                                 RTE_PKTMBUF_HEADROOM, start_alignment,
1028                                 end_padding_alignment);
1029                         return 0;
1030                 }
1031                 buf_size -= end_padding_alignment;
1032         } else {
1033                 /*
1034                  * Start is aligned the same or better than end,
1035                  * just align length.
1036                  */
1037                 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end);
1038         }
1039
1040         return buf_size;
1041 }
1042
1043 int
1044 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
1045              uint16_t nb_rx_desc, unsigned int socket_id,
1046              const struct rte_eth_rxconf *rx_conf,
1047              struct rte_mempool *mb_pool)
1048 {
1049         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1050         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1051         int rc;
1052         unsigned int rxq_entries;
1053         unsigned int evq_entries;
1054         unsigned int rxq_max_fill_level;
1055         uint64_t offloads;
1056         uint16_t buf_size;
1057         struct sfc_rxq_info *rxq_info;
1058         struct sfc_evq *evq;
1059         struct sfc_rxq *rxq;
1060         struct sfc_dp_rx_qcreate_info info;
1061         struct sfc_dp_rx_hw_limits hw_limits;
1062         uint16_t rx_free_thresh;
1063         const char *error;
1064
1065         memset(&hw_limits, 0, sizeof(hw_limits));
1066         hw_limits.rxq_max_entries = sa->rxq_max_entries;
1067         hw_limits.rxq_min_entries = sa->rxq_min_entries;
1068         hw_limits.evq_max_entries = sa->evq_max_entries;
1069         hw_limits.evq_min_entries = sa->evq_min_entries;
1070
1071         rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool,
1072                                             &rxq_entries, &evq_entries,
1073                                             &rxq_max_fill_level);
1074         if (rc != 0)
1075                 goto fail_size_up_rings;
1076         SFC_ASSERT(rxq_entries >= sa->rxq_min_entries);
1077         SFC_ASSERT(rxq_entries <= sa->rxq_max_entries);
1078         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
1079
1080         offloads = rx_conf->offloads |
1081                 sa->eth_dev->data->dev_conf.rxmode.offloads;
1082         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
1083         if (rc != 0)
1084                 goto fail_bad_conf;
1085
1086         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1087         if (buf_size == 0) {
1088                 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
1089                         sw_index);
1090                 rc = EINVAL;
1091                 goto fail_bad_conf;
1092         }
1093
1094         if (!sfc_rx_check_scatter(sa->port.pdu, buf_size,
1095                                   encp->enc_rx_prefix_size,
1096                                   (offloads & DEV_RX_OFFLOAD_SCATTER),
1097                                   encp->enc_rx_scatter_max,
1098                                   &error)) {
1099                 sfc_err(sa, "RxQ %u MTU check failed: %s", sw_index, error);
1100                 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
1101                         "PDU size %u plus Rx prefix %u bytes",
1102                         sw_index, buf_size, (unsigned int)sa->port.pdu,
1103                         encp->enc_rx_prefix_size);
1104                 rc = EINVAL;
1105                 goto fail_bad_conf;
1106         }
1107
1108         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1109         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1110
1111         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1112         rxq_info->entries = rxq_entries;
1113
1114         if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1115                 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1116         else
1117                 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1118
1119         rxq_info->type_flags =
1120                 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1121                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1122
1123         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1124             (sfc_dp_rx_offload_capa(sa->priv.dp_rx) &
1125              DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0)
1126                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1127
1128         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1129                           evq_entries, socket_id, &evq);
1130         if (rc != 0)
1131                 goto fail_ev_qinit;
1132
1133         rxq = &sa->rxq_ctrl[sw_index];
1134         rxq->evq = evq;
1135         rxq->hw_index = sw_index;
1136         /*
1137          * If Rx refill threshold is specified (its value is non zero) in
1138          * Rx configuration, use specified value. Otherwise use 1/8 of
1139          * the Rx descriptors number as the default. It allows to keep
1140          * Rx ring full-enough and does not refill too aggressive if
1141          * packet rate is high.
1142          *
1143          * Since PMD refills in bulks waiting for full bulk may be
1144          * refilled (basically round down), it is better to round up
1145          * here to mitigate it a bit.
1146          */
1147         rx_free_thresh = (rx_conf->rx_free_thresh != 0) ?
1148                 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8);
1149         /* Rx refill threshold cannot be smaller than refill bulk */
1150         rxq_info->refill_threshold =
1151                 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK);
1152         rxq_info->refill_mb_pool = mb_pool;
1153
1154         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 &&
1155             (offloads & DEV_RX_OFFLOAD_RSS_HASH))
1156                 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH;
1157         else
1158                 rxq_info->rxq_flags = 0;
1159
1160         rxq->buf_size = buf_size;
1161
1162         rc = sfc_dma_alloc(sa, "rxq", sw_index,
1163                            efx_rxq_size(sa->nic, rxq_info->entries),
1164                            socket_id, &rxq->mem);
1165         if (rc != 0)
1166                 goto fail_dma_alloc;
1167
1168         memset(&info, 0, sizeof(info));
1169         info.refill_mb_pool = rxq_info->refill_mb_pool;
1170         info.max_fill_level = rxq_max_fill_level;
1171         info.refill_threshold = rxq_info->refill_threshold;
1172         info.buf_size = buf_size;
1173         info.batch_max = encp->enc_rx_batch_max;
1174         info.prefix_size = encp->enc_rx_prefix_size;
1175         info.flags = rxq_info->rxq_flags;
1176         info.rxq_entries = rxq_info->entries;
1177         info.rxq_hw_ring = rxq->mem.esm_base;
1178         info.evq_hw_index = sfc_evq_index_by_rxq_sw_index(sa, sw_index);
1179         info.evq_entries = evq_entries;
1180         info.evq_hw_ring = evq->mem.esm_base;
1181         info.hw_index = rxq->hw_index;
1182         info.mem_bar = sa->mem_bar.esb_base;
1183         info.vi_window_shift = encp->enc_vi_window_shift;
1184
1185         rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1186                                      &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1187                                      socket_id, &info, &rxq_info->dp);
1188         if (rc != 0)
1189                 goto fail_dp_rx_qcreate;
1190
1191         evq->dp_rxq = rxq_info->dp;
1192
1193         rxq_info->state = SFC_RXQ_INITIALIZED;
1194
1195         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1196
1197         return 0;
1198
1199 fail_dp_rx_qcreate:
1200         sfc_dma_free(sa, &rxq->mem);
1201
1202 fail_dma_alloc:
1203         sfc_ev_qfini(evq);
1204
1205 fail_ev_qinit:
1206         rxq_info->entries = 0;
1207
1208 fail_bad_conf:
1209 fail_size_up_rings:
1210         sfc_log_init(sa, "failed %d", rc);
1211         return rc;
1212 }
1213
1214 void
1215 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
1216 {
1217         struct sfc_rxq_info *rxq_info;
1218         struct sfc_rxq *rxq;
1219
1220         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1221         sa->eth_dev->data->rx_queues[sw_index] = NULL;
1222
1223         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1224
1225         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1226
1227         sa->priv.dp_rx->qdestroy(rxq_info->dp);
1228         rxq_info->dp = NULL;
1229
1230         rxq_info->state &= ~SFC_RXQ_INITIALIZED;
1231         rxq_info->entries = 0;
1232
1233         rxq = &sa->rxq_ctrl[sw_index];
1234
1235         sfc_dma_free(sa, &rxq->mem);
1236
1237         sfc_ev_qfini(rxq->evq);
1238         rxq->evq = NULL;
1239 }
1240
1241 /*
1242  * Mapping between RTE RSS hash functions and their EFX counterparts.
1243  */
1244 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1245         { ETH_RSS_NONFRAG_IPV4_TCP,
1246           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1247         { ETH_RSS_NONFRAG_IPV4_UDP,
1248           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1249         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1250           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1251         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1252           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1253         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1254           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1255           EFX_RX_HASH(IPV4, 2TUPLE) },
1256         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1257           ETH_RSS_IPV6_EX,
1258           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1259           EFX_RX_HASH(IPV6, 2TUPLE) }
1260 };
1261
1262 static efx_rx_hash_type_t
1263 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1264                             unsigned int *hash_type_flags_supported,
1265                             unsigned int nb_hash_type_flags_supported)
1266 {
1267         efx_rx_hash_type_t hash_type_masked = 0;
1268         unsigned int i, j;
1269
1270         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1271                 unsigned int class_tuple_lbn[] = {
1272                         EFX_RX_CLASS_IPV4_TCP_LBN,
1273                         EFX_RX_CLASS_IPV4_UDP_LBN,
1274                         EFX_RX_CLASS_IPV4_LBN,
1275                         EFX_RX_CLASS_IPV6_TCP_LBN,
1276                         EFX_RX_CLASS_IPV6_UDP_LBN,
1277                         EFX_RX_CLASS_IPV6_LBN
1278                 };
1279
1280                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1281                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1282                         unsigned int flag;
1283
1284                         tuple_mask <<= class_tuple_lbn[j];
1285                         flag = hash_type & tuple_mask;
1286
1287                         if (flag == hash_type_flags_supported[i])
1288                                 hash_type_masked |= flag;
1289                 }
1290         }
1291
1292         return hash_type_masked;
1293 }
1294
1295 int
1296 sfc_rx_hash_init(struct sfc_adapter *sa)
1297 {
1298         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1299         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1300         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1301         efx_rx_hash_alg_t alg;
1302         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1303         unsigned int nb_flags_supp;
1304         struct sfc_rss_hf_rte_to_efx *hf_map;
1305         struct sfc_rss_hf_rte_to_efx *entry;
1306         efx_rx_hash_type_t efx_hash_types;
1307         unsigned int i;
1308         int rc;
1309
1310         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1311                 alg = EFX_RX_HASHALG_TOEPLITZ;
1312         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1313                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1314         else
1315                 return EINVAL;
1316
1317         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1318                                          RTE_DIM(flags_supp), &nb_flags_supp);
1319         if (rc != 0)
1320                 return rc;
1321
1322         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1323                                    RTE_DIM(sfc_rss_hf_map),
1324                                    sizeof(*hf_map), 0, sa->socket_id);
1325         if (hf_map == NULL)
1326                 return ENOMEM;
1327
1328         entry = hf_map;
1329         efx_hash_types = 0;
1330         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1331                 efx_rx_hash_type_t ht;
1332
1333                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1334                                                  flags_supp, nb_flags_supp);
1335                 if (ht != 0) {
1336                         entry->rte = sfc_rss_hf_map[i].rte;
1337                         entry->efx = ht;
1338                         efx_hash_types |= ht;
1339                         ++entry;
1340                 }
1341         }
1342
1343         rss->hash_alg = alg;
1344         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1345         rss->hf_map = hf_map;
1346         rss->hash_types = efx_hash_types;
1347
1348         return 0;
1349 }
1350
1351 void
1352 sfc_rx_hash_fini(struct sfc_adapter *sa)
1353 {
1354         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1355
1356         rte_free(rss->hf_map);
1357 }
1358
1359 int
1360 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1361                      efx_rx_hash_type_t *efx)
1362 {
1363         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1364         efx_rx_hash_type_t hash_types = 0;
1365         unsigned int i;
1366
1367         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1368                 uint64_t rte_mask = rss->hf_map[i].rte;
1369
1370                 if ((rte & rte_mask) != 0) {
1371                         rte &= ~rte_mask;
1372                         hash_types |= rss->hf_map[i].efx;
1373                 }
1374         }
1375
1376         if (rte != 0) {
1377                 sfc_err(sa, "unsupported hash functions requested");
1378                 return EINVAL;
1379         }
1380
1381         *efx = hash_types;
1382
1383         return 0;
1384 }
1385
1386 uint64_t
1387 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx)
1388 {
1389         uint64_t rte = 0;
1390         unsigned int i;
1391
1392         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1393                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1394
1395                 if ((efx & hash_type) == hash_type)
1396                         rte |= rss->hf_map[i].rte;
1397         }
1398
1399         return rte;
1400 }
1401
1402 static int
1403 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1404                             struct rte_eth_rss_conf *conf)
1405 {
1406         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1407         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1408         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types);
1409         int rc;
1410
1411         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1412                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1413                     conf->rss_key != NULL)
1414                         return EINVAL;
1415         }
1416
1417         if (conf->rss_hf != 0) {
1418                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1419                 if (rc != 0)
1420                         return rc;
1421         }
1422
1423         if (conf->rss_key != NULL) {
1424                 if (conf->rss_key_len != sizeof(rss->key)) {
1425                         sfc_err(sa, "RSS key size is wrong (should be %zu)",
1426                                 sizeof(rss->key));
1427                         return EINVAL;
1428                 }
1429                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1430         }
1431
1432         rss->hash_types = efx_hash_types;
1433
1434         return 0;
1435 }
1436
1437 static int
1438 sfc_rx_rss_config(struct sfc_adapter *sa)
1439 {
1440         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1441         int rc = 0;
1442
1443         if (rss->channels > 0) {
1444                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1445                                            rss->hash_alg, rss->hash_types,
1446                                            B_TRUE);
1447                 if (rc != 0)
1448                         goto finish;
1449
1450                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1451                                           rss->key, sizeof(rss->key));
1452                 if (rc != 0)
1453                         goto finish;
1454
1455                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1456                                           rss->tbl, RTE_DIM(rss->tbl));
1457         }
1458
1459 finish:
1460         return rc;
1461 }
1462
1463 int
1464 sfc_rx_start(struct sfc_adapter *sa)
1465 {
1466         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1467         unsigned int sw_index;
1468         int rc;
1469
1470         sfc_log_init(sa, "rxq_count=%u", sas->rxq_count);
1471
1472         rc = efx_rx_init(sa->nic);
1473         if (rc != 0)
1474                 goto fail_rx_init;
1475
1476         rc = sfc_rx_rss_config(sa);
1477         if (rc != 0)
1478                 goto fail_rss_config;
1479
1480         for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) {
1481                 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED &&
1482                     (!sas->rxq_info[sw_index].deferred_start ||
1483                      sas->rxq_info[sw_index].deferred_started)) {
1484                         rc = sfc_rx_qstart(sa, sw_index);
1485                         if (rc != 0)
1486                                 goto fail_rx_qstart;
1487                 }
1488         }
1489
1490         return 0;
1491
1492 fail_rx_qstart:
1493         while (sw_index-- > 0)
1494                 sfc_rx_qstop(sa, sw_index);
1495
1496 fail_rss_config:
1497         efx_rx_fini(sa->nic);
1498
1499 fail_rx_init:
1500         sfc_log_init(sa, "failed %d", rc);
1501         return rc;
1502 }
1503
1504 void
1505 sfc_rx_stop(struct sfc_adapter *sa)
1506 {
1507         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1508         unsigned int sw_index;
1509
1510         sfc_log_init(sa, "rxq_count=%u", sas->rxq_count);
1511
1512         sw_index = sas->rxq_count;
1513         while (sw_index-- > 0) {
1514                 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED)
1515                         sfc_rx_qstop(sa, sw_index);
1516         }
1517
1518         efx_rx_fini(sa->nic);
1519 }
1520
1521 static int
1522 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1523 {
1524         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1525         struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index];
1526         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1527         unsigned int max_entries;
1528
1529         max_entries = encp->enc_rxq_max_ndescs;
1530         SFC_ASSERT(rte_is_power_of_2(max_entries));
1531
1532         rxq_info->max_entries = max_entries;
1533
1534         return 0;
1535 }
1536
1537 static int
1538 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1539 {
1540         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1541         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1542                                       sfc_rx_get_queue_offload_caps(sa);
1543         struct sfc_rss *rss = &sas->rss;
1544         int rc = 0;
1545
1546         switch (rxmode->mq_mode) {
1547         case ETH_MQ_RX_NONE:
1548                 /* No special checks are required */
1549                 break;
1550         case ETH_MQ_RX_RSS:
1551                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1552                         sfc_err(sa, "RSS is not available");
1553                         rc = EINVAL;
1554                 }
1555                 break;
1556         default:
1557                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1558                         rxmode->mq_mode);
1559                 rc = EINVAL;
1560         }
1561
1562         /*
1563          * Requested offloads are validated against supported by ethdev,
1564          * so unsupported offloads cannot be added as the result of
1565          * below check.
1566          */
1567         if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1568             (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1569                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1570                 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1571         }
1572
1573         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1574             (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1575                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1576                 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1577         }
1578
1579         return rc;
1580 }
1581
1582 /**
1583  * Destroy excess queues that are no longer needed after reconfiguration
1584  * or complete close.
1585  */
1586 static void
1587 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1588 {
1589         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1590         int sw_index;
1591
1592         SFC_ASSERT(nb_rx_queues <= sas->rxq_count);
1593
1594         sw_index = sas->rxq_count;
1595         while (--sw_index >= (int)nb_rx_queues) {
1596                 if (sas->rxq_info[sw_index].state & SFC_RXQ_INITIALIZED)
1597                         sfc_rx_qfini(sa, sw_index);
1598         }
1599
1600         sas->rxq_count = nb_rx_queues;
1601 }
1602
1603 /**
1604  * Initialize Rx subsystem.
1605  *
1606  * Called at device (re)configuration stage when number of receive queues is
1607  * specified together with other device level receive configuration.
1608  *
1609  * It should be used to allocate NUMA-unaware resources.
1610  */
1611 int
1612 sfc_rx_configure(struct sfc_adapter *sa)
1613 {
1614         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1615         struct sfc_rss *rss = &sas->rss;
1616         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1617         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1618         int rc;
1619
1620         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1621                      nb_rx_queues, sas->rxq_count);
1622
1623         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1624         if (rc != 0)
1625                 goto fail_check_mode;
1626
1627         if (nb_rx_queues == sas->rxq_count)
1628                 goto configure_rss;
1629
1630         if (sas->rxq_info == NULL) {
1631                 rc = ENOMEM;
1632                 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1633                                                   sizeof(sas->rxq_info[0]), 0,
1634                                                   sa->socket_id);
1635                 if (sas->rxq_info == NULL)
1636                         goto fail_rxqs_alloc;
1637
1638                 /*
1639                  * Allocate primary process only RxQ control from heap
1640                  * since it should not be shared.
1641                  */
1642                 rc = ENOMEM;
1643                 sa->rxq_ctrl = calloc(nb_rx_queues, sizeof(sa->rxq_ctrl[0]));
1644                 if (sa->rxq_ctrl == NULL)
1645                         goto fail_rxqs_ctrl_alloc;
1646         } else {
1647                 struct sfc_rxq_info *new_rxq_info;
1648                 struct sfc_rxq *new_rxq_ctrl;
1649
1650                 if (nb_rx_queues < sas->rxq_count)
1651                         sfc_rx_fini_queues(sa, nb_rx_queues);
1652
1653                 rc = ENOMEM;
1654                 new_rxq_info =
1655                         rte_realloc(sas->rxq_info,
1656                                     nb_rx_queues * sizeof(sas->rxq_info[0]), 0);
1657                 if (new_rxq_info == NULL && nb_rx_queues > 0)
1658                         goto fail_rxqs_realloc;
1659
1660                 rc = ENOMEM;
1661                 new_rxq_ctrl = realloc(sa->rxq_ctrl,
1662                                        nb_rx_queues * sizeof(sa->rxq_ctrl[0]));
1663                 if (new_rxq_ctrl == NULL && nb_rx_queues > 0)
1664                         goto fail_rxqs_ctrl_realloc;
1665
1666                 sas->rxq_info = new_rxq_info;
1667                 sa->rxq_ctrl = new_rxq_ctrl;
1668                 if (nb_rx_queues > sas->rxq_count) {
1669                         memset(&sas->rxq_info[sas->rxq_count], 0,
1670                                (nb_rx_queues - sas->rxq_count) *
1671                                sizeof(sas->rxq_info[0]));
1672                         memset(&sa->rxq_ctrl[sas->rxq_count], 0,
1673                                (nb_rx_queues - sas->rxq_count) *
1674                                sizeof(sa->rxq_ctrl[0]));
1675                 }
1676         }
1677
1678         while (sas->rxq_count < nb_rx_queues) {
1679                 rc = sfc_rx_qinit_info(sa, sas->rxq_count);
1680                 if (rc != 0)
1681                         goto fail_rx_qinit_info;
1682
1683                 sas->rxq_count++;
1684         }
1685
1686 configure_rss:
1687         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1688                          MIN(sas->rxq_count, EFX_MAXRSS) : 0;
1689
1690         if (rss->channels > 0) {
1691                 struct rte_eth_rss_conf *adv_conf_rss;
1692                 unsigned int sw_index;
1693
1694                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1695                         rss->tbl[sw_index] = sw_index % rss->channels;
1696
1697                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1698                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1699                 if (rc != 0)
1700                         goto fail_rx_process_adv_conf_rss;
1701         }
1702
1703         return 0;
1704
1705 fail_rx_process_adv_conf_rss:
1706 fail_rx_qinit_info:
1707 fail_rxqs_ctrl_realloc:
1708 fail_rxqs_realloc:
1709 fail_rxqs_ctrl_alloc:
1710 fail_rxqs_alloc:
1711         sfc_rx_close(sa);
1712
1713 fail_check_mode:
1714         sfc_log_init(sa, "failed %d", rc);
1715         return rc;
1716 }
1717
1718 /**
1719  * Shutdown Rx subsystem.
1720  *
1721  * Called at device close stage, for example, before device shutdown.
1722  */
1723 void
1724 sfc_rx_close(struct sfc_adapter *sa)
1725 {
1726         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1727
1728         sfc_rx_fini_queues(sa, 0);
1729
1730         rss->channels = 0;
1731
1732         free(sa->rxq_ctrl);
1733         sa->rxq_ctrl = NULL;
1734
1735         rte_free(sfc_sa2shared(sa)->rxq_info);
1736         sfc_sa2shared(sa)->rxq_info = NULL;
1737 }