1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2016-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 #include <rte_mempool.h>
15 #include "sfc_debug.h"
19 #include "sfc_mae_counter.h"
20 #include "sfc_kvargs.h"
21 #include "sfc_tweak.h"
24 * Maximum number of Rx queue flush attempt in the case of failure or
27 #define SFC_RX_QFLUSH_ATTEMPTS (3)
30 * Time to wait between event queue polling attempts when waiting for Rx
31 * queue flush done or failed events.
33 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1)
36 * Maximum number of event queue polling attempts when waiting for Rx queue
37 * flush done or failed events. It defines Rx queue flush attempt timeout
38 * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
40 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000)
43 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
45 rxq_info->state |= SFC_RXQ_FLUSHED;
46 rxq_info->state &= ~SFC_RXQ_FLUSHING;
50 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
52 rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
53 rxq_info->state &= ~SFC_RXQ_FLUSHING;
56 /* This returns the running counter, which is not bounded by ring size */
58 sfc_rx_get_pushed(struct sfc_adapter *sa, struct sfc_dp_rxq *dp_rxq)
60 SFC_ASSERT(sa->priv.dp_rx->get_pushed != NULL);
62 return sa->priv.dp_rx->get_pushed(dp_rxq);
66 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq)
70 if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) {
71 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr);
73 rxq->evq->read_ptr_primed = rxq->evq->read_ptr;
79 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
81 unsigned int free_space;
83 void *objs[SFC_RX_REFILL_BULK];
84 efsys_dma_addr_t addr[RTE_DIM(objs)];
85 unsigned int added = rxq->added;
88 struct sfc_efx_rx_sw_desc *rxd;
90 uint16_t port_id = rxq->dp.dpq.port_id;
92 free_space = rxq->max_fill_level - (added - rxq->completed);
94 if (free_space < rxq->refill_threshold)
97 bulks = free_space / RTE_DIM(objs);
98 /* refill_threshold guarantees that bulks is positive */
99 SFC_ASSERT(bulks > 0);
101 id = added & rxq->ptr_mask;
103 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
104 RTE_DIM(objs)) < 0)) {
106 * It is hardly a safe way to increment counter
107 * from different contexts, but all PMDs do it.
109 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
111 /* Return if we have posted nothing yet */
112 if (added == rxq->added)
118 for (i = 0; i < RTE_DIM(objs);
119 ++i, id = (id + 1) & rxq->ptr_mask) {
122 __rte_mbuf_raw_sanity_check(m);
124 rxd = &rxq->sw_desc[id];
127 m->data_off = RTE_PKTMBUF_HEADROOM;
130 addr[i] = rte_pktmbuf_iova(m);
133 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
134 RTE_DIM(objs), rxq->completed, added);
135 added += RTE_DIM(objs);
136 } while (--bulks > 0);
138 SFC_ASSERT(added != rxq->added);
140 efx_rx_qpush(rxq->common, added, &rxq->pushed);
144 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
146 uint64_t mbuf_flags = 0;
148 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
149 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
150 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
153 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
156 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
157 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
158 PKT_RX_IP_CKSUM_UNKNOWN);
162 switch ((desc_flags &
163 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
164 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
165 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
166 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
170 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
173 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
174 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
175 PKT_RX_L4_CKSUM_UNKNOWN);
183 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
185 return RTE_PTYPE_L2_ETHER |
186 ((desc_flags & EFX_PKT_IPV4) ?
187 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
188 ((desc_flags & EFX_PKT_IPV6) ?
189 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
190 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
191 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
194 static const uint32_t *
195 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
197 static const uint32_t ptypes[] = {
199 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
200 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
210 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
216 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
219 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
221 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
222 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
223 EFX_RX_HASHALG_TOEPLITZ,
226 m->ol_flags |= PKT_RX_RSS_HASH;
231 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
233 struct sfc_dp_rxq *dp_rxq = rx_queue;
234 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
235 unsigned int completed;
236 unsigned int prefix_size = rxq->prefix_size;
237 unsigned int done_pkts = 0;
238 boolean_t discard_next = B_FALSE;
239 struct rte_mbuf *scatter_pkt = NULL;
241 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
244 sfc_ev_qpoll(rxq->evq);
246 completed = rxq->completed;
247 while (completed != rxq->pending && done_pkts < nb_pkts) {
249 struct sfc_efx_rx_sw_desc *rxd;
251 unsigned int seg_len;
252 unsigned int desc_flags;
254 id = completed++ & rxq->ptr_mask;
255 rxd = &rxq->sw_desc[id];
257 desc_flags = rxd->flags;
262 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
265 if (desc_flags & EFX_PKT_PREFIX_LEN) {
269 rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
270 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
274 seg_len = rxd->size - prefix_size;
277 rte_pktmbuf_data_len(m) = seg_len;
278 rte_pktmbuf_pkt_len(m) = seg_len;
280 if (scatter_pkt != NULL) {
281 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
282 rte_pktmbuf_free(scatter_pkt);
285 /* The packet to deliver */
289 if (desc_flags & EFX_PKT_CONT) {
290 /* The packet is scattered, more fragments to come */
292 /* Further fragments have no prefix */
297 /* Scattered packet is done */
299 /* The first fragment of the packet has prefix */
300 prefix_size = rxq->prefix_size;
303 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
305 sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
308 * Extract RSS hash from the packet prefix and
309 * set the corresponding field (if needed and possible)
311 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
313 m->data_off += prefix_size;
320 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
321 rte_mbuf_raw_free(m);
325 /* pending is only moved when entire packet is received */
326 SFC_ASSERT(scatter_pkt == NULL);
328 rxq->completed = completed;
330 sfc_efx_rx_qrefill(rxq);
332 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN)
333 sfc_efx_rx_qprime(rxq);
338 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
340 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
342 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
344 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
347 sfc_ev_qpoll(rxq->evq);
349 return rxq->pending - rxq->completed;
352 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
354 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
356 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
358 if (unlikely(offset > rxq->ptr_mask))
362 * Poll EvQ to derive up-to-date 'rxq->pending' figure;
363 * it is required for the queue to be running, but the
364 * check is omitted because API design assumes that it
365 * is the duty of the caller to satisfy all conditions
367 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
368 SFC_EFX_RXQ_FLAG_RUNNING);
369 sfc_ev_qpoll(rxq->evq);
372 * There is a handful of reserved entries in the ring,
373 * but an explicit check whether the offset points to
374 * a reserved entry is neglected since the two checks
375 * below rely on the figures which take the HW limits
376 * into account and thus if an entry is reserved, the
377 * checks will fail and UNAVAIL code will be returned
380 if (offset < (rxq->pending - rxq->completed))
381 return RTE_ETH_RX_DESC_DONE;
383 if (offset < (rxq->added - rxq->completed))
384 return RTE_ETH_RX_DESC_AVAIL;
386 return RTE_ETH_RX_DESC_UNAVAIL;
390 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size,
391 boolean_t rx_scatter_enabled, uint32_t rx_scatter_max,
394 uint32_t effective_rx_scatter_max;
395 uint32_t rx_scatter_bufs;
397 effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1;
398 rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size);
400 if (rx_scatter_bufs > effective_rx_scatter_max) {
401 if (rx_scatter_enabled)
402 *error = "Possible number of Rx scatter buffers exceeds maximum number";
404 *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small";
411 /** Get Rx datapath ops by the datapath RxQ handle */
412 const struct sfc_dp_rx *
413 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
415 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
416 struct rte_eth_dev *eth_dev;
417 struct sfc_adapter_priv *sap;
419 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
420 eth_dev = &rte_eth_devices[dpq->port_id];
422 sap = sfc_adapter_priv_by_eth_dev(eth_dev);
427 struct sfc_rxq_info *
428 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
430 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
431 struct rte_eth_dev *eth_dev;
432 struct sfc_adapter_shared *sas;
434 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
435 eth_dev = &rte_eth_devices[dpq->port_id];
437 sas = sfc_adapter_shared_by_eth_dev(eth_dev);
439 SFC_ASSERT(dpq->queue_id < sas->rxq_count);
440 return &sas->rxq_info[dpq->queue_id];
444 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
446 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
447 struct rte_eth_dev *eth_dev;
448 struct sfc_adapter *sa;
450 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
451 eth_dev = &rte_eth_devices[dpq->port_id];
453 sa = sfc_adapter_by_eth_dev(eth_dev);
455 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count);
456 return &sa->rxq_ctrl[dpq->queue_id];
459 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
461 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
462 __rte_unused struct sfc_dp_rx_hw_limits *limits,
463 __rte_unused struct rte_mempool *mb_pool,
464 unsigned int *rxq_entries,
465 unsigned int *evq_entries,
466 unsigned int *rxq_max_fill_level)
468 *rxq_entries = nb_rx_desc;
469 *evq_entries = nb_rx_desc;
470 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
474 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
476 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
477 const struct rte_pci_addr *pci_addr, int socket_id,
478 const struct sfc_dp_rx_qcreate_info *info,
479 struct sfc_dp_rxq **dp_rxqp)
481 struct sfc_efx_rxq *rxq;
485 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
486 RTE_CACHE_LINE_SIZE, socket_id);
490 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
493 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
495 sizeof(*rxq->sw_desc),
496 RTE_CACHE_LINE_SIZE, socket_id);
497 if (rxq->sw_desc == NULL)
498 goto fail_desc_alloc;
500 /* efx datapath is bound to efx control path */
501 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
502 if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
503 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
504 rxq->ptr_mask = info->rxq_entries - 1;
505 rxq->batch_max = info->batch_max;
506 rxq->prefix_size = info->prefix_size;
507 rxq->max_fill_level = info->max_fill_level;
508 rxq->refill_threshold = info->refill_threshold;
509 rxq->buf_size = info->buf_size;
510 rxq->refill_mb_pool = info->refill_mb_pool;
522 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
524 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
526 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
528 rte_free(rxq->sw_desc);
533 /* Use qstop and qstart functions in the case of qstart failure */
534 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
535 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
538 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
540 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
541 __rte_unused unsigned int evq_read_ptr,
542 const efx_rx_prefix_layout_t *pinfo)
544 /* libefx-based datapath is specific to libefx-based PMD */
545 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
546 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
550 * libefx API is used to extract information from Rx prefix and
551 * it guarantees consistency. Just do length check to ensure
552 * that we reserved space in Rx buffers correctly.
554 if (rxq->prefix_size != pinfo->erpl_length)
557 rxq->common = crxq->common;
559 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
561 sfc_efx_rx_qrefill(rxq);
563 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
565 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) {
566 rc = sfc_efx_rx_qprime(rxq);
574 sfc_efx_rx_qstop(dp_rxq, NULL);
575 sfc_efx_rx_qpurge(dp_rxq);
580 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
581 __rte_unused unsigned int *evq_read_ptr)
583 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
585 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
587 /* libefx-based datapath is bound to libefx-based PMD and uses
588 * event queue structure directly. So, there is no necessity to
589 * return EvQ read pointer.
594 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
596 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
598 struct sfc_efx_rx_sw_desc *rxd;
600 for (i = rxq->completed; i != rxq->added; ++i) {
601 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
602 rte_mbuf_raw_free(rxd->mbuf);
604 /* Packed stream relies on 0 in inactive SW desc.
605 * Rx queue stop is not performance critical, so
606 * there is no harm to do it always.
612 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
615 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable;
617 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
619 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
622 rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN;
623 if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) {
624 rc = sfc_efx_rx_qprime(rxq);
626 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
631 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable;
633 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
635 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
637 /* Cannot disarm, just disable rearm */
638 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
642 struct sfc_dp_rx sfc_efx_rx = {
644 .name = SFC_KVARG_DATAPATH_EFX,
646 .hw_fw_caps = SFC_DP_HW_FW_CAP_RX_EFX,
648 .features = SFC_DP_RX_FEAT_INTR,
649 .dev_offload_capa = DEV_RX_OFFLOAD_CHECKSUM |
650 DEV_RX_OFFLOAD_RSS_HASH,
651 .queue_offload_capa = DEV_RX_OFFLOAD_SCATTER,
652 .qsize_up_rings = sfc_efx_rx_qsize_up_rings,
653 .qcreate = sfc_efx_rx_qcreate,
654 .qdestroy = sfc_efx_rx_qdestroy,
655 .qstart = sfc_efx_rx_qstart,
656 .qstop = sfc_efx_rx_qstop,
657 .qpurge = sfc_efx_rx_qpurge,
658 .supported_ptypes_get = sfc_efx_supported_ptypes_get,
659 .qdesc_npending = sfc_efx_rx_qdesc_npending,
660 .qdesc_status = sfc_efx_rx_qdesc_status,
661 .intr_enable = sfc_efx_rx_intr_enable,
662 .intr_disable = sfc_efx_rx_intr_disable,
663 .pkt_burst = sfc_efx_recv_pkts,
667 sfc_rx_qflush(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
669 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
670 sfc_ethdev_qid_t ethdev_qid;
671 struct sfc_rxq_info *rxq_info;
673 unsigned int retry_count;
674 unsigned int wait_count;
677 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
678 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
679 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
681 rxq = &sa->rxq_ctrl[sw_index];
684 * Retry Rx queue flushing in the case of flush failed or
685 * timeout. In the worst case it can delay for 6 seconds.
687 for (retry_count = 0;
688 ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
689 (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
691 rc = efx_rx_qflush(rxq->common);
693 rxq_info->state |= (rc == EALREADY) ?
694 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
697 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
698 rxq_info->state |= SFC_RXQ_FLUSHING;
701 * Wait for Rx queue flush done or failed event at least
702 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
703 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
704 * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
708 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
709 sfc_ev_qpoll(rxq->evq);
710 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
711 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
713 if (rxq_info->state & SFC_RXQ_FLUSHING)
714 sfc_err(sa, "RxQ %d (internal %u) flush timed out",
715 ethdev_qid, sw_index);
717 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
718 sfc_err(sa, "RxQ %d (internal %u) flush failed",
719 ethdev_qid, sw_index);
721 if (rxq_info->state & SFC_RXQ_FLUSHED)
722 sfc_notice(sa, "RxQ %d (internal %u) flushed",
723 ethdev_qid, sw_index);
726 sa->priv.dp_rx->qpurge(rxq_info->dp);
730 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
732 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
733 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
734 struct sfc_port *port = &sa->port;
738 * If promiscuous or all-multicast mode has been requested, setting
739 * filter for the default Rx queue might fail, in particular, while
740 * running over PCI function which is not a member of corresponding
741 * privilege groups; if this occurs, few iterations will be made to
742 * repeat this step without promiscuous and all-multicast flags set
745 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
748 else if (rc != EOPNOTSUPP)
752 sfc_warn(sa, "promiscuous mode has been requested, "
753 "but the HW rejects it");
754 sfc_warn(sa, "promiscuous mode will be disabled");
756 port->promisc = B_FALSE;
757 sa->eth_dev->data->promiscuous = 0;
758 rc = sfc_set_rx_mode_unchecked(sa);
765 if (port->allmulti) {
766 sfc_warn(sa, "all-multicast mode has been requested, "
767 "but the HW rejects it");
768 sfc_warn(sa, "all-multicast mode will be disabled");
770 port->allmulti = B_FALSE;
771 sa->eth_dev->data->all_multicast = 0;
772 rc = sfc_set_rx_mode_unchecked(sa);
783 sfc_rx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
785 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
786 sfc_ethdev_qid_t ethdev_qid;
787 struct sfc_rxq_info *rxq_info;
790 efx_rx_prefix_layout_t pinfo;
793 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
794 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
796 sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
798 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
799 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
801 rxq = &sa->rxq_ctrl[sw_index];
804 rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index));
808 switch (rxq_info->type) {
809 case EFX_RXQ_TYPE_DEFAULT:
810 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
812 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
813 rxq_info->type_flags, evq->common, &rxq->common);
815 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
816 struct rte_mempool *mp = rxq_info->refill_mb_pool;
817 struct rte_mempool_info mp_info;
819 rc = rte_mempool_ops_get_info(mp, &mp_info);
821 /* Positive errno is used in the driver */
823 goto fail_mp_get_info;
825 if (mp_info.contig_block_size <= 0) {
827 goto fail_bad_contig_block_size;
829 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
830 mp_info.contig_block_size, rxq->buf_size,
831 mp->header_size + mp->elt_size + mp->trailer_size,
832 sa->rxd_wait_timeout_ns,
833 &rxq->mem, rxq_info->entries, rxq_info->type_flags,
834 evq->common, &rxq->common);
841 goto fail_rx_qcreate;
843 rc = efx_rx_prefix_get_layout(rxq->common, &pinfo);
845 goto fail_prefix_get_layout;
847 efx_rx_qenable(rxq->common);
849 rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr, &pinfo);
853 rxq_info->state |= SFC_RXQ_STARTED;
855 if (ethdev_qid == 0 && !sfc_sa2shared(sa)->isolated) {
856 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
858 goto fail_mac_filter_default_rxq_set;
861 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
862 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
863 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
864 RTE_ETH_QUEUE_STATE_STARTED;
868 fail_mac_filter_default_rxq_set:
869 sfc_rx_qflush(sa, sw_index);
870 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
871 rxq_info->state = SFC_RXQ_INITIALIZED;
874 efx_rx_qdestroy(rxq->common);
876 fail_prefix_get_layout:
878 fail_bad_contig_block_size:
887 sfc_rx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
889 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
890 sfc_ethdev_qid_t ethdev_qid;
891 struct sfc_rxq_info *rxq_info;
894 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
895 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
897 sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
899 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
901 if (rxq_info->state == SFC_RXQ_INITIALIZED)
903 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
905 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
906 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
907 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
908 RTE_ETH_QUEUE_STATE_STOPPED;
910 rxq = &sa->rxq_ctrl[sw_index];
911 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
914 efx_mac_filter_default_rxq_clear(sa->nic);
916 sfc_rx_qflush(sa, sw_index);
918 rxq_info->state = SFC_RXQ_INITIALIZED;
920 efx_rx_qdestroy(rxq->common);
922 sfc_ev_qstop(rxq->evq);
926 sfc_rx_get_offload_mask(struct sfc_adapter *sa)
928 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
929 uint64_t no_caps = 0;
931 if (encp->enc_tunnel_encapsulations_supported == 0)
932 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
938 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
940 uint64_t caps = sa->priv.dp_rx->dev_offload_capa;
942 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
944 return caps & sfc_rx_get_offload_mask(sa);
948 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
950 return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa);
954 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
955 const struct rte_eth_rxconf *rx_conf,
956 __rte_unused uint64_t offloads)
960 if (rx_conf->rx_thresh.pthresh != 0 ||
961 rx_conf->rx_thresh.hthresh != 0 ||
962 rx_conf->rx_thresh.wthresh != 0) {
964 "RxQ prefetch/host/writeback thresholds are not supported");
967 if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
969 "RxQ free threshold too large: %u vs maximum %u",
970 rx_conf->rx_free_thresh, rxq_max_fill_level);
974 if (rx_conf->rx_drop_en == 0) {
975 sfc_err(sa, "RxQ drop disable is not supported");
983 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
988 /* The mbuf object itself is always cache line aligned */
989 order = rte_bsf32(RTE_CACHE_LINE_SIZE);
991 /* Data offset from mbuf object start */
992 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
993 RTE_PKTMBUF_HEADROOM;
995 order = MIN(order, rte_bsf32(data_off));
1001 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
1003 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1004 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
1005 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
1007 unsigned int buf_aligned;
1008 unsigned int start_alignment;
1009 unsigned int end_padding_alignment;
1011 /* Below it is assumed that both alignments are power of 2 */
1012 SFC_ASSERT(rte_is_power_of_2(nic_align_start));
1013 SFC_ASSERT(rte_is_power_of_2(nic_align_end));
1016 * mbuf is always cache line aligned, double-check
1017 * that it meets rx buffer start alignment requirements.
1020 /* Start from mbuf pool data room size */
1021 buf_size = rte_pktmbuf_data_room_size(mb_pool);
1023 /* Remove headroom */
1024 if (buf_size <= RTE_PKTMBUF_HEADROOM) {
1026 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
1027 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
1030 buf_size -= RTE_PKTMBUF_HEADROOM;
1032 /* Calculate guaranteed data start alignment */
1033 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
1035 /* Reserve space for start alignment */
1036 if (buf_aligned < nic_align_start) {
1037 start_alignment = nic_align_start - buf_aligned;
1038 if (buf_size <= start_alignment) {
1040 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
1042 rte_pktmbuf_data_room_size(mb_pool),
1043 RTE_PKTMBUF_HEADROOM, start_alignment);
1046 buf_aligned = nic_align_start;
1047 buf_size -= start_alignment;
1049 start_alignment = 0;
1052 /* Make sure that end padding does not write beyond the buffer */
1053 if (buf_aligned < nic_align_end) {
1055 * Estimate space which can be lost. If guarnteed buffer
1056 * size is odd, lost space is (nic_align_end - 1). More
1057 * accurate formula is below.
1059 end_padding_alignment = nic_align_end -
1060 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
1061 if (buf_size <= end_padding_alignment) {
1063 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
1065 rte_pktmbuf_data_room_size(mb_pool),
1066 RTE_PKTMBUF_HEADROOM, start_alignment,
1067 end_padding_alignment);
1070 buf_size -= end_padding_alignment;
1073 * Start is aligned the same or better than end,
1074 * just align length.
1076 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end);
1083 sfc_rx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1084 uint16_t nb_rx_desc, unsigned int socket_id,
1085 const struct rte_eth_rxconf *rx_conf,
1086 struct rte_mempool *mb_pool)
1088 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1089 sfc_ethdev_qid_t ethdev_qid;
1090 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1091 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1093 unsigned int rxq_entries;
1094 unsigned int evq_entries;
1095 unsigned int rxq_max_fill_level;
1098 struct sfc_rxq_info *rxq_info;
1099 struct sfc_evq *evq;
1100 struct sfc_rxq *rxq;
1101 struct sfc_dp_rx_qcreate_info info;
1102 struct sfc_dp_rx_hw_limits hw_limits;
1103 uint16_t rx_free_thresh;
1106 memset(&hw_limits, 0, sizeof(hw_limits));
1107 hw_limits.rxq_max_entries = sa->rxq_max_entries;
1108 hw_limits.rxq_min_entries = sa->rxq_min_entries;
1109 hw_limits.evq_max_entries = sa->evq_max_entries;
1110 hw_limits.evq_min_entries = sa->evq_min_entries;
1112 rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool,
1113 &rxq_entries, &evq_entries,
1114 &rxq_max_fill_level);
1116 goto fail_size_up_rings;
1117 SFC_ASSERT(rxq_entries >= sa->rxq_min_entries);
1118 SFC_ASSERT(rxq_entries <= sa->rxq_max_entries);
1119 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
1121 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1123 offloads = rx_conf->offloads;
1124 /* Add device level Rx offloads if the queue is an ethdev Rx queue */
1125 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1126 offloads |= sa->eth_dev->data->dev_conf.rxmode.offloads;
1128 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
1132 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1133 if (buf_size == 0) {
1135 "RxQ %d (internal %u) mbuf pool object size is too small",
1136 ethdev_qid, sw_index);
1141 if (!sfc_rx_check_scatter(sa->port.pdu, buf_size,
1142 encp->enc_rx_prefix_size,
1143 (offloads & DEV_RX_OFFLOAD_SCATTER),
1144 encp->enc_rx_scatter_max,
1146 sfc_err(sa, "RxQ %d (internal %u) MTU check failed: %s",
1147 ethdev_qid, sw_index, error);
1149 "RxQ %d (internal %u) calculated Rx buffer size is %u vs "
1150 "PDU size %u plus Rx prefix %u bytes",
1151 ethdev_qid, sw_index, buf_size,
1152 (unsigned int)sa->port.pdu, encp->enc_rx_prefix_size);
1157 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1158 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1160 SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1161 rxq_info->entries = rxq_entries;
1163 if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1164 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1166 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1168 rxq_info->type_flags |=
1169 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1170 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1172 if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1173 (sfc_dp_rx_offload_capa(sa->priv.dp_rx) &
1174 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0)
1175 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1177 if (offloads & DEV_RX_OFFLOAD_RSS_HASH)
1178 rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH;
1180 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1181 evq_entries, socket_id, &evq);
1185 rxq = &sa->rxq_ctrl[sw_index];
1187 rxq->hw_index = sw_index;
1189 * If Rx refill threshold is specified (its value is non zero) in
1190 * Rx configuration, use specified value. Otherwise use 1/8 of
1191 * the Rx descriptors number as the default. It allows to keep
1192 * Rx ring full-enough and does not refill too aggressive if
1193 * packet rate is high.
1195 * Since PMD refills in bulks waiting for full bulk may be
1196 * refilled (basically round down), it is better to round up
1197 * here to mitigate it a bit.
1199 rx_free_thresh = (rx_conf->rx_free_thresh != 0) ?
1200 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8);
1201 /* Rx refill threshold cannot be smaller than refill bulk */
1202 rxq_info->refill_threshold =
1203 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK);
1204 rxq_info->refill_mb_pool = mb_pool;
1206 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 &&
1207 (offloads & DEV_RX_OFFLOAD_RSS_HASH))
1208 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH;
1210 rxq_info->rxq_flags = 0;
1212 rxq->buf_size = buf_size;
1214 rc = sfc_dma_alloc(sa, "rxq", sw_index,
1215 efx_rxq_size(sa->nic, rxq_info->entries),
1216 socket_id, &rxq->mem);
1218 goto fail_dma_alloc;
1220 memset(&info, 0, sizeof(info));
1221 info.refill_mb_pool = rxq_info->refill_mb_pool;
1222 info.max_fill_level = rxq_max_fill_level;
1223 info.refill_threshold = rxq_info->refill_threshold;
1224 info.buf_size = buf_size;
1225 info.batch_max = encp->enc_rx_batch_max;
1226 info.prefix_size = encp->enc_rx_prefix_size;
1227 info.flags = rxq_info->rxq_flags;
1228 info.rxq_entries = rxq_info->entries;
1229 info.rxq_hw_ring = rxq->mem.esm_base;
1230 info.evq_hw_index = sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index);
1231 info.evq_entries = evq_entries;
1232 info.evq_hw_ring = evq->mem.esm_base;
1233 info.hw_index = rxq->hw_index;
1234 info.mem_bar = sa->mem_bar.esb_base;
1235 info.vi_window_shift = encp->enc_vi_window_shift;
1236 info.fcw_offset = sa->fcw_offset;
1238 rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1239 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1240 socket_id, &info, &rxq_info->dp);
1242 goto fail_dp_rx_qcreate;
1244 evq->dp_rxq = rxq_info->dp;
1246 rxq_info->state = SFC_RXQ_INITIALIZED;
1248 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1253 sfc_dma_free(sa, &rxq->mem);
1259 rxq_info->entries = 0;
1263 sfc_log_init(sa, "failed %d", rc);
1268 sfc_rx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
1270 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1271 sfc_ethdev_qid_t ethdev_qid;
1272 struct sfc_rxq_info *rxq_info;
1273 struct sfc_rxq *rxq;
1275 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1276 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1278 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1279 sa->eth_dev->data->rx_queues[ethdev_qid] = NULL;
1281 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1283 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1285 sa->priv.dp_rx->qdestroy(rxq_info->dp);
1286 rxq_info->dp = NULL;
1288 rxq_info->state &= ~SFC_RXQ_INITIALIZED;
1289 rxq_info->entries = 0;
1291 rxq = &sa->rxq_ctrl[sw_index];
1293 sfc_dma_free(sa, &rxq->mem);
1295 sfc_ev_qfini(rxq->evq);
1300 * Mapping between RTE RSS hash functions and their EFX counterparts.
1302 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1303 { ETH_RSS_NONFRAG_IPV4_TCP,
1304 EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1305 { ETH_RSS_NONFRAG_IPV4_UDP,
1306 EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1307 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1308 EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1309 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1310 EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1311 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1312 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1313 EFX_RX_HASH(IPV4, 2TUPLE) },
1314 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1316 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1317 EFX_RX_HASH(IPV6, 2TUPLE) }
1320 static efx_rx_hash_type_t
1321 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1322 unsigned int *hash_type_flags_supported,
1323 unsigned int nb_hash_type_flags_supported)
1325 efx_rx_hash_type_t hash_type_masked = 0;
1328 for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1329 unsigned int class_tuple_lbn[] = {
1330 EFX_RX_CLASS_IPV4_TCP_LBN,
1331 EFX_RX_CLASS_IPV4_UDP_LBN,
1332 EFX_RX_CLASS_IPV4_LBN,
1333 EFX_RX_CLASS_IPV6_TCP_LBN,
1334 EFX_RX_CLASS_IPV6_UDP_LBN,
1335 EFX_RX_CLASS_IPV6_LBN
1338 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1339 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1342 tuple_mask <<= class_tuple_lbn[j];
1343 flag = hash_type & tuple_mask;
1345 if (flag == hash_type_flags_supported[i])
1346 hash_type_masked |= flag;
1350 return hash_type_masked;
1354 sfc_rx_hash_init(struct sfc_adapter *sa)
1356 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1357 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1358 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1359 efx_rx_hash_alg_t alg;
1360 unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1361 unsigned int nb_flags_supp;
1362 struct sfc_rss_hf_rte_to_efx *hf_map;
1363 struct sfc_rss_hf_rte_to_efx *entry;
1364 efx_rx_hash_type_t efx_hash_types;
1368 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1369 alg = EFX_RX_HASHALG_TOEPLITZ;
1370 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1371 alg = EFX_RX_HASHALG_PACKED_STREAM;
1375 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1376 RTE_DIM(flags_supp), &nb_flags_supp);
1380 hf_map = rte_calloc_socket("sfc-rss-hf-map",
1381 RTE_DIM(sfc_rss_hf_map),
1382 sizeof(*hf_map), 0, sa->socket_id);
1388 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1389 efx_rx_hash_type_t ht;
1391 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1392 flags_supp, nb_flags_supp);
1394 entry->rte = sfc_rss_hf_map[i].rte;
1396 efx_hash_types |= ht;
1401 rss->hash_alg = alg;
1402 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1403 rss->hf_map = hf_map;
1404 rss->hash_types = efx_hash_types;
1410 sfc_rx_hash_fini(struct sfc_adapter *sa)
1412 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1414 rte_free(rss->hf_map);
1418 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1419 efx_rx_hash_type_t *efx)
1421 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1422 efx_rx_hash_type_t hash_types = 0;
1425 for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1426 uint64_t rte_mask = rss->hf_map[i].rte;
1428 if ((rte & rte_mask) != 0) {
1430 hash_types |= rss->hf_map[i].efx;
1435 sfc_err(sa, "unsupported hash functions requested");
1445 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx)
1450 for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1451 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1453 if ((efx & hash_type) == hash_type)
1454 rte |= rss->hf_map[i].rte;
1461 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1462 struct rte_eth_rss_conf *conf)
1464 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1465 efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1466 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types);
1469 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1470 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1471 conf->rss_key != NULL)
1475 if (conf->rss_hf != 0) {
1476 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1481 if (conf->rss_key != NULL) {
1482 if (conf->rss_key_len != sizeof(rss->key)) {
1483 sfc_err(sa, "RSS key size is wrong (should be %zu)",
1487 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1490 rss->hash_types = efx_hash_types;
1496 sfc_rx_rss_config(struct sfc_adapter *sa)
1498 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1501 if (rss->channels > 0) {
1502 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1503 rss->hash_alg, rss->hash_types,
1508 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1509 rss->key, sizeof(rss->key));
1513 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1514 rss->tbl, RTE_DIM(rss->tbl));
1521 struct sfc_rxq_info *
1522 sfc_rxq_info_by_ethdev_qid(struct sfc_adapter_shared *sas,
1523 sfc_ethdev_qid_t ethdev_qid)
1525 sfc_sw_index_t sw_index;
1527 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1528 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1530 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1531 return &sas->rxq_info[sw_index];
1535 sfc_rxq_ctrl_by_ethdev_qid(struct sfc_adapter *sa, sfc_ethdev_qid_t ethdev_qid)
1537 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1538 sfc_sw_index_t sw_index;
1540 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1541 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1543 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1544 return &sa->rxq_ctrl[sw_index];
1548 sfc_rx_start(struct sfc_adapter *sa)
1550 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1551 sfc_sw_index_t sw_index;
1554 sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1557 rc = efx_rx_init(sa->nic);
1561 rc = sfc_rx_rss_config(sa);
1563 goto fail_rss_config;
1565 for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) {
1566 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED &&
1567 (!sas->rxq_info[sw_index].deferred_start ||
1568 sas->rxq_info[sw_index].deferred_started)) {
1569 rc = sfc_rx_qstart(sa, sw_index);
1571 goto fail_rx_qstart;
1578 while (sw_index-- > 0)
1579 sfc_rx_qstop(sa, sw_index);
1582 efx_rx_fini(sa->nic);
1585 sfc_log_init(sa, "failed %d", rc);
1590 sfc_rx_stop(struct sfc_adapter *sa)
1592 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1593 sfc_sw_index_t sw_index;
1595 sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1598 sw_index = sas->rxq_count;
1599 while (sw_index-- > 0) {
1600 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED)
1601 sfc_rx_qstop(sa, sw_index);
1604 efx_rx_fini(sa->nic);
1608 sfc_rx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1609 unsigned int extra_efx_type_flags)
1611 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1612 struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index];
1613 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1614 unsigned int max_entries;
1616 max_entries = encp->enc_rxq_max_ndescs;
1617 SFC_ASSERT(rte_is_power_of_2(max_entries));
1619 rxq_info->max_entries = max_entries;
1620 rxq_info->type_flags = extra_efx_type_flags;
1626 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1628 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1629 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1630 sfc_rx_get_queue_offload_caps(sa);
1631 struct sfc_rss *rss = &sas->rss;
1634 switch (rxmode->mq_mode) {
1635 case ETH_MQ_RX_NONE:
1636 /* No special checks are required */
1639 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1640 sfc_err(sa, "RSS is not available");
1645 sfc_err(sa, "Rx multi-queue mode %u not supported",
1651 * Requested offloads are validated against supported by ethdev,
1652 * so unsupported offloads cannot be added as the result of
1655 if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1656 (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1657 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1658 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1661 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1662 (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1663 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1664 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1671 * Destroy excess queues that are no longer needed after reconfiguration
1672 * or complete close.
1675 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1677 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1678 sfc_sw_index_t sw_index;
1679 sfc_ethdev_qid_t ethdev_qid;
1681 SFC_ASSERT(nb_rx_queues <= sas->ethdev_rxq_count);
1684 * Finalize only ethdev queues since other ones are finalized only
1685 * on device close and they may require additional deinitializaton.
1687 ethdev_qid = sas->ethdev_rxq_count;
1688 while (--ethdev_qid >= (int)nb_rx_queues) {
1689 struct sfc_rxq_info *rxq_info;
1691 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, ethdev_qid);
1692 if (rxq_info->state & SFC_RXQ_INITIALIZED) {
1693 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1695 sfc_rx_qfini(sa, sw_index);
1700 sas->ethdev_rxq_count = nb_rx_queues;
1704 * Initialize Rx subsystem.
1706 * Called at device (re)configuration stage when number of receive queues is
1707 * specified together with other device level receive configuration.
1709 * It should be used to allocate NUMA-unaware resources.
1712 sfc_rx_configure(struct sfc_adapter *sa)
1714 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1715 struct sfc_rss *rss = &sas->rss;
1716 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1717 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1718 const unsigned int nb_rsrv_rx_queues = sfc_nb_reserved_rxq(sas);
1719 const unsigned int nb_rxq_total = nb_rx_queues + nb_rsrv_rx_queues;
1723 sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1724 nb_rx_queues, sas->ethdev_rxq_count);
1726 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1728 goto fail_check_mode;
1730 if (nb_rxq_total == sas->rxq_count) {
1735 if (sas->rxq_info == NULL) {
1736 reconfigure = false;
1738 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rxq_total,
1739 sizeof(sas->rxq_info[0]), 0,
1741 if (sas->rxq_info == NULL)
1742 goto fail_rxqs_alloc;
1745 * Allocate primary process only RxQ control from heap
1746 * since it should not be shared.
1749 sa->rxq_ctrl = calloc(nb_rxq_total, sizeof(sa->rxq_ctrl[0]));
1750 if (sa->rxq_ctrl == NULL)
1751 goto fail_rxqs_ctrl_alloc;
1753 struct sfc_rxq_info *new_rxq_info;
1754 struct sfc_rxq *new_rxq_ctrl;
1758 /* Do not ununitialize reserved queues */
1759 if (nb_rx_queues < sas->ethdev_rxq_count)
1760 sfc_rx_fini_queues(sa, nb_rx_queues);
1764 rte_realloc(sas->rxq_info,
1765 nb_rxq_total * sizeof(sas->rxq_info[0]), 0);
1766 if (new_rxq_info == NULL && nb_rxq_total > 0)
1767 goto fail_rxqs_realloc;
1770 new_rxq_ctrl = realloc(sa->rxq_ctrl,
1771 nb_rxq_total * sizeof(sa->rxq_ctrl[0]));
1772 if (new_rxq_ctrl == NULL && nb_rxq_total > 0)
1773 goto fail_rxqs_ctrl_realloc;
1775 sas->rxq_info = new_rxq_info;
1776 sa->rxq_ctrl = new_rxq_ctrl;
1777 if (nb_rxq_total > sas->rxq_count) {
1778 unsigned int rxq_count = sas->rxq_count;
1780 memset(&sas->rxq_info[rxq_count], 0,
1781 (nb_rxq_total - rxq_count) *
1782 sizeof(sas->rxq_info[0]));
1783 memset(&sa->rxq_ctrl[rxq_count], 0,
1784 (nb_rxq_total - rxq_count) *
1785 sizeof(sa->rxq_ctrl[0]));
1789 while (sas->ethdev_rxq_count < nb_rx_queues) {
1790 sfc_sw_index_t sw_index;
1792 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1793 sas->ethdev_rxq_count);
1794 rc = sfc_rx_qinit_info(sa, sw_index, 0);
1796 goto fail_rx_qinit_info;
1798 sas->ethdev_rxq_count++;
1801 sas->rxq_count = sas->ethdev_rxq_count + nb_rsrv_rx_queues;
1804 rc = sfc_mae_counter_rxq_init(sa);
1806 goto fail_count_rxq_init;
1810 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1811 MIN(sas->ethdev_rxq_count, EFX_MAXRSS) : 0;
1813 if (rss->channels > 0) {
1814 struct rte_eth_rss_conf *adv_conf_rss;
1815 sfc_sw_index_t sw_index;
1817 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1818 rss->tbl[sw_index] = sw_index % rss->channels;
1820 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1821 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1823 goto fail_rx_process_adv_conf_rss;
1828 fail_rx_process_adv_conf_rss:
1830 sfc_mae_counter_rxq_fini(sa);
1832 fail_count_rxq_init:
1834 fail_rxqs_ctrl_realloc:
1836 fail_rxqs_ctrl_alloc:
1841 sfc_log_init(sa, "failed %d", rc);
1846 * Shutdown Rx subsystem.
1848 * Called at device close stage, for example, before device shutdown.
1851 sfc_rx_close(struct sfc_adapter *sa)
1853 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1855 sfc_rx_fini_queues(sa, 0);
1856 sfc_mae_counter_rxq_fini(sa);
1861 sa->rxq_ctrl = NULL;
1863 rte_free(sfc_sa2shared(sa)->rxq_info);
1864 sfc_sa2shared(sa)->rxq_info = NULL;