1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 #include <rte_mempool.h>
15 #include "sfc_debug.h"
19 #include "sfc_kvargs.h"
20 #include "sfc_tweak.h"
23 * Maximum number of Rx queue flush attempt in the case of failure or
26 #define SFC_RX_QFLUSH_ATTEMPTS (3)
29 * Time to wait between event queue polling attempts when waiting for Rx
30 * queue flush done or failed events.
32 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1)
35 * Maximum number of event queue polling attempts when waiting for Rx queue
36 * flush done or failed events. It defines Rx queue flush attempt timeout
37 * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000)
42 sfc_rx_qflush_done(struct sfc_rxq *rxq)
44 rxq->state |= SFC_RXQ_FLUSHED;
45 rxq->state &= ~SFC_RXQ_FLUSHING;
49 sfc_rx_qflush_failed(struct sfc_rxq *rxq)
51 rxq->state |= SFC_RXQ_FLUSH_FAILED;
52 rxq->state &= ~SFC_RXQ_FLUSHING;
56 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
58 unsigned int free_space;
60 void *objs[SFC_RX_REFILL_BULK];
61 efsys_dma_addr_t addr[RTE_DIM(objs)];
62 unsigned int added = rxq->added;
65 struct sfc_efx_rx_sw_desc *rxd;
67 uint16_t port_id = rxq->dp.dpq.port_id;
69 free_space = rxq->max_fill_level - (added - rxq->completed);
71 if (free_space < rxq->refill_threshold)
74 bulks = free_space / RTE_DIM(objs);
75 /* refill_threshold guarantees that bulks is positive */
76 SFC_ASSERT(bulks > 0);
78 id = added & rxq->ptr_mask;
80 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
81 RTE_DIM(objs)) < 0)) {
83 * It is hardly a safe way to increment counter
84 * from different contexts, but all PMDs do it.
86 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
88 /* Return if we have posted nothing yet */
89 if (added == rxq->added)
95 for (i = 0; i < RTE_DIM(objs);
96 ++i, id = (id + 1) & rxq->ptr_mask) {
99 rxd = &rxq->sw_desc[id];
102 SFC_ASSERT(rte_mbuf_refcnt_read(m) == 1);
103 m->data_off = RTE_PKTMBUF_HEADROOM;
104 SFC_ASSERT(m->next == NULL);
105 SFC_ASSERT(m->nb_segs == 1);
108 addr[i] = rte_pktmbuf_iova(m);
111 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
112 RTE_DIM(objs), rxq->completed, added);
113 added += RTE_DIM(objs);
114 } while (--bulks > 0);
116 SFC_ASSERT(added != rxq->added);
118 efx_rx_qpush(rxq->common, added, &rxq->pushed);
122 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
124 uint64_t mbuf_flags = 0;
126 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
127 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
128 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
131 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
134 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
135 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
136 PKT_RX_IP_CKSUM_UNKNOWN);
140 switch ((desc_flags &
141 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
142 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
143 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
144 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
148 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
151 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
152 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
153 PKT_RX_L4_CKSUM_UNKNOWN);
161 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
163 return RTE_PTYPE_L2_ETHER |
164 ((desc_flags & EFX_PKT_IPV4) ?
165 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
166 ((desc_flags & EFX_PKT_IPV6) ?
167 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
168 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
169 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
172 static const uint32_t *
173 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
175 static const uint32_t ptypes[] = {
177 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
178 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
188 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
194 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
197 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
199 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
200 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
201 EFX_RX_HASHALG_TOEPLITZ,
204 m->ol_flags |= PKT_RX_RSS_HASH;
209 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
211 struct sfc_dp_rxq *dp_rxq = rx_queue;
212 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
213 unsigned int completed;
214 unsigned int prefix_size = rxq->prefix_size;
215 unsigned int done_pkts = 0;
216 boolean_t discard_next = B_FALSE;
217 struct rte_mbuf *scatter_pkt = NULL;
219 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
222 sfc_ev_qpoll(rxq->evq);
224 completed = rxq->completed;
225 while (completed != rxq->pending && done_pkts < nb_pkts) {
227 struct sfc_efx_rx_sw_desc *rxd;
229 unsigned int seg_len;
230 unsigned int desc_flags;
232 id = completed++ & rxq->ptr_mask;
233 rxd = &rxq->sw_desc[id];
235 desc_flags = rxd->flags;
240 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
243 if (desc_flags & EFX_PKT_PREFIX_LEN) {
247 rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
248 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
252 seg_len = rxd->size - prefix_size;
255 rte_pktmbuf_data_len(m) = seg_len;
256 rte_pktmbuf_pkt_len(m) = seg_len;
258 if (scatter_pkt != NULL) {
259 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
260 rte_pktmbuf_free(scatter_pkt);
263 /* The packet to deliver */
267 if (desc_flags & EFX_PKT_CONT) {
268 /* The packet is scattered, more fragments to come */
270 /* Further fragments have no prefix */
275 /* Scattered packet is done */
277 /* The first fragment of the packet has prefix */
278 prefix_size = rxq->prefix_size;
281 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
283 sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
286 * Extract RSS hash from the packet prefix and
287 * set the corresponding field (if needed and possible)
289 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
291 m->data_off += prefix_size;
298 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
299 rte_mempool_put(rxq->refill_mb_pool, m);
303 /* pending is only moved when entire packet is received */
304 SFC_ASSERT(scatter_pkt == NULL);
306 rxq->completed = completed;
308 sfc_efx_rx_qrefill(rxq);
313 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
315 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
317 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
319 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
322 sfc_ev_qpoll(rxq->evq);
324 return rxq->pending - rxq->completed;
327 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
329 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
331 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
333 if (unlikely(offset > rxq->ptr_mask))
337 * Poll EvQ to derive up-to-date 'rxq->pending' figure;
338 * it is required for the queue to be running, but the
339 * check is omitted because API design assumes that it
340 * is the duty of the caller to satisfy all conditions
342 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
343 SFC_EFX_RXQ_FLAG_RUNNING);
344 sfc_ev_qpoll(rxq->evq);
347 * There is a handful of reserved entries in the ring,
348 * but an explicit check whether the offset points to
349 * a reserved entry is neglected since the two checks
350 * below rely on the figures which take the HW limits
351 * into account and thus if an entry is reserved, the
352 * checks will fail and UNAVAIL code will be returned
355 if (offset < (rxq->pending - rxq->completed))
356 return RTE_ETH_RX_DESC_DONE;
358 if (offset < (rxq->added - rxq->completed))
359 return RTE_ETH_RX_DESC_AVAIL;
361 return RTE_ETH_RX_DESC_UNAVAIL;
365 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
367 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
368 struct rte_eth_dev *eth_dev;
369 struct sfc_adapter *sa;
372 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
373 eth_dev = &rte_eth_devices[dpq->port_id];
375 sa = eth_dev->data->dev_private;
377 SFC_ASSERT(dpq->queue_id < sa->rxq_count);
378 rxq = sa->rxq_info[dpq->queue_id].rxq;
380 SFC_ASSERT(rxq != NULL);
384 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
386 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
387 unsigned int *rxq_entries,
388 unsigned int *evq_entries,
389 unsigned int *rxq_max_fill_level)
391 *rxq_entries = nb_rx_desc;
392 *evq_entries = nb_rx_desc;
393 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
397 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
399 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
400 const struct rte_pci_addr *pci_addr, int socket_id,
401 const struct sfc_dp_rx_qcreate_info *info,
402 struct sfc_dp_rxq **dp_rxqp)
404 struct sfc_efx_rxq *rxq;
408 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
409 RTE_CACHE_LINE_SIZE, socket_id);
413 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
416 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
418 sizeof(*rxq->sw_desc),
419 RTE_CACHE_LINE_SIZE, socket_id);
420 if (rxq->sw_desc == NULL)
421 goto fail_desc_alloc;
423 /* efx datapath is bound to efx control path */
424 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
425 if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
426 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
427 rxq->ptr_mask = info->rxq_entries - 1;
428 rxq->batch_max = info->batch_max;
429 rxq->prefix_size = info->prefix_size;
430 rxq->max_fill_level = info->max_fill_level;
431 rxq->refill_threshold = info->refill_threshold;
432 rxq->buf_size = info->buf_size;
433 rxq->refill_mb_pool = info->refill_mb_pool;
445 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
447 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
449 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
451 rte_free(rxq->sw_desc);
455 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
457 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
458 __rte_unused unsigned int evq_read_ptr)
460 /* libefx-based datapath is specific to libefx-based PMD */
461 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
462 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
464 rxq->common = crxq->common;
466 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
468 sfc_efx_rx_qrefill(rxq);
470 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
475 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
477 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
478 __rte_unused unsigned int *evq_read_ptr)
480 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
482 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
484 /* libefx-based datapath is bound to libefx-based PMD and uses
485 * event queue structure directly. So, there is no necessity to
486 * return EvQ read pointer.
490 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
492 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
494 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
496 struct sfc_efx_rx_sw_desc *rxd;
498 for (i = rxq->completed; i != rxq->added; ++i) {
499 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
500 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
502 /* Packed stream relies on 0 in inactive SW desc.
503 * Rx queue stop is not performance critical, so
504 * there is no harm to do it always.
510 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
513 struct sfc_dp_rx sfc_efx_rx = {
515 .name = SFC_KVARG_DATAPATH_EFX,
519 .features = SFC_DP_RX_FEAT_SCATTER,
520 .qsize_up_rings = sfc_efx_rx_qsize_up_rings,
521 .qcreate = sfc_efx_rx_qcreate,
522 .qdestroy = sfc_efx_rx_qdestroy,
523 .qstart = sfc_efx_rx_qstart,
524 .qstop = sfc_efx_rx_qstop,
525 .qpurge = sfc_efx_rx_qpurge,
526 .supported_ptypes_get = sfc_efx_supported_ptypes_get,
527 .qdesc_npending = sfc_efx_rx_qdesc_npending,
528 .qdesc_status = sfc_efx_rx_qdesc_status,
529 .pkt_burst = sfc_efx_recv_pkts,
533 sfc_rx_qdesc_npending(struct sfc_adapter *sa, unsigned int sw_index)
537 SFC_ASSERT(sw_index < sa->rxq_count);
538 rxq = sa->rxq_info[sw_index].rxq;
540 if (rxq == NULL || (rxq->state & SFC_RXQ_STARTED) == 0)
543 return sa->dp_rx->qdesc_npending(rxq->dp);
547 sfc_rx_qdesc_done(struct sfc_dp_rxq *dp_rxq, unsigned int offset)
549 struct sfc_rxq *rxq = sfc_rxq_by_dp_rxq(dp_rxq);
551 return offset < rxq->evq->sa->dp_rx->qdesc_npending(dp_rxq);
555 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
558 unsigned int retry_count;
559 unsigned int wait_count;
562 rxq = sa->rxq_info[sw_index].rxq;
563 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
566 * Retry Rx queue flushing in the case of flush failed or
567 * timeout. In the worst case it can delay for 6 seconds.
569 for (retry_count = 0;
570 ((rxq->state & SFC_RXQ_FLUSHED) == 0) &&
571 (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
573 rc = efx_rx_qflush(rxq->common);
575 rxq->state |= (rc == EALREADY) ?
576 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
579 rxq->state &= ~SFC_RXQ_FLUSH_FAILED;
580 rxq->state |= SFC_RXQ_FLUSHING;
583 * Wait for Rx queue flush done or failed event at least
584 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
585 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
586 * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
590 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
591 sfc_ev_qpoll(rxq->evq);
592 } while ((rxq->state & SFC_RXQ_FLUSHING) &&
593 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
595 if (rxq->state & SFC_RXQ_FLUSHING)
596 sfc_err(sa, "RxQ %u flush timed out", sw_index);
598 if (rxq->state & SFC_RXQ_FLUSH_FAILED)
599 sfc_err(sa, "RxQ %u flush failed", sw_index);
601 if (rxq->state & SFC_RXQ_FLUSHED)
602 sfc_notice(sa, "RxQ %u flushed", sw_index);
605 sa->dp_rx->qpurge(rxq->dp);
609 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
611 struct sfc_rss *rss = &sa->rss;
612 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
613 struct sfc_port *port = &sa->port;
617 * If promiscuous or all-multicast mode has been requested, setting
618 * filter for the default Rx queue might fail, in particular, while
619 * running over PCI function which is not a member of corresponding
620 * privilege groups; if this occurs, few iterations will be made to
621 * repeat this step without promiscuous and all-multicast flags set
624 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
627 else if (rc != EOPNOTSUPP)
631 sfc_warn(sa, "promiscuous mode has been requested, "
632 "but the HW rejects it");
633 sfc_warn(sa, "promiscuous mode will be disabled");
635 port->promisc = B_FALSE;
636 rc = sfc_set_rx_mode(sa);
643 if (port->allmulti) {
644 sfc_warn(sa, "all-multicast mode has been requested, "
645 "but the HW rejects it");
646 sfc_warn(sa, "all-multicast mode will be disabled");
648 port->allmulti = B_FALSE;
649 rc = sfc_set_rx_mode(sa);
660 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
662 struct sfc_port *port = &sa->port;
663 struct sfc_rxq_info *rxq_info;
668 sfc_log_init(sa, "sw_index=%u", sw_index);
670 SFC_ASSERT(sw_index < sa->rxq_count);
672 rxq_info = &sa->rxq_info[sw_index];
674 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
678 rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index));
682 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
683 &rxq->mem, rxq_info->entries,
684 0 /* not used on EF10 */, rxq_info->type_flags,
685 evq->common, &rxq->common);
687 goto fail_rx_qcreate;
689 efx_rx_qenable(rxq->common);
691 rc = sa->dp_rx->qstart(rxq->dp, evq->read_ptr);
695 rxq->state |= SFC_RXQ_STARTED;
697 if ((sw_index == 0) && !port->isolated) {
698 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
700 goto fail_mac_filter_default_rxq_set;
703 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
704 sa->eth_dev->data->rx_queue_state[sw_index] =
705 RTE_ETH_QUEUE_STATE_STARTED;
709 fail_mac_filter_default_rxq_set:
710 sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
713 sfc_rx_qflush(sa, sw_index);
723 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
725 struct sfc_rxq_info *rxq_info;
728 sfc_log_init(sa, "sw_index=%u", sw_index);
730 SFC_ASSERT(sw_index < sa->rxq_count);
732 rxq_info = &sa->rxq_info[sw_index];
735 if (rxq->state == SFC_RXQ_INITIALIZED)
737 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
739 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
740 sa->eth_dev->data->rx_queue_state[sw_index] =
741 RTE_ETH_QUEUE_STATE_STOPPED;
743 sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
746 efx_mac_filter_default_rxq_clear(sa->nic);
748 sfc_rx_qflush(sa, sw_index);
750 rxq->state = SFC_RXQ_INITIALIZED;
752 efx_rx_qdestroy(rxq->common);
754 sfc_ev_qstop(rxq->evq);
758 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
760 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
763 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
764 caps |= DEV_RX_OFFLOAD_CRC_STRIP;
765 caps |= DEV_RX_OFFLOAD_IPV4_CKSUM;
766 caps |= DEV_RX_OFFLOAD_UDP_CKSUM;
767 caps |= DEV_RX_OFFLOAD_TCP_CKSUM;
769 if (encp->enc_tunnel_encapsulations_supported &&
770 (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
771 caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
777 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
781 if (sa->dp_rx->features & SFC_DP_RX_FEAT_SCATTER)
782 caps |= DEV_RX_OFFLOAD_SCATTER;
788 sfc_rx_log_offloads(struct sfc_adapter *sa, const char *offload_group,
789 const char *verdict, uint64_t offloads)
791 unsigned long long bit;
793 while ((bit = __builtin_ffsll(offloads)) != 0) {
794 uint64_t flag = (1ULL << --bit);
796 sfc_err(sa, "Rx %s offload %s %s", offload_group,
797 rte_eth_dev_rx_offload_name(flag), verdict);
804 sfc_rx_queue_offloads_mismatch(struct sfc_adapter *sa, uint64_t requested)
806 uint64_t mandatory = sa->eth_dev->data->dev_conf.rxmode.offloads;
807 uint64_t supported = sfc_rx_get_dev_offload_caps(sa) |
808 sfc_rx_get_queue_offload_caps(sa);
809 uint64_t rejected = requested & ~supported;
810 uint64_t missing = (requested & mandatory) ^ mandatory;
811 boolean_t mismatch = B_FALSE;
814 sfc_rx_log_offloads(sa, "queue", "is unsupported", rejected);
819 sfc_rx_log_offloads(sa, "queue", "must be set", missing);
827 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
828 const struct rte_eth_rxconf *rx_conf)
830 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
831 sfc_rx_get_queue_offload_caps(sa);
834 if (rx_conf->rx_thresh.pthresh != 0 ||
835 rx_conf->rx_thresh.hthresh != 0 ||
836 rx_conf->rx_thresh.wthresh != 0) {
838 "RxQ prefetch/host/writeback thresholds are not supported");
841 if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
843 "RxQ free threshold too large: %u vs maximum %u",
844 rx_conf->rx_free_thresh, rxq_max_fill_level);
848 if (rx_conf->rx_drop_en == 0) {
849 sfc_err(sa, "RxQ drop disable is not supported");
853 if ((rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
854 DEV_RX_OFFLOAD_CHECKSUM)
855 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
857 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
858 (~rx_conf->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
859 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
861 if (sfc_rx_queue_offloads_mismatch(sa, rx_conf->offloads))
868 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
873 /* The mbuf object itself is always cache line aligned */
874 order = rte_bsf32(RTE_CACHE_LINE_SIZE);
876 /* Data offset from mbuf object start */
877 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
878 RTE_PKTMBUF_HEADROOM;
880 order = MIN(order, rte_bsf32(data_off));
886 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
888 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
889 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
890 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
892 unsigned int buf_aligned;
893 unsigned int start_alignment;
894 unsigned int end_padding_alignment;
896 /* Below it is assumed that both alignments are power of 2 */
897 SFC_ASSERT(rte_is_power_of_2(nic_align_start));
898 SFC_ASSERT(rte_is_power_of_2(nic_align_end));
901 * mbuf is always cache line aligned, double-check
902 * that it meets rx buffer start alignment requirements.
905 /* Start from mbuf pool data room size */
906 buf_size = rte_pktmbuf_data_room_size(mb_pool);
908 /* Remove headroom */
909 if (buf_size <= RTE_PKTMBUF_HEADROOM) {
911 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
912 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
915 buf_size -= RTE_PKTMBUF_HEADROOM;
917 /* Calculate guaranteed data start alignment */
918 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
920 /* Reserve space for start alignment */
921 if (buf_aligned < nic_align_start) {
922 start_alignment = nic_align_start - buf_aligned;
923 if (buf_size <= start_alignment) {
925 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
927 rte_pktmbuf_data_room_size(mb_pool),
928 RTE_PKTMBUF_HEADROOM, start_alignment);
931 buf_aligned = nic_align_start;
932 buf_size -= start_alignment;
937 /* Make sure that end padding does not write beyond the buffer */
938 if (buf_aligned < nic_align_end) {
940 * Estimate space which can be lost. If guarnteed buffer
941 * size is odd, lost space is (nic_align_end - 1). More
942 * accurate formula is below.
944 end_padding_alignment = nic_align_end -
945 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
946 if (buf_size <= end_padding_alignment) {
948 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
950 rte_pktmbuf_data_room_size(mb_pool),
951 RTE_PKTMBUF_HEADROOM, start_alignment,
952 end_padding_alignment);
955 buf_size -= end_padding_alignment;
958 * Start is aligned the same or better than end,
961 buf_size = P2ALIGN(buf_size, nic_align_end);
968 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
969 uint16_t nb_rx_desc, unsigned int socket_id,
970 const struct rte_eth_rxconf *rx_conf,
971 struct rte_mempool *mb_pool)
973 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
974 struct sfc_rss *rss = &sa->rss;
976 unsigned int rxq_entries;
977 unsigned int evq_entries;
978 unsigned int rxq_max_fill_level;
980 struct sfc_rxq_info *rxq_info;
983 struct sfc_dp_rx_qcreate_info info;
985 rc = sa->dp_rx->qsize_up_rings(nb_rx_desc, &rxq_entries, &evq_entries,
986 &rxq_max_fill_level);
988 goto fail_size_up_rings;
989 SFC_ASSERT(rxq_entries >= EFX_RXQ_MINNDESCS);
990 SFC_ASSERT(rxq_entries <= EFX_RXQ_MAXNDESCS);
991 SFC_ASSERT(rxq_entries >= nb_rx_desc);
992 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
994 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf);
998 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1000 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
1006 if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) &&
1007 (~rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)) {
1008 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool "
1009 "object size is too small", sw_index);
1010 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
1011 "PDU size %u plus Rx prefix %u bytes",
1012 sw_index, buf_size, (unsigned int)sa->port.pdu,
1013 encp->enc_rx_prefix_size);
1018 SFC_ASSERT(sw_index < sa->rxq_count);
1019 rxq_info = &sa->rxq_info[sw_index];
1021 SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1022 rxq_info->entries = rxq_entries;
1023 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1024 rxq_info->type_flags =
1025 (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) ?
1026 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1028 if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1029 (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS))
1030 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1032 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1033 evq_entries, socket_id, &evq);
1038 rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE,
1041 goto fail_rxq_alloc;
1043 rxq_info->rxq = rxq;
1046 rxq->hw_index = sw_index;
1047 rxq->refill_threshold =
1048 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK);
1049 rxq->refill_mb_pool = mb_pool;
1051 rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries),
1052 socket_id, &rxq->mem);
1054 goto fail_dma_alloc;
1056 memset(&info, 0, sizeof(info));
1057 info.refill_mb_pool = rxq->refill_mb_pool;
1058 info.max_fill_level = rxq_max_fill_level;
1059 info.refill_threshold = rxq->refill_threshold;
1060 info.buf_size = buf_size;
1061 info.batch_max = encp->enc_rx_batch_max;
1062 info.prefix_size = encp->enc_rx_prefix_size;
1064 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0)
1065 info.flags |= SFC_RXQ_FLAG_RSS_HASH;
1067 info.rxq_entries = rxq_info->entries;
1068 info.rxq_hw_ring = rxq->mem.esm_base;
1069 info.evq_entries = evq_entries;
1070 info.evq_hw_ring = evq->mem.esm_base;
1071 info.hw_index = rxq->hw_index;
1072 info.mem_bar = sa->mem_bar.esb_base;
1073 info.vi_window_shift = encp->enc_vi_window_shift;
1075 rc = sa->dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1076 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1077 socket_id, &info, &rxq->dp);
1079 goto fail_dp_rx_qcreate;
1081 evq->dp_rxq = rxq->dp;
1083 rxq->state = SFC_RXQ_INITIALIZED;
1085 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1090 sfc_dma_free(sa, &rxq->mem);
1093 rxq_info->rxq = NULL;
1100 rxq_info->entries = 0;
1104 sfc_log_init(sa, "failed %d", rc);
1109 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
1111 struct sfc_rxq_info *rxq_info;
1112 struct sfc_rxq *rxq;
1114 SFC_ASSERT(sw_index < sa->rxq_count);
1116 rxq_info = &sa->rxq_info[sw_index];
1118 rxq = rxq_info->rxq;
1119 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
1121 sa->dp_rx->qdestroy(rxq->dp);
1124 rxq_info->rxq = NULL;
1125 rxq_info->entries = 0;
1127 sfc_dma_free(sa, &rxq->mem);
1129 sfc_ev_qfini(rxq->evq);
1136 * Mapping between RTE RSS hash functions and their EFX counterparts.
1138 struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1139 { ETH_RSS_NONFRAG_IPV4_TCP,
1140 EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1141 { ETH_RSS_NONFRAG_IPV4_UDP,
1142 EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1143 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1144 EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1145 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1146 EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1147 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1148 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1149 EFX_RX_HASH(IPV4, 2TUPLE) },
1150 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1152 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1153 EFX_RX_HASH(IPV6, 2TUPLE) }
1156 static efx_rx_hash_type_t
1157 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1158 unsigned int *hash_type_flags_supported,
1159 unsigned int nb_hash_type_flags_supported)
1161 efx_rx_hash_type_t hash_type_masked = 0;
1164 for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1165 unsigned int class_tuple_lbn[] = {
1166 EFX_RX_CLASS_IPV4_TCP_LBN,
1167 EFX_RX_CLASS_IPV4_UDP_LBN,
1168 EFX_RX_CLASS_IPV4_LBN,
1169 EFX_RX_CLASS_IPV6_TCP_LBN,
1170 EFX_RX_CLASS_IPV6_UDP_LBN,
1171 EFX_RX_CLASS_IPV6_LBN
1174 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1175 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1178 tuple_mask <<= class_tuple_lbn[j];
1179 flag = hash_type & tuple_mask;
1181 if (flag == hash_type_flags_supported[i])
1182 hash_type_masked |= flag;
1186 return hash_type_masked;
1190 sfc_rx_hash_init(struct sfc_adapter *sa)
1192 struct sfc_rss *rss = &sa->rss;
1193 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1194 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1195 efx_rx_hash_alg_t alg;
1196 unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1197 unsigned int nb_flags_supp;
1198 struct sfc_rss_hf_rte_to_efx *hf_map;
1199 struct sfc_rss_hf_rte_to_efx *entry;
1200 efx_rx_hash_type_t efx_hash_types;
1204 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1205 alg = EFX_RX_HASHALG_TOEPLITZ;
1206 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1207 alg = EFX_RX_HASHALG_PACKED_STREAM;
1211 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1216 hf_map = rte_calloc_socket("sfc-rss-hf-map",
1217 RTE_DIM(sfc_rss_hf_map),
1218 sizeof(*hf_map), 0, sa->socket_id);
1224 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1225 efx_rx_hash_type_t ht;
1227 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1228 flags_supp, nb_flags_supp);
1230 entry->rte = sfc_rss_hf_map[i].rte;
1232 efx_hash_types |= ht;
1237 rss->hash_alg = alg;
1238 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1239 rss->hf_map = hf_map;
1240 rss->hash_types = efx_hash_types;
1246 sfc_rx_hash_fini(struct sfc_adapter *sa)
1248 struct sfc_rss *rss = &sa->rss;
1250 rte_free(rss->hf_map);
1254 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1255 efx_rx_hash_type_t *efx)
1257 struct sfc_rss *rss = &sa->rss;
1258 efx_rx_hash_type_t hash_types = 0;
1261 for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1262 uint64_t rte_mask = rss->hf_map[i].rte;
1264 if ((rte & rte_mask) != 0) {
1266 hash_types |= rss->hf_map[i].efx;
1271 sfc_err(sa, "unsupported hash functions requested");
1281 sfc_rx_hf_efx_to_rte(struct sfc_adapter *sa, efx_rx_hash_type_t efx)
1283 struct sfc_rss *rss = &sa->rss;
1287 for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1288 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1290 if ((efx & hash_type) == hash_type)
1291 rte |= rss->hf_map[i].rte;
1298 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1299 struct rte_eth_rss_conf *conf)
1301 struct sfc_rss *rss = &sa->rss;
1302 efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1303 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(sa, efx_hash_types);
1306 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1307 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1308 conf->rss_key != NULL)
1312 if (conf->rss_hf != 0) {
1313 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1318 if (conf->rss_key != NULL) {
1319 if (conf->rss_key_len != sizeof(rss->key)) {
1320 sfc_err(sa, "RSS key size is wrong (should be %lu)",
1324 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1327 rss->hash_types = efx_hash_types;
1333 sfc_rx_rss_config(struct sfc_adapter *sa)
1335 struct sfc_rss *rss = &sa->rss;
1338 if (rss->channels > 0) {
1339 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1340 rss->hash_alg, rss->hash_types,
1345 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1346 rss->key, sizeof(rss->key));
1350 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1351 rss->tbl, RTE_DIM(rss->tbl));
1359 sfc_rx_start(struct sfc_adapter *sa)
1361 unsigned int sw_index;
1364 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1366 rc = efx_rx_init(sa->nic);
1370 rc = sfc_rx_rss_config(sa);
1372 goto fail_rss_config;
1374 for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1375 if ((!sa->rxq_info[sw_index].deferred_start ||
1376 sa->rxq_info[sw_index].deferred_started)) {
1377 rc = sfc_rx_qstart(sa, sw_index);
1379 goto fail_rx_qstart;
1386 while (sw_index-- > 0)
1387 sfc_rx_qstop(sa, sw_index);
1390 efx_rx_fini(sa->nic);
1393 sfc_log_init(sa, "failed %d", rc);
1398 sfc_rx_stop(struct sfc_adapter *sa)
1400 unsigned int sw_index;
1402 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1404 sw_index = sa->rxq_count;
1405 while (sw_index-- > 0) {
1406 if (sa->rxq_info[sw_index].rxq != NULL)
1407 sfc_rx_qstop(sa, sw_index);
1410 efx_rx_fini(sa->nic);
1414 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1416 struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];
1417 unsigned int max_entries;
1419 max_entries = EFX_RXQ_MAXNDESCS;
1420 SFC_ASSERT(rte_is_power_of_2(max_entries));
1422 rxq_info->max_entries = max_entries;
1428 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1430 struct sfc_rss *rss = &sa->rss;
1431 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1432 sfc_rx_get_queue_offload_caps(sa);
1433 uint64_t offloads_rejected = rxmode->offloads & ~offloads_supported;
1436 switch (rxmode->mq_mode) {
1437 case ETH_MQ_RX_NONE:
1438 /* No special checks are required */
1441 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1442 sfc_err(sa, "RSS is not available");
1447 sfc_err(sa, "Rx multi-queue mode %u not supported",
1452 if (offloads_rejected) {
1453 sfc_rx_log_offloads(sa, "device", "is unsupported",
1458 if (~rxmode->offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
1459 sfc_warn(sa, "FCS stripping cannot be disabled - always on");
1460 rxmode->offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
1461 rxmode->hw_strip_crc = 1;
1468 * Destroy excess queues that are no longer needed after reconfiguration
1469 * or complete close.
1472 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1476 SFC_ASSERT(nb_rx_queues <= sa->rxq_count);
1478 sw_index = sa->rxq_count;
1479 while (--sw_index >= (int)nb_rx_queues) {
1480 if (sa->rxq_info[sw_index].rxq != NULL)
1481 sfc_rx_qfini(sa, sw_index);
1484 sa->rxq_count = nb_rx_queues;
1488 * Initialize Rx subsystem.
1490 * Called at device (re)configuration stage when number of receive queues is
1491 * specified together with other device level receive configuration.
1493 * It should be used to allocate NUMA-unaware resources.
1496 sfc_rx_configure(struct sfc_adapter *sa)
1498 struct sfc_rss *rss = &sa->rss;
1499 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1500 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1503 sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1504 nb_rx_queues, sa->rxq_count);
1506 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1508 goto fail_check_mode;
1510 if (nb_rx_queues == sa->rxq_count)
1513 if (sa->rxq_info == NULL) {
1515 sa->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1516 sizeof(sa->rxq_info[0]), 0,
1518 if (sa->rxq_info == NULL)
1519 goto fail_rxqs_alloc;
1521 struct sfc_rxq_info *new_rxq_info;
1523 if (nb_rx_queues < sa->rxq_count)
1524 sfc_rx_fini_queues(sa, nb_rx_queues);
1528 rte_realloc(sa->rxq_info,
1529 nb_rx_queues * sizeof(sa->rxq_info[0]), 0);
1530 if (new_rxq_info == NULL && nb_rx_queues > 0)
1531 goto fail_rxqs_realloc;
1533 sa->rxq_info = new_rxq_info;
1534 if (nb_rx_queues > sa->rxq_count)
1535 memset(&sa->rxq_info[sa->rxq_count], 0,
1536 (nb_rx_queues - sa->rxq_count) *
1537 sizeof(sa->rxq_info[0]));
1540 while (sa->rxq_count < nb_rx_queues) {
1541 rc = sfc_rx_qinit_info(sa, sa->rxq_count);
1543 goto fail_rx_qinit_info;
1548 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1549 MIN(sa->rxq_count, EFX_MAXRSS) : 0;
1551 if (rss->channels > 0) {
1552 struct rte_eth_rss_conf *adv_conf_rss;
1553 unsigned int sw_index;
1555 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1556 rss->tbl[sw_index] = sw_index % rss->channels;
1558 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1559 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1561 goto fail_rx_process_adv_conf_rss;
1567 fail_rx_process_adv_conf_rss:
1574 sfc_log_init(sa, "failed %d", rc);
1579 * Shutdown Rx subsystem.
1581 * Called at device close stage, for example, before device shutdown.
1584 sfc_rx_close(struct sfc_adapter *sa)
1586 struct sfc_rss *rss = &sa->rss;
1588 sfc_rx_fini_queues(sa, 0);
1592 rte_free(sa->rxq_info);
1593 sa->rxq_info = NULL;