drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2021 Xilinx, Inc.
   4  * Copyright(c) 2016-2019 Solarflare Communications Inc.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_mae_counter.h"
  20 #include "sfc_kvargs.h"
  21 #include "sfc_tweak.h"
  22
  23 /*
  24  * Maximum number of Rx queue flush attempt in the case of failure or
  25  * flush timeout
  26  */
  27 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  28
  29 /*
  30  * Time to wait between event queue polling attempts when waiting for Rx
  31  * queue flush done or failed events.
  32  */
  33 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  34
  35 /*
  36  * Maximum number of event queue polling attempts when waiting for Rx queue
  37  * flush done or failed events. It defines Rx queue flush attempt timeout
  38  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  39  */
  40 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  41
  42 void
  43 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
  44 {
  45         rxq_info->state |= SFC_RXQ_FLUSHED;
  46         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  47 }
  48
  49 void
  50 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
  51 {
  52         rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
  53         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  54 }
  55
  56 /* This returns the running counter, which is not bounded by ring size */
  57 unsigned int
  58 sfc_rx_get_pushed(struct sfc_adapter *sa, struct sfc_dp_rxq *dp_rxq)
  59 {
  60         SFC_ASSERT(sa->priv.dp_rx->get_pushed != NULL);
  61
  62         return sa->priv.dp_rx->get_pushed(dp_rxq);
  63 }
  64
  65 static int
  66 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq)
  67 {
  68         int rc = 0;
  69
  70         if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) {
  71                 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr);
  72                 if (rc == 0)
  73                         rxq->evq->read_ptr_primed = rxq->evq->read_ptr;
  74         }
  75         return rc;
  76 }
  77
  78 static void
  79 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  80 {
  81         unsigned int free_space;
  82         unsigned int bulks;
  83         void *objs[SFC_RX_REFILL_BULK];
  84         efsys_dma_addr_t addr[RTE_DIM(objs)];
  85         unsigned int added = rxq->added;
  86         unsigned int id;
  87         unsigned int i;
  88         struct sfc_efx_rx_sw_desc *rxd;
  89         struct rte_mbuf *m;
  90         uint16_t port_id = rxq->dp.dpq.port_id;
  91
  92         free_space = rxq->max_fill_level - (added - rxq->completed);
  93
  94         if (free_space < rxq->refill_threshold)
  95                 return;
  96
  97         bulks = free_space / RTE_DIM(objs);
  98         /* refill_threshold guarantees that bulks is positive */
  99         SFC_ASSERT(bulks > 0);
 100
 101         id = added & rxq->ptr_mask;
 102         do {
 103                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
 104                                                   RTE_DIM(objs)) < 0)) {
 105                         /*
 106                          * It is hardly a safe way to increment counter
 107                          * from different contexts, but all PMDs do it.
 108                          */
 109                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
 110                                 RTE_DIM(objs);
 111                         /* Return if we have posted nothing yet */
 112                         if (added == rxq->added)
 113                                 return;
 114                         /* Push posted */
 115                         break;
 116                 }
 117
 118                 for (i = 0; i < RTE_DIM(objs);
 119                      ++i, id = (id + 1) & rxq->ptr_mask) {
 120                         m = objs[i];
 121
 122                         __rte_mbuf_raw_sanity_check(m);
 123
 124                         rxd = &rxq->sw_desc[id];
 125                         rxd->mbuf = m;
 126
 127                         m->data_off = RTE_PKTMBUF_HEADROOM;
 128                         m->port = port_id;
 129
 130                         addr[i] = rte_pktmbuf_iova(m);
 131                 }
 132
 133                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 134                              RTE_DIM(objs), rxq->completed, added);
 135                 added += RTE_DIM(objs);
 136         } while (--bulks > 0);
 137
 138         SFC_ASSERT(added != rxq->added);
 139         rxq->added = added;
 140         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 141 }
 142
 143 static uint64_t
 144 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 145 {
 146         uint64_t mbuf_flags = 0;
 147
 148         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 149         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 150                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 151                 break;
 152         case EFX_PKT_IPV4:
 153                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 154                 break;
 155         default:
 156                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 157                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 158                            PKT_RX_IP_CKSUM_UNKNOWN);
 159                 break;
 160         }
 161
 162         switch ((desc_flags &
 163                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 164         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 165         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 166                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 167                 break;
 168         case EFX_PKT_TCP:
 169         case EFX_PKT_UDP:
 170                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 171                 break;
 172         default:
 173                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 174                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 175                            PKT_RX_L4_CKSUM_UNKNOWN);
 176                 break;
 177         }
 178
 179         return mbuf_flags;
 180 }
 181
 182 static uint32_t
 183 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 184 {
 185         return RTE_PTYPE_L2_ETHER |
 186                 ((desc_flags & EFX_PKT_IPV4) ?
 187                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 188                 ((desc_flags & EFX_PKT_IPV6) ?
 189                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 190                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 191                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 192 }
 193
 194 static const uint32_t *
 195 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 196 {
 197         static const uint32_t ptypes[] = {
 198                 RTE_PTYPE_L2_ETHER,
 199                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 200                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 201                 RTE_PTYPE_L4_TCP,
 202                 RTE_PTYPE_L4_UDP,
 203                 RTE_PTYPE_UNKNOWN
 204         };
 205
 206         return ptypes;
 207 }
 208
 209 static void
 210 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 211                         struct rte_mbuf *m)
 212 {
 213         uint8_t *mbuf_data;
 214
 215
 216         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 217                 return;
 218
 219         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 220
 221         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 222                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 223                                                       EFX_RX_HASHALG_TOEPLITZ,
 224                                                       mbuf_data);
 225
 226                 m->ol_flags |= PKT_RX_RSS_HASH;
 227         }
 228 }
 229
 230 static uint16_t
 231 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 232 {
 233         struct sfc_dp_rxq *dp_rxq = rx_queue;
 234         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 235         unsigned int completed;
 236         unsigned int prefix_size = rxq->prefix_size;
 237         unsigned int done_pkts = 0;
 238         boolean_t discard_next = B_FALSE;
 239         struct rte_mbuf *scatter_pkt = NULL;
 240
 241         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 242                 return 0;
 243
 244         sfc_ev_qpoll(rxq->evq);
 245
 246         completed = rxq->completed;
 247         while (completed != rxq->pending && done_pkts < nb_pkts) {
 248                 unsigned int id;
 249                 struct sfc_efx_rx_sw_desc *rxd;
 250                 struct rte_mbuf *m;
 251                 unsigned int seg_len;
 252                 unsigned int desc_flags;
 253
 254                 id = completed++ & rxq->ptr_mask;
 255                 rxd = &rxq->sw_desc[id];
 256                 m = rxd->mbuf;
 257                 desc_flags = rxd->flags;
 258
 259                 if (discard_next)
 260                         goto discard;
 261
 262                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 263                         goto discard;
 264
 265                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 266                         uint16_t tmp_size;
 267                         int rc __rte_unused;
 268
 269                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 270                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 271                         SFC_ASSERT(rc == 0);
 272                         seg_len = tmp_size;
 273                 } else {
 274                         seg_len = rxd->size - prefix_size;
 275                 }
 276
 277                 rte_pktmbuf_data_len(m) = seg_len;
 278                 rte_pktmbuf_pkt_len(m) = seg_len;
 279
 280                 if (scatter_pkt != NULL) {
 281                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 282                                 rte_pktmbuf_free(scatter_pkt);
 283                                 goto discard;
 284                         }
 285                         /* The packet to deliver */
 286                         m = scatter_pkt;
 287                 }
 288
 289                 if (desc_flags & EFX_PKT_CONT) {
 290                         /* The packet is scattered, more fragments to come */
 291                         scatter_pkt = m;
 292                         /* Further fragments have no prefix */
 293                         prefix_size = 0;
 294                         continue;
 295                 }
 296
 297                 /* Scattered packet is done */
 298                 scatter_pkt = NULL;
 299                 /* The first fragment of the packet has prefix */
 300                 prefix_size = rxq->prefix_size;
 301
 302                 m->ol_flags =
 303                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 304                 m->packet_type =
 305                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 306
 307                 /*
 308                  * Extract RSS hash from the packet prefix and
 309                  * set the corresponding field (if needed and possible)
 310                  */
 311                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 312
 313                 m->data_off += prefix_size;
 314
 315                 *rx_pkts++ = m;
 316                 done_pkts++;
 317                 continue;
 318
 319 discard:
 320                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 321                 rte_mbuf_raw_free(m);
 322                 rxd->mbuf = NULL;
 323         }
 324
 325         /* pending is only moved when entire packet is received */
 326         SFC_ASSERT(scatter_pkt == NULL);
 327
 328         rxq->completed = completed;
 329
 330         sfc_efx_rx_qrefill(rxq);
 331
 332         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN)
 333                 sfc_efx_rx_qprime(rxq);
 334
 335         return done_pkts;
 336 }
 337
 338 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 339 static unsigned int
 340 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 341 {
 342         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 343
 344         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 345                 return 0;
 346
 347         sfc_ev_qpoll(rxq->evq);
 348
 349         return rxq->pending - rxq->completed;
 350 }
 351
 352 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 353 static int
 354 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 355 {
 356         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 357
 358         if (unlikely(offset > rxq->ptr_mask))
 359                 return -EINVAL;
 360
 361         /*
 362          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 363          * it is required for the queue to be running, but the
 364          * check is omitted because API design assumes that it
 365          * is the duty of the caller to satisfy all conditions
 366          */
 367         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 368                    SFC_EFX_RXQ_FLAG_RUNNING);
 369         sfc_ev_qpoll(rxq->evq);
 370
 371         /*
 372          * There is a handful of reserved entries in the ring,
 373          * but an explicit check whether the offset points to
 374          * a reserved entry is neglected since the two checks
 375          * below rely on the figures which take the HW limits
 376          * into account and thus if an entry is reserved, the
 377          * checks will fail and UNAVAIL code will be returned
 378          */
 379
 380         if (offset < (rxq->pending - rxq->completed))
 381                 return RTE_ETH_RX_DESC_DONE;
 382
 383         if (offset < (rxq->added - rxq->completed))
 384                 return RTE_ETH_RX_DESC_AVAIL;
 385
 386         return RTE_ETH_RX_DESC_UNAVAIL;
 387 }
 388
 389 boolean_t
 390 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size,
 391                      boolean_t rx_scatter_enabled, uint32_t rx_scatter_max,
 392                      const char **error)
 393 {
 394         uint32_t effective_rx_scatter_max;
 395         uint32_t rx_scatter_bufs;
 396
 397         effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1;
 398         rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size);
 399
 400         if (rx_scatter_bufs > effective_rx_scatter_max) {
 401                 if (rx_scatter_enabled)
 402                         *error = "Possible number of Rx scatter buffers exceeds maximum number";
 403                 else
 404                         *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small";
 405                 return B_FALSE;
 406         }
 407
 408         return B_TRUE;
 409 }
 410
 411 /** Get Rx datapath ops by the datapath RxQ handle */
 412 const struct sfc_dp_rx *
 413 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 414 {
 415         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 416         struct rte_eth_dev *eth_dev;
 417         struct sfc_adapter_priv *sap;
 418
 419         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 420         eth_dev = &rte_eth_devices[dpq->port_id];
 421
 422         sap = sfc_adapter_priv_by_eth_dev(eth_dev);
 423
 424         return sap->dp_rx;
 425 }
 426
 427 struct sfc_rxq_info *
 428 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 429 {
 430         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 431         struct rte_eth_dev *eth_dev;
 432         struct sfc_adapter_shared *sas;
 433
 434         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 435         eth_dev = &rte_eth_devices[dpq->port_id];
 436
 437         sas = sfc_adapter_shared_by_eth_dev(eth_dev);
 438
 439         SFC_ASSERT(dpq->queue_id < sas->rxq_count);
 440         return &sas->rxq_info[dpq->queue_id];
 441 }
 442
 443 struct sfc_rxq *
 444 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 445 {
 446         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 447         struct rte_eth_dev *eth_dev;
 448         struct sfc_adapter *sa;
 449
 450         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 451         eth_dev = &rte_eth_devices[dpq->port_id];
 452
 453         sa = sfc_adapter_by_eth_dev(eth_dev);
 454
 455         SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count);
 456         return &sa->rxq_ctrl[dpq->queue_id];
 457 }
 458
 459 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 460 static int
 461 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 462                           __rte_unused struct sfc_dp_rx_hw_limits *limits,
 463                           __rte_unused struct rte_mempool *mb_pool,
 464                           unsigned int *rxq_entries,
 465                           unsigned int *evq_entries,
 466                           unsigned int *rxq_max_fill_level)
 467 {
 468         *rxq_entries = nb_rx_desc;
 469         *evq_entries = nb_rx_desc;
 470         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 471         return 0;
 472 }
 473
 474 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 475 static int
 476 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 477                    const struct rte_pci_addr *pci_addr, int socket_id,
 478                    const struct sfc_dp_rx_qcreate_info *info,
 479                    struct sfc_dp_rxq **dp_rxqp)
 480 {
 481         struct sfc_efx_rxq *rxq;
 482         int rc;
 483
 484         rc = ENOMEM;
 485         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 486                                  RTE_CACHE_LINE_SIZE, socket_id);
 487         if (rxq == NULL)
 488                 goto fail_rxq_alloc;
 489
 490         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 491
 492         rc = ENOMEM;
 493         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 494                                          info->rxq_entries,
 495                                          sizeof(*rxq->sw_desc),
 496                                          RTE_CACHE_LINE_SIZE, socket_id);
 497         if (rxq->sw_desc == NULL)
 498                 goto fail_desc_alloc;
 499
 500         /* efx datapath is bound to efx control path */
 501         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 502         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 503                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 504         rxq->ptr_mask = info->rxq_entries - 1;
 505         rxq->batch_max = info->batch_max;
 506         rxq->prefix_size = info->prefix_size;
 507         rxq->max_fill_level = info->max_fill_level;
 508         rxq->refill_threshold = info->refill_threshold;
 509         rxq->buf_size = info->buf_size;
 510         rxq->refill_mb_pool = info->refill_mb_pool;
 511
 512         *dp_rxqp = &rxq->dp;
 513         return 0;
 514
 515 fail_desc_alloc:
 516         rte_free(rxq);
 517
 518 fail_rxq_alloc:
 519         return rc;
 520 }
 521
 522 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 523 static void
 524 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 525 {
 526         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 527
 528         rte_free(rxq->sw_desc);
 529         rte_free(rxq);
 530 }
 531
 532
 533 /* Use qstop and qstart functions in the case of qstart failure */
 534 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 535 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 536
 537
 538 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 539 static int
 540 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 541                   __rte_unused unsigned int evq_read_ptr,
 542                   const efx_rx_prefix_layout_t *pinfo)
 543 {
 544         /* libefx-based datapath is specific to libefx-based PMD */
 545         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 546         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 547         int rc;
 548
 549         /*
 550          * libefx API is used to extract information from Rx prefix and
 551          * it guarantees consistency. Just do length check to ensure
 552          * that we reserved space in Rx buffers correctly.
 553          */
 554         if (rxq->prefix_size != pinfo->erpl_length)
 555                 return ENOTSUP;
 556
 557         rxq->common = crxq->common;
 558
 559         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 560
 561         sfc_efx_rx_qrefill(rxq);
 562
 563         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 564
 565         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) {
 566                 rc = sfc_efx_rx_qprime(rxq);
 567                 if (rc != 0)
 568                         goto fail_rx_qprime;
 569         }
 570
 571         return 0;
 572
 573 fail_rx_qprime:
 574         sfc_efx_rx_qstop(dp_rxq, NULL);
 575         sfc_efx_rx_qpurge(dp_rxq);
 576         return rc;
 577 }
 578
 579 static void
 580 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 581                  __rte_unused unsigned int *evq_read_ptr)
 582 {
 583         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 584
 585         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 586
 587         /* libefx-based datapath is bound to libefx-based PMD and uses
 588          * event queue structure directly. So, there is no necessity to
 589          * return EvQ read pointer.
 590          */
 591 }
 592
 593 static void
 594 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 595 {
 596         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 597         unsigned int i;
 598         struct sfc_efx_rx_sw_desc *rxd;
 599
 600         for (i = rxq->completed; i != rxq->added; ++i) {
 601                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 602                 rte_mbuf_raw_free(rxd->mbuf);
 603                 rxd->mbuf = NULL;
 604                 /* Packed stream relies on 0 in inactive SW desc.
 605                  * Rx queue stop is not performance critical, so
 606                  * there is no harm to do it always.
 607                  */
 608                 rxd->flags = 0;
 609                 rxd->size = 0;
 610         }
 611
 612         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 613 }
 614
 615 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable;
 616 static int
 617 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
 618 {
 619         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 620         int rc = 0;
 621
 622         rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN;
 623         if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) {
 624                 rc = sfc_efx_rx_qprime(rxq);
 625                 if (rc != 0)
 626                         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 627         }
 628         return rc;
 629 }
 630
 631 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable;
 632 static int
 633 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
 634 {
 635         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 636
 637         /* Cannot disarm, just disable rearm */
 638         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 639         return 0;
 640 }
 641
 642 struct sfc_dp_rx sfc_efx_rx = {
 643         .dp = {
 644                 .name           = SFC_KVARG_DATAPATH_EFX,
 645                 .type           = SFC_DP_RX,
 646                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_RX_EFX,
 647         },
 648         .features               = SFC_DP_RX_FEAT_INTR,
 649         .dev_offload_capa       = DEV_RX_OFFLOAD_CHECKSUM |
 650                                   DEV_RX_OFFLOAD_RSS_HASH,
 651         .queue_offload_capa     = DEV_RX_OFFLOAD_SCATTER,
 652         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 653         .qcreate                = sfc_efx_rx_qcreate,
 654         .qdestroy               = sfc_efx_rx_qdestroy,
 655         .qstart                 = sfc_efx_rx_qstart,
 656         .qstop                  = sfc_efx_rx_qstop,
 657         .qpurge                 = sfc_efx_rx_qpurge,
 658         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 659         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 660         .qdesc_status           = sfc_efx_rx_qdesc_status,
 661         .intr_enable            = sfc_efx_rx_intr_enable,
 662         .intr_disable           = sfc_efx_rx_intr_disable,
 663         .pkt_burst              = sfc_efx_recv_pkts,
 664 };
 665
 666 static void
 667 sfc_rx_qflush(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 668 {
 669         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 670         sfc_ethdev_qid_t ethdev_qid;
 671         struct sfc_rxq_info *rxq_info;
 672         struct sfc_rxq *rxq;
 673         unsigned int retry_count;
 674         unsigned int wait_count;
 675         int rc;
 676
 677         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 678         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 679         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 680
 681         rxq = &sa->rxq_ctrl[sw_index];
 682
 683         /*
 684          * Retry Rx queue flushing in the case of flush failed or
 685          * timeout. In the worst case it can delay for 6 seconds.
 686          */
 687         for (retry_count = 0;
 688              ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
 689              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 690              ++retry_count) {
 691                 rc = efx_rx_qflush(rxq->common);
 692                 if (rc != 0) {
 693                         rxq_info->state |= (rc == EALREADY) ?
 694                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 695                         break;
 696                 }
 697                 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
 698                 rxq_info->state |= SFC_RXQ_FLUSHING;
 699
 700                 /*
 701                  * Wait for Rx queue flush done or failed event at least
 702                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 703                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 704                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 705                  */
 706                 wait_count = 0;
 707                 do {
 708                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 709                         sfc_ev_qpoll(rxq->evq);
 710                 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
 711                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 712
 713                 if (rxq_info->state & SFC_RXQ_FLUSHING)
 714                         sfc_err(sa, "RxQ %d (internal %u) flush timed out",
 715                                 ethdev_qid, sw_index);
 716
 717                 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
 718                         sfc_err(sa, "RxQ %d (internal %u) flush failed",
 719                                 ethdev_qid, sw_index);
 720
 721                 if (rxq_info->state & SFC_RXQ_FLUSHED)
 722                         sfc_notice(sa, "RxQ %d (internal %u) flushed",
 723                                    ethdev_qid, sw_index);
 724         }
 725
 726         sa->priv.dp_rx->qpurge(rxq_info->dp);
 727 }
 728
 729 static int
 730 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 731 {
 732         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
 733         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 734         struct sfc_port *port = &sa->port;
 735         int rc;
 736
 737         /*
 738          * If promiscuous or all-multicast mode has been requested, setting
 739          * filter for the default Rx queue might fail, in particular, while
 740          * running over PCI function which is not a member of corresponding
 741          * privilege groups; if this occurs, few iterations will be made to
 742          * repeat this step without promiscuous and all-multicast flags set
 743          */
 744 retry:
 745         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 746         if (rc == 0)
 747                 return 0;
 748         else if (rc != EOPNOTSUPP)
 749                 return rc;
 750
 751         if (port->promisc) {
 752                 sfc_warn(sa, "promiscuous mode has been requested, "
 753                              "but the HW rejects it");
 754                 sfc_warn(sa, "promiscuous mode will be disabled");
 755
 756                 port->promisc = B_FALSE;
 757                 sa->eth_dev->data->promiscuous = 0;
 758                 rc = sfc_set_rx_mode_unchecked(sa);
 759                 if (rc != 0)
 760                         return rc;
 761
 762                 goto retry;
 763         }
 764
 765         if (port->allmulti) {
 766                 sfc_warn(sa, "all-multicast mode has been requested, "
 767                              "but the HW rejects it");
 768                 sfc_warn(sa, "all-multicast mode will be disabled");
 769
 770                 port->allmulti = B_FALSE;
 771                 sa->eth_dev->data->all_multicast = 0;
 772                 rc = sfc_set_rx_mode_unchecked(sa);
 773                 if (rc != 0)
 774                         return rc;
 775
 776                 goto retry;
 777         }
 778
 779         return rc;
 780 }
 781
 782 int
 783 sfc_rx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 784 {
 785         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 786         sfc_ethdev_qid_t ethdev_qid;
 787         struct sfc_rxq_info *rxq_info;
 788         struct sfc_rxq *rxq;
 789         struct sfc_evq *evq;
 790         efx_rx_prefix_layout_t pinfo;
 791         int rc;
 792
 793         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 794         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 795
 796         sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
 797
 798         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 799         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
 800
 801         rxq = &sa->rxq_ctrl[sw_index];
 802         evq = rxq->evq;
 803
 804         rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index));
 805         if (rc != 0)
 806                 goto fail_ev_qstart;
 807
 808         switch (rxq_info->type) {
 809         case EFX_RXQ_TYPE_DEFAULT:
 810                 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 811                         rxq->buf_size,
 812                         &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
 813                         rxq_info->type_flags, evq->common, &rxq->common);
 814                 break;
 815         case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
 816                 struct rte_mempool *mp = rxq_info->refill_mb_pool;
 817                 struct rte_mempool_info mp_info;
 818
 819                 rc = rte_mempool_ops_get_info(mp, &mp_info);
 820                 if (rc != 0) {
 821                         /* Positive errno is used in the driver */
 822                         rc = -rc;
 823                         goto fail_mp_get_info;
 824                 }
 825                 if (mp_info.contig_block_size <= 0) {
 826                         rc = EINVAL;
 827                         goto fail_bad_contig_block_size;
 828                 }
 829                 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
 830                         mp_info.contig_block_size, rxq->buf_size,
 831                         mp->header_size + mp->elt_size + mp->trailer_size,
 832                         sa->rxd_wait_timeout_ns,
 833                         &rxq->mem, rxq_info->entries, rxq_info->type_flags,
 834                         evq->common, &rxq->common);
 835                 break;
 836         }
 837         default:
 838                 rc = ENOTSUP;
 839         }
 840         if (rc != 0)
 841                 goto fail_rx_qcreate;
 842
 843         rc = efx_rx_prefix_get_layout(rxq->common, &pinfo);
 844         if (rc != 0)
 845                 goto fail_prefix_get_layout;
 846
 847         efx_rx_qenable(rxq->common);
 848
 849         rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr, &pinfo);
 850         if (rc != 0)
 851                 goto fail_dp_qstart;
 852
 853         rxq_info->state |= SFC_RXQ_STARTED;
 854
 855         if (ethdev_qid == 0 && !sfc_sa2shared(sa)->isolated) {
 856                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 857                 if (rc != 0)
 858                         goto fail_mac_filter_default_rxq_set;
 859         }
 860
 861         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 862         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
 863                 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
 864                         RTE_ETH_QUEUE_STATE_STARTED;
 865
 866         return 0;
 867
 868 fail_mac_filter_default_rxq_set:
 869         sfc_rx_qflush(sa, sw_index);
 870         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 871         rxq_info->state = SFC_RXQ_INITIALIZED;
 872
 873 fail_dp_qstart:
 874         efx_rx_qdestroy(rxq->common);
 875
 876 fail_prefix_get_layout:
 877 fail_rx_qcreate:
 878 fail_bad_contig_block_size:
 879 fail_mp_get_info:
 880         sfc_ev_qstop(evq);
 881
 882 fail_ev_qstart:
 883         return rc;
 884 }
 885
 886 void
 887 sfc_rx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 888 {
 889         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 890         sfc_ethdev_qid_t ethdev_qid;
 891         struct sfc_rxq_info *rxq_info;
 892         struct sfc_rxq *rxq;
 893
 894         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 895         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 896
 897         sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
 898
 899         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 900
 901         if (rxq_info->state == SFC_RXQ_INITIALIZED)
 902                 return;
 903         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 904
 905         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 906         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
 907                 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
 908                         RTE_ETH_QUEUE_STATE_STOPPED;
 909
 910         rxq = &sa->rxq_ctrl[sw_index];
 911         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 912
 913         if (ethdev_qid == 0)
 914                 efx_mac_filter_default_rxq_clear(sa->nic);
 915
 916         sfc_rx_qflush(sa, sw_index);
 917
 918         rxq_info->state = SFC_RXQ_INITIALIZED;
 919
 920         efx_rx_qdestroy(rxq->common);
 921
 922         sfc_ev_qstop(rxq->evq);
 923 }
 924
 925 static uint64_t
 926 sfc_rx_get_offload_mask(struct sfc_adapter *sa)
 927 {
 928         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 929         uint64_t no_caps = 0;
 930
 931         if (encp->enc_tunnel_encapsulations_supported == 0)
 932                 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 933
 934         return ~no_caps;
 935 }
 936
 937 uint64_t
 938 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 939 {
 940         uint64_t caps = sa->priv.dp_rx->dev_offload_capa;
 941
 942         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 943
 944         return caps & sfc_rx_get_offload_mask(sa);
 945 }
 946
 947 uint64_t
 948 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 949 {
 950         return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa);
 951 }
 952
 953 static int
 954 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 955                    const struct rte_eth_rxconf *rx_conf,
 956                    __rte_unused uint64_t offloads)
 957 {
 958         int rc = 0;
 959
 960         if (rx_conf->rx_thresh.pthresh != 0 ||
 961             rx_conf->rx_thresh.hthresh != 0 ||
 962             rx_conf->rx_thresh.wthresh != 0) {
 963                 sfc_warn(sa,
 964                         "RxQ prefetch/host/writeback thresholds are not supported");
 965         }
 966
 967         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 968                 sfc_err(sa,
 969                         "RxQ free threshold too large: %u vs maximum %u",
 970                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 971                 rc = EINVAL;
 972         }
 973
 974         if (rx_conf->rx_drop_en == 0) {
 975                 sfc_err(sa, "RxQ drop disable is not supported");
 976                 rc = EINVAL;
 977         }
 978
 979         return rc;
 980 }
 981
 982 static unsigned int
 983 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 984 {
 985         uint32_t data_off;
 986         uint32_t order;
 987
 988         /* The mbuf object itself is always cache line aligned */
 989         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 990
 991         /* Data offset from mbuf object start */
 992         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 993                 RTE_PKTMBUF_HEADROOM;
 994
 995         order = MIN(order, rte_bsf32(data_off));
 996
 997         return 1u << order;
 998 }
 999
1000 static uint16_t
1001 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
1002 {
1003         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1004         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
1005         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
1006         uint16_t buf_size;
1007         unsigned int buf_aligned;
1008         unsigned int start_alignment;
1009         unsigned int end_padding_alignment;
1010
1011         /* Below it is assumed that both alignments are power of 2 */
1012         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
1013         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
1014
1015         /*
1016          * mbuf is always cache line aligned, double-check
1017          * that it meets rx buffer start alignment requirements.
1018          */
1019
1020         /* Start from mbuf pool data room size */
1021         buf_size = rte_pktmbuf_data_room_size(mb_pool);
1022
1023         /* Remove headroom */
1024         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
1025                 sfc_err(sa,
1026                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
1027                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
1028                 return 0;
1029         }
1030         buf_size -= RTE_PKTMBUF_HEADROOM;
1031
1032         /* Calculate guaranteed data start alignment */
1033         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
1034
1035         /* Reserve space for start alignment */
1036         if (buf_aligned < nic_align_start) {
1037                 start_alignment = nic_align_start - buf_aligned;
1038                 if (buf_size <= start_alignment) {
1039                         sfc_err(sa,
1040                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
1041                                 mb_pool->name,
1042                                 rte_pktmbuf_data_room_size(mb_pool),
1043                                 RTE_PKTMBUF_HEADROOM, start_alignment);
1044                         return 0;
1045                 }
1046                 buf_aligned = nic_align_start;
1047                 buf_size -= start_alignment;
1048         } else {
1049                 start_alignment = 0;
1050         }
1051
1052         /* Make sure that end padding does not write beyond the buffer */
1053         if (buf_aligned < nic_align_end) {
1054                 /*
1055                  * Estimate space which can be lost. If guarnteed buffer
1056                  * size is odd, lost space is (nic_align_end - 1). More
1057                  * accurate formula is below.
1058                  */
1059                 end_padding_alignment = nic_align_end -
1060                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
1061                 if (buf_size <= end_padding_alignment) {
1062                         sfc_err(sa,
1063                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
1064                                 mb_pool->name,
1065                                 rte_pktmbuf_data_room_size(mb_pool),
1066                                 RTE_PKTMBUF_HEADROOM, start_alignment,
1067                                 end_padding_alignment);
1068                         return 0;
1069                 }
1070                 buf_size -= end_padding_alignment;
1071         } else {
1072                 /*
1073                  * Start is aligned the same or better than end,
1074                  * just align length.
1075                  */
1076                 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end);
1077         }
1078
1079         return buf_size;
1080 }
1081
1082 int
1083 sfc_rx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1084              uint16_t nb_rx_desc, unsigned int socket_id,
1085              const struct rte_eth_rxconf *rx_conf,
1086              struct rte_mempool *mb_pool)
1087 {
1088         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1089         sfc_ethdev_qid_t ethdev_qid;
1090         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1091         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1092         int rc;
1093         unsigned int rxq_entries;
1094         unsigned int evq_entries;
1095         unsigned int rxq_max_fill_level;
1096         uint64_t offloads;
1097         uint16_t buf_size;
1098         struct sfc_rxq_info *rxq_info;
1099         struct sfc_evq *evq;
1100         struct sfc_rxq *rxq;
1101         struct sfc_dp_rx_qcreate_info info;
1102         struct sfc_dp_rx_hw_limits hw_limits;
1103         uint16_t rx_free_thresh;
1104         const char *error;
1105
1106         memset(&hw_limits, 0, sizeof(hw_limits));
1107         hw_limits.rxq_max_entries = sa->rxq_max_entries;
1108         hw_limits.rxq_min_entries = sa->rxq_min_entries;
1109         hw_limits.evq_max_entries = sa->evq_max_entries;
1110         hw_limits.evq_min_entries = sa->evq_min_entries;
1111
1112         rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool,
1113                                             &rxq_entries, &evq_entries,
1114                                             &rxq_max_fill_level);
1115         if (rc != 0)
1116                 goto fail_size_up_rings;
1117         SFC_ASSERT(rxq_entries >= sa->rxq_min_entries);
1118         SFC_ASSERT(rxq_entries <= sa->rxq_max_entries);
1119         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
1120
1121         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1122
1123         offloads = rx_conf->offloads;
1124         /* Add device level Rx offloads if the queue is an ethdev Rx queue */
1125         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1126                 offloads |= sa->eth_dev->data->dev_conf.rxmode.offloads;
1127
1128         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
1129         if (rc != 0)
1130                 goto fail_bad_conf;
1131
1132         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1133         if (buf_size == 0) {
1134                 sfc_err(sa,
1135                         "RxQ %d (internal %u) mbuf pool object size is too small",
1136                         ethdev_qid, sw_index);
1137                 rc = EINVAL;
1138                 goto fail_bad_conf;
1139         }
1140
1141         if (!sfc_rx_check_scatter(sa->port.pdu, buf_size,
1142                                   encp->enc_rx_prefix_size,
1143                                   (offloads & DEV_RX_OFFLOAD_SCATTER),
1144                                   encp->enc_rx_scatter_max,
1145                                   &error)) {
1146                 sfc_err(sa, "RxQ %d (internal %u) MTU check failed: %s",
1147                         ethdev_qid, sw_index, error);
1148                 sfc_err(sa,
1149                         "RxQ %d (internal %u) calculated Rx buffer size is %u vs "
1150                         "PDU size %u plus Rx prefix %u bytes",
1151                         ethdev_qid, sw_index, buf_size,
1152                         (unsigned int)sa->port.pdu, encp->enc_rx_prefix_size);
1153                 rc = EINVAL;
1154                 goto fail_bad_conf;
1155         }
1156
1157         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1158         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1159
1160         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1161         rxq_info->entries = rxq_entries;
1162
1163         if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1164                 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1165         else
1166                 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1167
1168         rxq_info->type_flags |=
1169                 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1170                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1171
1172         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1173             (sfc_dp_rx_offload_capa(sa->priv.dp_rx) &
1174              DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0)
1175                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1176
1177         if (offloads & DEV_RX_OFFLOAD_RSS_HASH)
1178                 rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH;
1179
1180         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1181                           evq_entries, socket_id, &evq);
1182         if (rc != 0)
1183                 goto fail_ev_qinit;
1184
1185         rxq = &sa->rxq_ctrl[sw_index];
1186         rxq->evq = evq;
1187         rxq->hw_index = sw_index;
1188         /*
1189          * If Rx refill threshold is specified (its value is non zero) in
1190          * Rx configuration, use specified value. Otherwise use 1/8 of
1191          * the Rx descriptors number as the default. It allows to keep
1192          * Rx ring full-enough and does not refill too aggressive if
1193          * packet rate is high.
1194          *
1195          * Since PMD refills in bulks waiting for full bulk may be
1196          * refilled (basically round down), it is better to round up
1197          * here to mitigate it a bit.
1198          */
1199         rx_free_thresh = (rx_conf->rx_free_thresh != 0) ?
1200                 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8);
1201         /* Rx refill threshold cannot be smaller than refill bulk */
1202         rxq_info->refill_threshold =
1203                 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK);
1204         rxq_info->refill_mb_pool = mb_pool;
1205
1206         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 &&
1207             (offloads & DEV_RX_OFFLOAD_RSS_HASH))
1208                 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH;
1209         else
1210                 rxq_info->rxq_flags = 0;
1211
1212         rxq->buf_size = buf_size;
1213
1214         rc = sfc_dma_alloc(sa, "rxq", sw_index,
1215                            efx_rxq_size(sa->nic, rxq_info->entries),
1216                            socket_id, &rxq->mem);
1217         if (rc != 0)
1218                 goto fail_dma_alloc;
1219
1220         memset(&info, 0, sizeof(info));
1221         info.refill_mb_pool = rxq_info->refill_mb_pool;
1222         info.max_fill_level = rxq_max_fill_level;
1223         info.refill_threshold = rxq_info->refill_threshold;
1224         info.buf_size = buf_size;
1225         info.batch_max = encp->enc_rx_batch_max;
1226         info.prefix_size = encp->enc_rx_prefix_size;
1227         info.flags = rxq_info->rxq_flags;
1228         info.rxq_entries = rxq_info->entries;
1229         info.rxq_hw_ring = rxq->mem.esm_base;
1230         info.evq_hw_index = sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index);
1231         info.evq_entries = evq_entries;
1232         info.evq_hw_ring = evq->mem.esm_base;
1233         info.hw_index = rxq->hw_index;
1234         info.mem_bar = sa->mem_bar.esb_base;
1235         info.vi_window_shift = encp->enc_vi_window_shift;
1236         info.fcw_offset = sa->fcw_offset;
1237
1238         rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1239                                      &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1240                                      socket_id, &info, &rxq_info->dp);
1241         if (rc != 0)
1242                 goto fail_dp_rx_qcreate;
1243
1244         evq->dp_rxq = rxq_info->dp;
1245
1246         rxq_info->state = SFC_RXQ_INITIALIZED;
1247
1248         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1249
1250         return 0;
1251
1252 fail_dp_rx_qcreate:
1253         sfc_dma_free(sa, &rxq->mem);
1254
1255 fail_dma_alloc:
1256         sfc_ev_qfini(evq);
1257
1258 fail_ev_qinit:
1259         rxq_info->entries = 0;
1260
1261 fail_bad_conf:
1262 fail_size_up_rings:
1263         sfc_log_init(sa, "failed %d", rc);
1264         return rc;
1265 }
1266
1267 void
1268 sfc_rx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
1269 {
1270         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1271         sfc_ethdev_qid_t ethdev_qid;
1272         struct sfc_rxq_info *rxq_info;
1273         struct sfc_rxq *rxq;
1274
1275         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1276         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1277
1278         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1279                 sa->eth_dev->data->rx_queues[ethdev_qid] = NULL;
1280
1281         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1282
1283         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1284
1285         sa->priv.dp_rx->qdestroy(rxq_info->dp);
1286         rxq_info->dp = NULL;
1287
1288         rxq_info->state &= ~SFC_RXQ_INITIALIZED;
1289         rxq_info->entries = 0;
1290
1291         rxq = &sa->rxq_ctrl[sw_index];
1292
1293         sfc_dma_free(sa, &rxq->mem);
1294
1295         sfc_ev_qfini(rxq->evq);
1296         rxq->evq = NULL;
1297 }
1298
1299 /*
1300  * Mapping between RTE RSS hash functions and their EFX counterparts.
1301  */
1302 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1303         { ETH_RSS_NONFRAG_IPV4_TCP,
1304           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1305         { ETH_RSS_NONFRAG_IPV4_UDP,
1306           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1307         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1308           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1309         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1310           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1311         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1312           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1313           EFX_RX_HASH(IPV4, 2TUPLE) },
1314         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1315           ETH_RSS_IPV6_EX,
1316           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1317           EFX_RX_HASH(IPV6, 2TUPLE) }
1318 };
1319
1320 static efx_rx_hash_type_t
1321 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1322                             unsigned int *hash_type_flags_supported,
1323                             unsigned int nb_hash_type_flags_supported)
1324 {
1325         efx_rx_hash_type_t hash_type_masked = 0;
1326         unsigned int i, j;
1327
1328         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1329                 unsigned int class_tuple_lbn[] = {
1330                         EFX_RX_CLASS_IPV4_TCP_LBN,
1331                         EFX_RX_CLASS_IPV4_UDP_LBN,
1332                         EFX_RX_CLASS_IPV4_LBN,
1333                         EFX_RX_CLASS_IPV6_TCP_LBN,
1334                         EFX_RX_CLASS_IPV6_UDP_LBN,
1335                         EFX_RX_CLASS_IPV6_LBN
1336                 };
1337
1338                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1339                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1340                         unsigned int flag;
1341
1342                         tuple_mask <<= class_tuple_lbn[j];
1343                         flag = hash_type & tuple_mask;
1344
1345                         if (flag == hash_type_flags_supported[i])
1346                                 hash_type_masked |= flag;
1347                 }
1348         }
1349
1350         return hash_type_masked;
1351 }
1352
1353 int
1354 sfc_rx_hash_init(struct sfc_adapter *sa)
1355 {
1356         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1357         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1358         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1359         efx_rx_hash_alg_t alg;
1360         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1361         unsigned int nb_flags_supp;
1362         struct sfc_rss_hf_rte_to_efx *hf_map;
1363         struct sfc_rss_hf_rte_to_efx *entry;
1364         efx_rx_hash_type_t efx_hash_types;
1365         unsigned int i;
1366         int rc;
1367
1368         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1369                 alg = EFX_RX_HASHALG_TOEPLITZ;
1370         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1371                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1372         else
1373                 return EINVAL;
1374
1375         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1376                                          RTE_DIM(flags_supp), &nb_flags_supp);
1377         if (rc != 0)
1378                 return rc;
1379
1380         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1381                                    RTE_DIM(sfc_rss_hf_map),
1382                                    sizeof(*hf_map), 0, sa->socket_id);
1383         if (hf_map == NULL)
1384                 return ENOMEM;
1385
1386         entry = hf_map;
1387         efx_hash_types = 0;
1388         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1389                 efx_rx_hash_type_t ht;
1390
1391                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1392                                                  flags_supp, nb_flags_supp);
1393                 if (ht != 0) {
1394                         entry->rte = sfc_rss_hf_map[i].rte;
1395                         entry->efx = ht;
1396                         efx_hash_types |= ht;
1397                         ++entry;
1398                 }
1399         }
1400
1401         rss->hash_alg = alg;
1402         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1403         rss->hf_map = hf_map;
1404         rss->hash_types = efx_hash_types;
1405
1406         return 0;
1407 }
1408
1409 void
1410 sfc_rx_hash_fini(struct sfc_adapter *sa)
1411 {
1412         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1413
1414         rte_free(rss->hf_map);
1415 }
1416
1417 int
1418 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1419                      efx_rx_hash_type_t *efx)
1420 {
1421         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1422         efx_rx_hash_type_t hash_types = 0;
1423         unsigned int i;
1424
1425         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1426                 uint64_t rte_mask = rss->hf_map[i].rte;
1427
1428                 if ((rte & rte_mask) != 0) {
1429                         rte &= ~rte_mask;
1430                         hash_types |= rss->hf_map[i].efx;
1431                 }
1432         }
1433
1434         if (rte != 0) {
1435                 sfc_err(sa, "unsupported hash functions requested");
1436                 return EINVAL;
1437         }
1438
1439         *efx = hash_types;
1440
1441         return 0;
1442 }
1443
1444 uint64_t
1445 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx)
1446 {
1447         uint64_t rte = 0;
1448         unsigned int i;
1449
1450         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1451                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1452
1453                 if ((efx & hash_type) == hash_type)
1454                         rte |= rss->hf_map[i].rte;
1455         }
1456
1457         return rte;
1458 }
1459
1460 static int
1461 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1462                             struct rte_eth_rss_conf *conf)
1463 {
1464         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1465         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1466         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types);
1467         int rc;
1468
1469         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1470                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1471                     conf->rss_key != NULL)
1472                         return EINVAL;
1473         }
1474
1475         if (conf->rss_hf != 0) {
1476                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1477                 if (rc != 0)
1478                         return rc;
1479         }
1480
1481         if (conf->rss_key != NULL) {
1482                 if (conf->rss_key_len != sizeof(rss->key)) {
1483                         sfc_err(sa, "RSS key size is wrong (should be %zu)",
1484                                 sizeof(rss->key));
1485                         return EINVAL;
1486                 }
1487                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1488         }
1489
1490         rss->hash_types = efx_hash_types;
1491
1492         return 0;
1493 }
1494
1495 static int
1496 sfc_rx_rss_config(struct sfc_adapter *sa)
1497 {
1498         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1499         int rc = 0;
1500
1501         if (rss->channels > 0) {
1502                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1503                                            rss->hash_alg, rss->hash_types,
1504                                            B_TRUE);
1505                 if (rc != 0)
1506                         goto finish;
1507
1508                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1509                                           rss->key, sizeof(rss->key));
1510                 if (rc != 0)
1511                         goto finish;
1512
1513                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1514                                           rss->tbl, RTE_DIM(rss->tbl));
1515         }
1516
1517 finish:
1518         return rc;
1519 }
1520
1521 struct sfc_rxq_info *
1522 sfc_rxq_info_by_ethdev_qid(struct sfc_adapter_shared *sas,
1523                            sfc_ethdev_qid_t ethdev_qid)
1524 {
1525         sfc_sw_index_t sw_index;
1526
1527         SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1528         SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1529
1530         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1531         return &sas->rxq_info[sw_index];
1532 }
1533
1534 struct sfc_rxq *
1535 sfc_rxq_ctrl_by_ethdev_qid(struct sfc_adapter *sa, sfc_ethdev_qid_t ethdev_qid)
1536 {
1537         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1538         sfc_sw_index_t sw_index;
1539
1540         SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1541         SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1542
1543         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1544         return &sa->rxq_ctrl[sw_index];
1545 }
1546
1547 int
1548 sfc_rx_start(struct sfc_adapter *sa)
1549 {
1550         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1551         sfc_sw_index_t sw_index;
1552         int rc;
1553
1554         sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1555                      sas->rxq_count);
1556
1557         rc = efx_rx_init(sa->nic);
1558         if (rc != 0)
1559                 goto fail_rx_init;
1560
1561         rc = sfc_rx_rss_config(sa);
1562         if (rc != 0)
1563                 goto fail_rss_config;
1564
1565         for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) {
1566                 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED &&
1567                     (!sas->rxq_info[sw_index].deferred_start ||
1568                      sas->rxq_info[sw_index].deferred_started)) {
1569                         rc = sfc_rx_qstart(sa, sw_index);
1570                         if (rc != 0)
1571                                 goto fail_rx_qstart;
1572                 }
1573         }
1574
1575         return 0;
1576
1577 fail_rx_qstart:
1578         while (sw_index-- > 0)
1579                 sfc_rx_qstop(sa, sw_index);
1580
1581 fail_rss_config:
1582         efx_rx_fini(sa->nic);
1583
1584 fail_rx_init:
1585         sfc_log_init(sa, "failed %d", rc);
1586         return rc;
1587 }
1588
1589 void
1590 sfc_rx_stop(struct sfc_adapter *sa)
1591 {
1592         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1593         sfc_sw_index_t sw_index;
1594
1595         sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1596                      sas->rxq_count);
1597
1598         sw_index = sas->rxq_count;
1599         while (sw_index-- > 0) {
1600                 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED)
1601                         sfc_rx_qstop(sa, sw_index);
1602         }
1603
1604         efx_rx_fini(sa->nic);
1605 }
1606
1607 int
1608 sfc_rx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1609                   unsigned int extra_efx_type_flags)
1610 {
1611         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1612         struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index];
1613         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1614         unsigned int max_entries;
1615
1616         max_entries = encp->enc_rxq_max_ndescs;
1617         SFC_ASSERT(rte_is_power_of_2(max_entries));
1618
1619         rxq_info->max_entries = max_entries;
1620         rxq_info->type_flags = extra_efx_type_flags;
1621
1622         return 0;
1623 }
1624
1625 static int
1626 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1627 {
1628         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1629         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1630                                       sfc_rx_get_queue_offload_caps(sa);
1631         struct sfc_rss *rss = &sas->rss;
1632         int rc = 0;
1633
1634         switch (rxmode->mq_mode) {
1635         case ETH_MQ_RX_NONE:
1636                 /* No special checks are required */
1637                 break;
1638         case ETH_MQ_RX_RSS:
1639                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1640                         sfc_err(sa, "RSS is not available");
1641                         rc = EINVAL;
1642                 }
1643                 break;
1644         default:
1645                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1646                         rxmode->mq_mode);
1647                 rc = EINVAL;
1648         }
1649
1650         /*
1651          * Requested offloads are validated against supported by ethdev,
1652          * so unsupported offloads cannot be added as the result of
1653          * below check.
1654          */
1655         if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1656             (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1657                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1658                 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1659         }
1660
1661         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1662             (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1663                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1664                 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1665         }
1666
1667         return rc;
1668 }
1669
1670 /**
1671  * Destroy excess queues that are no longer needed after reconfiguration
1672  * or complete close.
1673  */
1674 static void
1675 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1676 {
1677         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1678         sfc_sw_index_t sw_index;
1679         sfc_ethdev_qid_t ethdev_qid;
1680
1681         SFC_ASSERT(nb_rx_queues <= sas->ethdev_rxq_count);
1682
1683         /*
1684          * Finalize only ethdev queues since other ones are finalized only
1685          * on device close and they may require additional deinitializaton.
1686          */
1687         ethdev_qid = sas->ethdev_rxq_count;
1688         while (--ethdev_qid >= (int)nb_rx_queues) {
1689                 struct sfc_rxq_info *rxq_info;
1690
1691                 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, ethdev_qid);
1692                 if (rxq_info->state & SFC_RXQ_INITIALIZED) {
1693                         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1694                                                                 ethdev_qid);
1695                         sfc_rx_qfini(sa, sw_index);
1696                 }
1697
1698         }
1699
1700         sas->ethdev_rxq_count = nb_rx_queues;
1701 }
1702
1703 /**
1704  * Initialize Rx subsystem.
1705  *
1706  * Called at device (re)configuration stage when number of receive queues is
1707  * specified together with other device level receive configuration.
1708  *
1709  * It should be used to allocate NUMA-unaware resources.
1710  */
1711 int
1712 sfc_rx_configure(struct sfc_adapter *sa)
1713 {
1714         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1715         struct sfc_rss *rss = &sas->rss;
1716         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1717         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1718         const unsigned int nb_rsrv_rx_queues = sfc_nb_reserved_rxq(sas);
1719         const unsigned int nb_rxq_total = nb_rx_queues + nb_rsrv_rx_queues;
1720         bool reconfigure;
1721         int rc;
1722
1723         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1724                      nb_rx_queues, sas->ethdev_rxq_count);
1725
1726         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1727         if (rc != 0)
1728                 goto fail_check_mode;
1729
1730         if (nb_rxq_total == sas->rxq_count) {
1731                 reconfigure = true;
1732                 goto configure_rss;
1733         }
1734
1735         if (sas->rxq_info == NULL) {
1736                 reconfigure = false;
1737                 rc = ENOMEM;
1738                 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rxq_total,
1739                                                   sizeof(sas->rxq_info[0]), 0,
1740                                                   sa->socket_id);
1741                 if (sas->rxq_info == NULL)
1742                         goto fail_rxqs_alloc;
1743
1744                 /*
1745                  * Allocate primary process only RxQ control from heap
1746                  * since it should not be shared.
1747                  */
1748                 rc = ENOMEM;
1749                 sa->rxq_ctrl = calloc(nb_rxq_total, sizeof(sa->rxq_ctrl[0]));
1750                 if (sa->rxq_ctrl == NULL)
1751                         goto fail_rxqs_ctrl_alloc;
1752         } else {
1753                 struct sfc_rxq_info *new_rxq_info;
1754                 struct sfc_rxq *new_rxq_ctrl;
1755
1756                 reconfigure = true;
1757
1758                 /* Do not ununitialize reserved queues */
1759                 if (nb_rx_queues < sas->ethdev_rxq_count)
1760                         sfc_rx_fini_queues(sa, nb_rx_queues);
1761
1762                 rc = ENOMEM;
1763                 new_rxq_info =
1764                         rte_realloc(sas->rxq_info,
1765                                     nb_rxq_total * sizeof(sas->rxq_info[0]), 0);
1766                 if (new_rxq_info == NULL && nb_rxq_total > 0)
1767                         goto fail_rxqs_realloc;
1768
1769                 rc = ENOMEM;
1770                 new_rxq_ctrl = realloc(sa->rxq_ctrl,
1771                                        nb_rxq_total * sizeof(sa->rxq_ctrl[0]));
1772                 if (new_rxq_ctrl == NULL && nb_rxq_total > 0)
1773                         goto fail_rxqs_ctrl_realloc;
1774
1775                 sas->rxq_info = new_rxq_info;
1776                 sa->rxq_ctrl = new_rxq_ctrl;
1777                 if (nb_rxq_total > sas->rxq_count) {
1778                         unsigned int rxq_count = sas->rxq_count;
1779
1780                         memset(&sas->rxq_info[rxq_count], 0,
1781                                (nb_rxq_total - rxq_count) *
1782                                sizeof(sas->rxq_info[0]));
1783                         memset(&sa->rxq_ctrl[rxq_count], 0,
1784                                (nb_rxq_total - rxq_count) *
1785                                sizeof(sa->rxq_ctrl[0]));
1786                 }
1787         }
1788
1789         while (sas->ethdev_rxq_count < nb_rx_queues) {
1790                 sfc_sw_index_t sw_index;
1791
1792                 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1793                                                         sas->ethdev_rxq_count);
1794                 rc = sfc_rx_qinit_info(sa, sw_index, 0);
1795                 if (rc != 0)
1796                         goto fail_rx_qinit_info;
1797
1798                 sas->ethdev_rxq_count++;
1799         }
1800
1801         sas->rxq_count = sas->ethdev_rxq_count + nb_rsrv_rx_queues;
1802
1803         if (!reconfigure) {
1804                 rc = sfc_mae_counter_rxq_init(sa);
1805                 if (rc != 0)
1806                         goto fail_count_rxq_init;
1807         }
1808
1809 configure_rss:
1810         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1811                          MIN(sas->ethdev_rxq_count, EFX_MAXRSS) : 0;
1812
1813         if (rss->channels > 0) {
1814                 struct rte_eth_rss_conf *adv_conf_rss;
1815                 sfc_sw_index_t sw_index;
1816
1817                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1818                         rss->tbl[sw_index] = sw_index % rss->channels;
1819
1820                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1821                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1822                 if (rc != 0)
1823                         goto fail_rx_process_adv_conf_rss;
1824         }
1825
1826         return 0;
1827
1828 fail_rx_process_adv_conf_rss:
1829         if (!reconfigure)
1830                 sfc_mae_counter_rxq_fini(sa);
1831
1832 fail_count_rxq_init:
1833 fail_rx_qinit_info:
1834 fail_rxqs_ctrl_realloc:
1835 fail_rxqs_realloc:
1836 fail_rxqs_ctrl_alloc:
1837 fail_rxqs_alloc:
1838         sfc_rx_close(sa);
1839
1840 fail_check_mode:
1841         sfc_log_init(sa, "failed %d", rc);
1842         return rc;
1843 }
1844
1845 /**
1846  * Shutdown Rx subsystem.
1847  *
1848  * Called at device close stage, for example, before device shutdown.
1849  */
1850 void
1851 sfc_rx_close(struct sfc_adapter *sa)
1852 {
1853         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1854
1855         sfc_rx_fini_queues(sa, 0);
1856         sfc_mae_counter_rxq_fini(sa);
1857
1858         rss->channels = 0;
1859
1860         free(sa->rxq_ctrl);
1861         sa->rxq_ctrl = NULL;
1862
1863         rte_free(sfc_sa2shared(sa)->rxq_info);
1864         sfc_sa2shared(sa)->rxq_info = NULL;
1865 }