drivers/net/sfc/sfc_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2021 Xilinx, Inc.
   4  * Copyright(c) 2016-2019 Solarflare Communications Inc.
   5  *
   6  * This software was jointly developed between OKTET Labs (under contract
   7  * for Solarflare) and Solarflare Communications, Inc.
   8  */
   9
  10 #include <rte_mempool.h>
  11
  12 #include "efx.h"
  13
  14 #include "sfc.h"
  15 #include "sfc_debug.h"
  16 #include "sfc_log.h"
  17 #include "sfc_ev.h"
  18 #include "sfc_rx.h"
  19 #include "sfc_mae_counter.h"
  20 #include "sfc_kvargs.h"
  21 #include "sfc_tweak.h"
  22
  23 /*
  24  * Maximum number of Rx queue flush attempt in the case of failure or
  25  * flush timeout
  26  */
  27 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  28
  29 /*
  30  * Time to wait between event queue polling attempts when waiting for Rx
  31  * queue flush done or failed events.
  32  */
  33 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  34
  35 /*
  36  * Maximum number of event queue polling attempts when waiting for Rx queue
  37  * flush done or failed events. It defines Rx queue flush attempt timeout
  38  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  39  */
  40 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  41
  42 void
  43 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
  44 {
  45         rxq_info->state |= SFC_RXQ_FLUSHED;
  46         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  47 }
  48
  49 void
  50 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
  51 {
  52         rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
  53         rxq_info->state &= ~SFC_RXQ_FLUSHING;
  54 }
  55
  56 /* This returns the running counter, which is not bounded by ring size */
  57 unsigned int
  58 sfc_rx_get_pushed(struct sfc_adapter *sa, struct sfc_dp_rxq *dp_rxq)
  59 {
  60         SFC_ASSERT(sa->priv.dp_rx->get_pushed != NULL);
  61
  62         return sa->priv.dp_rx->get_pushed(dp_rxq);
  63 }
  64
  65 static int
  66 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq)
  67 {
  68         int rc = 0;
  69
  70         if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) {
  71                 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr);
  72                 if (rc == 0)
  73                         rxq->evq->read_ptr_primed = rxq->evq->read_ptr;
  74         }
  75         return rc;
  76 }
  77
  78 static void
  79 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  80 {
  81         unsigned int free_space;
  82         unsigned int bulks;
  83         void *objs[SFC_RX_REFILL_BULK];
  84         efsys_dma_addr_t addr[RTE_DIM(objs)];
  85         unsigned int added = rxq->added;
  86         unsigned int id;
  87         unsigned int i;
  88         struct sfc_efx_rx_sw_desc *rxd;
  89         struct rte_mbuf *m;
  90         uint16_t port_id = rxq->dp.dpq.port_id;
  91
  92         free_space = rxq->max_fill_level - (added - rxq->completed);
  93
  94         if (free_space < rxq->refill_threshold)
  95                 return;
  96
  97         bulks = free_space / RTE_DIM(objs);
  98         /* refill_threshold guarantees that bulks is positive */
  99         SFC_ASSERT(bulks > 0);
 100
 101         id = added & rxq->ptr_mask;
 102         do {
 103                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
 104                                                   RTE_DIM(objs)) < 0)) {
 105                         /*
 106                          * It is hardly a safe way to increment counter
 107                          * from different contexts, but all PMDs do it.
 108                          */
 109                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
 110                                 RTE_DIM(objs);
 111                         /* Return if we have posted nothing yet */
 112                         if (added == rxq->added)
 113                                 return;
 114                         /* Push posted */
 115                         break;
 116                 }
 117
 118                 for (i = 0; i < RTE_DIM(objs);
 119                      ++i, id = (id + 1) & rxq->ptr_mask) {
 120                         m = objs[i];
 121
 122                         __rte_mbuf_raw_sanity_check(m);
 123
 124                         rxd = &rxq->sw_desc[id];
 125                         rxd->mbuf = m;
 126
 127                         m->data_off = RTE_PKTMBUF_HEADROOM;
 128                         m->port = port_id;
 129
 130                         addr[i] = rte_pktmbuf_iova(m);
 131                 }
 132
 133                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 134                              RTE_DIM(objs), rxq->completed, added);
 135                 added += RTE_DIM(objs);
 136         } while (--bulks > 0);
 137
 138         SFC_ASSERT(added != rxq->added);
 139         rxq->added = added;
 140         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 141         rxq->dp.dpq.rx_dbells++;
 142 }
 143
 144 static uint64_t
 145 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 146 {
 147         uint64_t mbuf_flags = 0;
 148
 149         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 150         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 151                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 152                 break;
 153         case EFX_PKT_IPV4:
 154                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 155                 break;
 156         default:
 157                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 158                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 159                            PKT_RX_IP_CKSUM_UNKNOWN);
 160                 break;
 161         }
 162
 163         switch ((desc_flags &
 164                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 165         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 166         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 167                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 168                 break;
 169         case EFX_PKT_TCP:
 170         case EFX_PKT_UDP:
 171                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 172                 break;
 173         default:
 174                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 175                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 176                            PKT_RX_L4_CKSUM_UNKNOWN);
 177                 break;
 178         }
 179
 180         return mbuf_flags;
 181 }
 182
 183 static uint32_t
 184 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 185 {
 186         return RTE_PTYPE_L2_ETHER |
 187                 ((desc_flags & EFX_PKT_IPV4) ?
 188                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 189                 ((desc_flags & EFX_PKT_IPV6) ?
 190                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 191                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 192                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 193 }
 194
 195 static const uint32_t *
 196 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
 197 {
 198         static const uint32_t ptypes[] = {
 199                 RTE_PTYPE_L2_ETHER,
 200                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 201                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 202                 RTE_PTYPE_L4_TCP,
 203                 RTE_PTYPE_L4_UDP,
 204                 RTE_PTYPE_UNKNOWN
 205         };
 206
 207         return ptypes;
 208 }
 209
 210 static void
 211 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 212                         struct rte_mbuf *m)
 213 {
 214         uint8_t *mbuf_data;
 215
 216
 217         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 218                 return;
 219
 220         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 221
 222         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 223                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 224                                                       EFX_RX_HASHALG_TOEPLITZ,
 225                                                       mbuf_data);
 226
 227                 m->ol_flags |= PKT_RX_RSS_HASH;
 228         }
 229 }
 230
 231 static uint16_t
 232 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 233 {
 234         struct sfc_dp_rxq *dp_rxq = rx_queue;
 235         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 236         unsigned int completed;
 237         unsigned int prefix_size = rxq->prefix_size;
 238         unsigned int done_pkts = 0;
 239         boolean_t discard_next = B_FALSE;
 240         struct rte_mbuf *scatter_pkt = NULL;
 241
 242         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 243                 return 0;
 244
 245         sfc_ev_qpoll(rxq->evq);
 246
 247         completed = rxq->completed;
 248         while (completed != rxq->pending && done_pkts < nb_pkts) {
 249                 unsigned int id;
 250                 struct sfc_efx_rx_sw_desc *rxd;
 251                 struct rte_mbuf *m;
 252                 unsigned int seg_len;
 253                 unsigned int desc_flags;
 254
 255                 id = completed++ & rxq->ptr_mask;
 256                 rxd = &rxq->sw_desc[id];
 257                 m = rxd->mbuf;
 258                 desc_flags = rxd->flags;
 259
 260                 if (discard_next)
 261                         goto discard;
 262
 263                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 264                         goto discard;
 265
 266                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 267                         uint16_t tmp_size;
 268                         int rc __rte_unused;
 269
 270                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 271                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 272                         SFC_ASSERT(rc == 0);
 273                         seg_len = tmp_size;
 274                 } else {
 275                         seg_len = rxd->size - prefix_size;
 276                 }
 277
 278                 rte_pktmbuf_data_len(m) = seg_len;
 279                 rte_pktmbuf_pkt_len(m) = seg_len;
 280
 281                 if (scatter_pkt != NULL) {
 282                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 283                                 rte_pktmbuf_free(scatter_pkt);
 284                                 goto discard;
 285                         }
 286                         /* The packet to deliver */
 287                         m = scatter_pkt;
 288                 }
 289
 290                 if (desc_flags & EFX_PKT_CONT) {
 291                         /* The packet is scattered, more fragments to come */
 292                         scatter_pkt = m;
 293                         /* Further fragments have no prefix */
 294                         prefix_size = 0;
 295                         continue;
 296                 }
 297
 298                 /* Scattered packet is done */
 299                 scatter_pkt = NULL;
 300                 /* The first fragment of the packet has prefix */
 301                 prefix_size = rxq->prefix_size;
 302
 303                 m->ol_flags =
 304                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 305                 m->packet_type =
 306                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 307
 308                 /*
 309                  * Extract RSS hash from the packet prefix and
 310                  * set the corresponding field (if needed and possible)
 311                  */
 312                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 313
 314                 m->data_off += prefix_size;
 315
 316                 *rx_pkts++ = m;
 317                 done_pkts++;
 318                 continue;
 319
 320 discard:
 321                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 322                 rte_mbuf_raw_free(m);
 323                 rxd->mbuf = NULL;
 324         }
 325
 326         /* pending is only moved when entire packet is received */
 327         SFC_ASSERT(scatter_pkt == NULL);
 328
 329         rxq->completed = completed;
 330
 331         sfc_efx_rx_qrefill(rxq);
 332
 333         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN)
 334                 sfc_efx_rx_qprime(rxq);
 335
 336         return done_pkts;
 337 }
 338
 339 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 340 static unsigned int
 341 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 342 {
 343         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 344
 345         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 346                 return 0;
 347
 348         sfc_ev_qpoll(rxq->evq);
 349
 350         return rxq->pending - rxq->completed;
 351 }
 352
 353 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
 354 static int
 355 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
 356 {
 357         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 358
 359         if (unlikely(offset > rxq->ptr_mask))
 360                 return -EINVAL;
 361
 362         /*
 363          * Poll EvQ to derive up-to-date 'rxq->pending' figure;
 364          * it is required for the queue to be running, but the
 365          * check is omitted because API design assumes that it
 366          * is the duty of the caller to satisfy all conditions
 367          */
 368         SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
 369                    SFC_EFX_RXQ_FLAG_RUNNING);
 370         sfc_ev_qpoll(rxq->evq);
 371
 372         /*
 373          * There is a handful of reserved entries in the ring,
 374          * but an explicit check whether the offset points to
 375          * a reserved entry is neglected since the two checks
 376          * below rely on the figures which take the HW limits
 377          * into account and thus if an entry is reserved, the
 378          * checks will fail and UNAVAIL code will be returned
 379          */
 380
 381         if (offset < (rxq->pending - rxq->completed))
 382                 return RTE_ETH_RX_DESC_DONE;
 383
 384         if (offset < (rxq->added - rxq->completed))
 385                 return RTE_ETH_RX_DESC_AVAIL;
 386
 387         return RTE_ETH_RX_DESC_UNAVAIL;
 388 }
 389
 390 boolean_t
 391 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size,
 392                      boolean_t rx_scatter_enabled, uint32_t rx_scatter_max,
 393                      const char **error)
 394 {
 395         uint32_t effective_rx_scatter_max;
 396         uint32_t rx_scatter_bufs;
 397
 398         effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1;
 399         rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size);
 400
 401         if (rx_scatter_bufs > effective_rx_scatter_max) {
 402                 if (rx_scatter_enabled)
 403                         *error = "Possible number of Rx scatter buffers exceeds maximum number";
 404                 else
 405                         *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small";
 406                 return B_FALSE;
 407         }
 408
 409         return B_TRUE;
 410 }
 411
 412 /** Get Rx datapath ops by the datapath RxQ handle */
 413 const struct sfc_dp_rx *
 414 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 415 {
 416         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 417         struct rte_eth_dev *eth_dev;
 418         struct sfc_adapter_priv *sap;
 419
 420         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 421         eth_dev = &rte_eth_devices[dpq->port_id];
 422
 423         sap = sfc_adapter_priv_by_eth_dev(eth_dev);
 424
 425         return sap->dp_rx;
 426 }
 427
 428 struct sfc_rxq_info *
 429 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 430 {
 431         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 432         struct rte_eth_dev *eth_dev;
 433         struct sfc_adapter_shared *sas;
 434
 435         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 436         eth_dev = &rte_eth_devices[dpq->port_id];
 437
 438         sas = sfc_adapter_shared_by_eth_dev(eth_dev);
 439
 440         SFC_ASSERT(dpq->queue_id < sas->rxq_count);
 441         return &sas->rxq_info[dpq->queue_id];
 442 }
 443
 444 struct sfc_rxq *
 445 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 446 {
 447         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 448         struct rte_eth_dev *eth_dev;
 449         struct sfc_adapter *sa;
 450
 451         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 452         eth_dev = &rte_eth_devices[dpq->port_id];
 453
 454         sa = sfc_adapter_by_eth_dev(eth_dev);
 455
 456         SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count);
 457         return &sa->rxq_ctrl[dpq->queue_id];
 458 }
 459
 460 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
 461 static int
 462 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
 463                           __rte_unused struct sfc_dp_rx_hw_limits *limits,
 464                           __rte_unused struct rte_mempool *mb_pool,
 465                           unsigned int *rxq_entries,
 466                           unsigned int *evq_entries,
 467                           unsigned int *rxq_max_fill_level)
 468 {
 469         *rxq_entries = nb_rx_desc;
 470         *evq_entries = nb_rx_desc;
 471         *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
 472         return 0;
 473 }
 474
 475 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 476 static int
 477 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 478                    const struct rte_pci_addr *pci_addr, int socket_id,
 479                    const struct sfc_dp_rx_qcreate_info *info,
 480                    struct sfc_dp_rxq **dp_rxqp)
 481 {
 482         struct sfc_efx_rxq *rxq;
 483         int rc;
 484
 485         rc = ENOMEM;
 486         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 487                                  RTE_CACHE_LINE_SIZE, socket_id);
 488         if (rxq == NULL)
 489                 goto fail_rxq_alloc;
 490
 491         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 492
 493         rc = ENOMEM;
 494         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 495                                          info->rxq_entries,
 496                                          sizeof(*rxq->sw_desc),
 497                                          RTE_CACHE_LINE_SIZE, socket_id);
 498         if (rxq->sw_desc == NULL)
 499                 goto fail_desc_alloc;
 500
 501         /* efx datapath is bound to efx control path */
 502         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 503         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 504                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 505         rxq->ptr_mask = info->rxq_entries - 1;
 506         rxq->batch_max = info->batch_max;
 507         rxq->prefix_size = info->prefix_size;
 508         rxq->max_fill_level = info->max_fill_level;
 509         rxq->refill_threshold = info->refill_threshold;
 510         rxq->buf_size = info->buf_size;
 511         rxq->refill_mb_pool = info->refill_mb_pool;
 512
 513         *dp_rxqp = &rxq->dp;
 514         return 0;
 515
 516 fail_desc_alloc:
 517         rte_free(rxq);
 518
 519 fail_rxq_alloc:
 520         return rc;
 521 }
 522
 523 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 524 static void
 525 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 526 {
 527         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 528
 529         rte_free(rxq->sw_desc);
 530         rte_free(rxq);
 531 }
 532
 533
 534 /* Use qstop and qstart functions in the case of qstart failure */
 535 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 536 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 537
 538
 539 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 540 static int
 541 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 542                   __rte_unused unsigned int evq_read_ptr,
 543                   const efx_rx_prefix_layout_t *pinfo)
 544 {
 545         /* libefx-based datapath is specific to libefx-based PMD */
 546         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 547         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 548         int rc;
 549
 550         /*
 551          * libefx API is used to extract information from Rx prefix and
 552          * it guarantees consistency. Just do length check to ensure
 553          * that we reserved space in Rx buffers correctly.
 554          */
 555         if (rxq->prefix_size != pinfo->erpl_length)
 556                 return ENOTSUP;
 557
 558         rxq->common = crxq->common;
 559
 560         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 561
 562         sfc_efx_rx_qrefill(rxq);
 563
 564         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 565
 566         if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) {
 567                 rc = sfc_efx_rx_qprime(rxq);
 568                 if (rc != 0)
 569                         goto fail_rx_qprime;
 570         }
 571
 572         return 0;
 573
 574 fail_rx_qprime:
 575         sfc_efx_rx_qstop(dp_rxq, NULL);
 576         sfc_efx_rx_qpurge(dp_rxq);
 577         return rc;
 578 }
 579
 580 static void
 581 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 582                  __rte_unused unsigned int *evq_read_ptr)
 583 {
 584         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 585
 586         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 587
 588         /* libefx-based datapath is bound to libefx-based PMD and uses
 589          * event queue structure directly. So, there is no necessity to
 590          * return EvQ read pointer.
 591          */
 592 }
 593
 594 static void
 595 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 596 {
 597         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 598         unsigned int i;
 599         struct sfc_efx_rx_sw_desc *rxd;
 600
 601         for (i = rxq->completed; i != rxq->added; ++i) {
 602                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 603                 rte_mbuf_raw_free(rxd->mbuf);
 604                 rxd->mbuf = NULL;
 605                 /* Packed stream relies on 0 in inactive SW desc.
 606                  * Rx queue stop is not performance critical, so
 607                  * there is no harm to do it always.
 608                  */
 609                 rxd->flags = 0;
 610                 rxd->size = 0;
 611         }
 612
 613         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 614 }
 615
 616 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable;
 617 static int
 618 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
 619 {
 620         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 621         int rc = 0;
 622
 623         rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN;
 624         if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) {
 625                 rc = sfc_efx_rx_qprime(rxq);
 626                 if (rc != 0)
 627                         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 628         }
 629         return rc;
 630 }
 631
 632 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable;
 633 static int
 634 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
 635 {
 636         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 637
 638         /* Cannot disarm, just disable rearm */
 639         rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
 640         return 0;
 641 }
 642
 643 struct sfc_dp_rx sfc_efx_rx = {
 644         .dp = {
 645                 .name           = SFC_KVARG_DATAPATH_EFX,
 646                 .type           = SFC_DP_RX,
 647                 .hw_fw_caps     = SFC_DP_HW_FW_CAP_RX_EFX,
 648         },
 649         .features               = SFC_DP_RX_FEAT_INTR,
 650         .dev_offload_capa       = DEV_RX_OFFLOAD_CHECKSUM |
 651                                   DEV_RX_OFFLOAD_RSS_HASH,
 652         .queue_offload_capa     = DEV_RX_OFFLOAD_SCATTER,
 653         .qsize_up_rings         = sfc_efx_rx_qsize_up_rings,
 654         .qcreate                = sfc_efx_rx_qcreate,
 655         .qdestroy               = sfc_efx_rx_qdestroy,
 656         .qstart                 = sfc_efx_rx_qstart,
 657         .qstop                  = sfc_efx_rx_qstop,
 658         .qpurge                 = sfc_efx_rx_qpurge,
 659         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 660         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 661         .qdesc_status           = sfc_efx_rx_qdesc_status,
 662         .intr_enable            = sfc_efx_rx_intr_enable,
 663         .intr_disable           = sfc_efx_rx_intr_disable,
 664         .pkt_burst              = sfc_efx_recv_pkts,
 665 };
 666
 667 static void
 668 sfc_rx_qflush(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 669 {
 670         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 671         sfc_ethdev_qid_t ethdev_qid;
 672         struct sfc_rxq_info *rxq_info;
 673         struct sfc_rxq *rxq;
 674         unsigned int retry_count;
 675         unsigned int wait_count;
 676         int rc;
 677
 678         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 679         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 680         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 681
 682         rxq = &sa->rxq_ctrl[sw_index];
 683
 684         /*
 685          * Retry Rx queue flushing in the case of flush failed or
 686          * timeout. In the worst case it can delay for 6 seconds.
 687          */
 688         for (retry_count = 0;
 689              ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
 690              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 691              ++retry_count) {
 692                 rc = efx_rx_qflush(rxq->common);
 693                 if (rc != 0) {
 694                         rxq_info->state |= (rc == EALREADY) ?
 695                                 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
 696                         break;
 697                 }
 698                 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
 699                 rxq_info->state |= SFC_RXQ_FLUSHING;
 700
 701                 /*
 702                  * Wait for Rx queue flush done or failed event at least
 703                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 704                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 705                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 706                  */
 707                 wait_count = 0;
 708                 do {
 709                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 710                         sfc_ev_qpoll(rxq->evq);
 711                 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
 712                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 713
 714                 if (rxq_info->state & SFC_RXQ_FLUSHING)
 715                         sfc_err(sa, "RxQ %d (internal %u) flush timed out",
 716                                 ethdev_qid, sw_index);
 717
 718                 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
 719                         sfc_err(sa, "RxQ %d (internal %u) flush failed",
 720                                 ethdev_qid, sw_index);
 721
 722                 if (rxq_info->state & SFC_RXQ_FLUSHED)
 723                         sfc_notice(sa, "RxQ %d (internal %u) flushed",
 724                                    ethdev_qid, sw_index);
 725         }
 726
 727         sa->priv.dp_rx->qpurge(rxq_info->dp);
 728 }
 729
 730 static int
 731 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 732 {
 733         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
 734         boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
 735         struct sfc_port *port = &sa->port;
 736         int rc;
 737
 738         /*
 739          * If promiscuous or all-multicast mode has been requested, setting
 740          * filter for the default Rx queue might fail, in particular, while
 741          * running over PCI function which is not a member of corresponding
 742          * privilege groups; if this occurs, few iterations will be made to
 743          * repeat this step without promiscuous and all-multicast flags set
 744          */
 745 retry:
 746         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
 747         if (rc == 0)
 748                 return 0;
 749         else if (rc != EOPNOTSUPP)
 750                 return rc;
 751
 752         if (port->promisc) {
 753                 sfc_warn(sa, "promiscuous mode has been requested, "
 754                              "but the HW rejects it");
 755                 sfc_warn(sa, "promiscuous mode will be disabled");
 756
 757                 port->promisc = B_FALSE;
 758                 sa->eth_dev->data->promiscuous = 0;
 759                 rc = sfc_set_rx_mode_unchecked(sa);
 760                 if (rc != 0)
 761                         return rc;
 762
 763                 goto retry;
 764         }
 765
 766         if (port->allmulti) {
 767                 sfc_warn(sa, "all-multicast mode has been requested, "
 768                              "but the HW rejects it");
 769                 sfc_warn(sa, "all-multicast mode will be disabled");
 770
 771                 port->allmulti = B_FALSE;
 772                 sa->eth_dev->data->all_multicast = 0;
 773                 rc = sfc_set_rx_mode_unchecked(sa);
 774                 if (rc != 0)
 775                         return rc;
 776
 777                 goto retry;
 778         }
 779
 780         return rc;
 781 }
 782
 783 int
 784 sfc_rx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 785 {
 786         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 787         sfc_ethdev_qid_t ethdev_qid;
 788         struct sfc_rxq_info *rxq_info;
 789         struct sfc_rxq *rxq;
 790         struct sfc_evq *evq;
 791         efx_rx_prefix_layout_t pinfo;
 792         int rc;
 793
 794         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 795         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 796
 797         sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
 798
 799         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 800         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
 801
 802         rxq = &sa->rxq_ctrl[sw_index];
 803         evq = rxq->evq;
 804
 805         rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index));
 806         if (rc != 0)
 807                 goto fail_ev_qstart;
 808
 809         switch (rxq_info->type) {
 810         case EFX_RXQ_TYPE_DEFAULT:
 811                 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 812                         rxq->buf_size,
 813                         &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
 814                         rxq_info->type_flags, evq->common, &rxq->common);
 815                 break;
 816         case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
 817                 struct rte_mempool *mp = rxq_info->refill_mb_pool;
 818                 struct rte_mempool_info mp_info;
 819
 820                 rc = rte_mempool_ops_get_info(mp, &mp_info);
 821                 if (rc != 0) {
 822                         /* Positive errno is used in the driver */
 823                         rc = -rc;
 824                         goto fail_mp_get_info;
 825                 }
 826                 if (mp_info.contig_block_size <= 0) {
 827                         rc = EINVAL;
 828                         goto fail_bad_contig_block_size;
 829                 }
 830                 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
 831                         mp_info.contig_block_size, rxq->buf_size,
 832                         mp->header_size + mp->elt_size + mp->trailer_size,
 833                         sa->rxd_wait_timeout_ns,
 834                         &rxq->mem, rxq_info->entries, rxq_info->type_flags,
 835                         evq->common, &rxq->common);
 836                 break;
 837         }
 838         default:
 839                 rc = ENOTSUP;
 840         }
 841         if (rc != 0)
 842                 goto fail_rx_qcreate;
 843
 844         rc = efx_rx_prefix_get_layout(rxq->common, &pinfo);
 845         if (rc != 0)
 846                 goto fail_prefix_get_layout;
 847
 848         efx_rx_qenable(rxq->common);
 849
 850         rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr, &pinfo);
 851         if (rc != 0)
 852                 goto fail_dp_qstart;
 853
 854         rxq_info->state |= SFC_RXQ_STARTED;
 855
 856         if (ethdev_qid == 0 && !sfc_sa2shared(sa)->isolated) {
 857                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 858                 if (rc != 0)
 859                         goto fail_mac_filter_default_rxq_set;
 860         }
 861
 862         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 863         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
 864                 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
 865                         RTE_ETH_QUEUE_STATE_STARTED;
 866
 867         return 0;
 868
 869 fail_mac_filter_default_rxq_set:
 870         sfc_rx_qflush(sa, sw_index);
 871         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 872         rxq_info->state = SFC_RXQ_INITIALIZED;
 873
 874 fail_dp_qstart:
 875         efx_rx_qdestroy(rxq->common);
 876
 877 fail_prefix_get_layout:
 878 fail_rx_qcreate:
 879 fail_bad_contig_block_size:
 880 fail_mp_get_info:
 881         sfc_ev_qstop(evq);
 882
 883 fail_ev_qstart:
 884         return rc;
 885 }
 886
 887 void
 888 sfc_rx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
 889 {
 890         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
 891         sfc_ethdev_qid_t ethdev_qid;
 892         struct sfc_rxq_info *rxq_info;
 893         struct sfc_rxq *rxq;
 894
 895         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
 896         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
 897
 898         sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
 899
 900         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
 901
 902         if (rxq_info->state == SFC_RXQ_INITIALIZED)
 903                 return;
 904         SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
 905
 906         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 907         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
 908                 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
 909                         RTE_ETH_QUEUE_STATE_STOPPED;
 910
 911         rxq = &sa->rxq_ctrl[sw_index];
 912         sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
 913
 914         if (ethdev_qid == 0)
 915                 efx_mac_filter_default_rxq_clear(sa->nic);
 916
 917         sfc_rx_qflush(sa, sw_index);
 918
 919         rxq_info->state = SFC_RXQ_INITIALIZED;
 920
 921         efx_rx_qdestroy(rxq->common);
 922
 923         sfc_ev_qstop(rxq->evq);
 924 }
 925
 926 static uint64_t
 927 sfc_rx_get_offload_mask(struct sfc_adapter *sa)
 928 {
 929         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 930         uint64_t no_caps = 0;
 931
 932         if (encp->enc_tunnel_encapsulations_supported == 0)
 933                 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
 934
 935         return ~no_caps;
 936 }
 937
 938 uint64_t
 939 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
 940 {
 941         uint64_t caps = sa->priv.dp_rx->dev_offload_capa;
 942
 943         caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 944
 945         return caps & sfc_rx_get_offload_mask(sa);
 946 }
 947
 948 uint64_t
 949 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
 950 {
 951         return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa);
 952 }
 953
 954 static int
 955 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
 956                    const struct rte_eth_rxconf *rx_conf,
 957                    __rte_unused uint64_t offloads)
 958 {
 959         int rc = 0;
 960
 961         if (rx_conf->rx_thresh.pthresh != 0 ||
 962             rx_conf->rx_thresh.hthresh != 0 ||
 963             rx_conf->rx_thresh.wthresh != 0) {
 964                 sfc_warn(sa,
 965                         "RxQ prefetch/host/writeback thresholds are not supported");
 966         }
 967
 968         if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
 969                 sfc_err(sa,
 970                         "RxQ free threshold too large: %u vs maximum %u",
 971                         rx_conf->rx_free_thresh, rxq_max_fill_level);
 972                 rc = EINVAL;
 973         }
 974
 975         if (rx_conf->rx_drop_en == 0) {
 976                 sfc_err(sa, "RxQ drop disable is not supported");
 977                 rc = EINVAL;
 978         }
 979
 980         return rc;
 981 }
 982
 983 static unsigned int
 984 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 985 {
 986         uint32_t data_off;
 987         uint32_t order;
 988
 989         /* The mbuf object itself is always cache line aligned */
 990         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 991
 992         /* Data offset from mbuf object start */
 993         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 994                 RTE_PKTMBUF_HEADROOM;
 995
 996         order = MIN(order, rte_bsf32(data_off));
 997
 998         return 1u << order;
 999 }
1000
1001 static uint16_t
1002 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
1003 {
1004         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1005         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
1006         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
1007         uint16_t buf_size;
1008         unsigned int buf_aligned;
1009         unsigned int start_alignment;
1010         unsigned int end_padding_alignment;
1011
1012         /* Below it is assumed that both alignments are power of 2 */
1013         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
1014         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
1015
1016         /*
1017          * mbuf is always cache line aligned, double-check
1018          * that it meets rx buffer start alignment requirements.
1019          */
1020
1021         /* Start from mbuf pool data room size */
1022         buf_size = rte_pktmbuf_data_room_size(mb_pool);
1023
1024         /* Remove headroom */
1025         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
1026                 sfc_err(sa,
1027                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
1028                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
1029                 return 0;
1030         }
1031         buf_size -= RTE_PKTMBUF_HEADROOM;
1032
1033         /* Calculate guaranteed data start alignment */
1034         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
1035
1036         /* Reserve space for start alignment */
1037         if (buf_aligned < nic_align_start) {
1038                 start_alignment = nic_align_start - buf_aligned;
1039                 if (buf_size <= start_alignment) {
1040                         sfc_err(sa,
1041                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
1042                                 mb_pool->name,
1043                                 rte_pktmbuf_data_room_size(mb_pool),
1044                                 RTE_PKTMBUF_HEADROOM, start_alignment);
1045                         return 0;
1046                 }
1047                 buf_aligned = nic_align_start;
1048                 buf_size -= start_alignment;
1049         } else {
1050                 start_alignment = 0;
1051         }
1052
1053         /* Make sure that end padding does not write beyond the buffer */
1054         if (buf_aligned < nic_align_end) {
1055                 /*
1056                  * Estimate space which can be lost. If guarnteed buffer
1057                  * size is odd, lost space is (nic_align_end - 1). More
1058                  * accurate formula is below.
1059                  */
1060                 end_padding_alignment = nic_align_end -
1061                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
1062                 if (buf_size <= end_padding_alignment) {
1063                         sfc_err(sa,
1064                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
1065                                 mb_pool->name,
1066                                 rte_pktmbuf_data_room_size(mb_pool),
1067                                 RTE_PKTMBUF_HEADROOM, start_alignment,
1068                                 end_padding_alignment);
1069                         return 0;
1070                 }
1071                 buf_size -= end_padding_alignment;
1072         } else {
1073                 /*
1074                  * Start is aligned the same or better than end,
1075                  * just align length.
1076                  */
1077                 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end);
1078         }
1079
1080         return buf_size;
1081 }
1082
1083 int
1084 sfc_rx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1085              uint16_t nb_rx_desc, unsigned int socket_id,
1086              const struct rte_eth_rxconf *rx_conf,
1087              struct rte_mempool *mb_pool)
1088 {
1089         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1090         sfc_ethdev_qid_t ethdev_qid;
1091         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1092         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1093         int rc;
1094         unsigned int rxq_entries;
1095         unsigned int evq_entries;
1096         unsigned int rxq_max_fill_level;
1097         uint64_t offloads;
1098         uint16_t buf_size;
1099         struct sfc_rxq_info *rxq_info;
1100         struct sfc_evq *evq;
1101         struct sfc_rxq *rxq;
1102         struct sfc_dp_rx_qcreate_info info;
1103         struct sfc_dp_rx_hw_limits hw_limits;
1104         uint16_t rx_free_thresh;
1105         const char *error;
1106
1107         memset(&hw_limits, 0, sizeof(hw_limits));
1108         hw_limits.rxq_max_entries = sa->rxq_max_entries;
1109         hw_limits.rxq_min_entries = sa->rxq_min_entries;
1110         hw_limits.evq_max_entries = sa->evq_max_entries;
1111         hw_limits.evq_min_entries = sa->evq_min_entries;
1112
1113         rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool,
1114                                             &rxq_entries, &evq_entries,
1115                                             &rxq_max_fill_level);
1116         if (rc != 0)
1117                 goto fail_size_up_rings;
1118         SFC_ASSERT(rxq_entries >= sa->rxq_min_entries);
1119         SFC_ASSERT(rxq_entries <= sa->rxq_max_entries);
1120         SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
1121
1122         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1123
1124         offloads = rx_conf->offloads;
1125         /* Add device level Rx offloads if the queue is an ethdev Rx queue */
1126         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1127                 offloads |= sa->eth_dev->data->dev_conf.rxmode.offloads;
1128
1129         rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
1130         if (rc != 0)
1131                 goto fail_bad_conf;
1132
1133         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1134         if (buf_size == 0) {
1135                 sfc_err(sa,
1136                         "RxQ %d (internal %u) mbuf pool object size is too small",
1137                         ethdev_qid, sw_index);
1138                 rc = EINVAL;
1139                 goto fail_bad_conf;
1140         }
1141
1142         if (!sfc_rx_check_scatter(sa->port.pdu, buf_size,
1143                                   encp->enc_rx_prefix_size,
1144                                   (offloads & DEV_RX_OFFLOAD_SCATTER),
1145                                   encp->enc_rx_scatter_max,
1146                                   &error)) {
1147                 sfc_err(sa, "RxQ %d (internal %u) MTU check failed: %s",
1148                         ethdev_qid, sw_index, error);
1149                 sfc_err(sa,
1150                         "RxQ %d (internal %u) calculated Rx buffer size is %u vs "
1151                         "PDU size %u plus Rx prefix %u bytes",
1152                         ethdev_qid, sw_index, buf_size,
1153                         (unsigned int)sa->port.pdu, encp->enc_rx_prefix_size);
1154                 rc = EINVAL;
1155                 goto fail_bad_conf;
1156         }
1157
1158         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1159         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1160
1161         SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1162         rxq_info->entries = rxq_entries;
1163
1164         if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1165                 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1166         else
1167                 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1168
1169         rxq_info->type_flags |=
1170                 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1171                 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1172
1173         if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1174             (sfc_dp_rx_offload_capa(sa->priv.dp_rx) &
1175              DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0)
1176                 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1177
1178         if (offloads & DEV_RX_OFFLOAD_RSS_HASH)
1179                 rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH;
1180
1181         if ((sa->negotiated_rx_metadata & RTE_ETH_RX_METADATA_USER_MARK) != 0)
1182                 rxq_info->type_flags |= EFX_RXQ_FLAG_USER_MARK;
1183
1184         rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1185                           evq_entries, socket_id, &evq);
1186         if (rc != 0)
1187                 goto fail_ev_qinit;
1188
1189         rxq = &sa->rxq_ctrl[sw_index];
1190         rxq->evq = evq;
1191         rxq->hw_index = sw_index;
1192         /*
1193          * If Rx refill threshold is specified (its value is non zero) in
1194          * Rx configuration, use specified value. Otherwise use 1/8 of
1195          * the Rx descriptors number as the default. It allows to keep
1196          * Rx ring full-enough and does not refill too aggressive if
1197          * packet rate is high.
1198          *
1199          * Since PMD refills in bulks waiting for full bulk may be
1200          * refilled (basically round down), it is better to round up
1201          * here to mitigate it a bit.
1202          */
1203         rx_free_thresh = (rx_conf->rx_free_thresh != 0) ?
1204                 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8);
1205         /* Rx refill threshold cannot be smaller than refill bulk */
1206         rxq_info->refill_threshold =
1207                 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK);
1208         rxq_info->refill_mb_pool = mb_pool;
1209
1210         if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 &&
1211             (offloads & DEV_RX_OFFLOAD_RSS_HASH))
1212                 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH;
1213         else
1214                 rxq_info->rxq_flags = 0;
1215
1216         rxq->buf_size = buf_size;
1217
1218         rc = sfc_dma_alloc(sa, "rxq", sw_index,
1219                            efx_rxq_size(sa->nic, rxq_info->entries),
1220                            socket_id, &rxq->mem);
1221         if (rc != 0)
1222                 goto fail_dma_alloc;
1223
1224         memset(&info, 0, sizeof(info));
1225         info.refill_mb_pool = rxq_info->refill_mb_pool;
1226         info.max_fill_level = rxq_max_fill_level;
1227         info.refill_threshold = rxq_info->refill_threshold;
1228         info.buf_size = buf_size;
1229         info.batch_max = encp->enc_rx_batch_max;
1230         info.prefix_size = encp->enc_rx_prefix_size;
1231         info.flags = rxq_info->rxq_flags;
1232         info.rxq_entries = rxq_info->entries;
1233         info.rxq_hw_ring = rxq->mem.esm_base;
1234         info.evq_hw_index = sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index);
1235         info.evq_entries = evq_entries;
1236         info.evq_hw_ring = evq->mem.esm_base;
1237         info.hw_index = rxq->hw_index;
1238         info.mem_bar = sa->mem_bar.esb_base;
1239         info.vi_window_shift = encp->enc_vi_window_shift;
1240         info.fcw_offset = sa->fcw_offset;
1241
1242         rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1243                                      &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1244                                      socket_id, &info, &rxq_info->dp);
1245         if (rc != 0)
1246                 goto fail_dp_rx_qcreate;
1247
1248         evq->dp_rxq = rxq_info->dp;
1249
1250         rxq_info->state = SFC_RXQ_INITIALIZED;
1251
1252         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1253
1254         return 0;
1255
1256 fail_dp_rx_qcreate:
1257         sfc_dma_free(sa, &rxq->mem);
1258
1259 fail_dma_alloc:
1260         sfc_ev_qfini(evq);
1261
1262 fail_ev_qinit:
1263         rxq_info->entries = 0;
1264
1265 fail_bad_conf:
1266 fail_size_up_rings:
1267         sfc_log_init(sa, "failed %d", rc);
1268         return rc;
1269 }
1270
1271 void
1272 sfc_rx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
1273 {
1274         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1275         sfc_ethdev_qid_t ethdev_qid;
1276         struct sfc_rxq_info *rxq_info;
1277         struct sfc_rxq *rxq;
1278
1279         SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1280         ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1281
1282         if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1283                 sa->eth_dev->data->rx_queues[ethdev_qid] = NULL;
1284
1285         rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1286
1287         SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1288
1289         sa->priv.dp_rx->qdestroy(rxq_info->dp);
1290         rxq_info->dp = NULL;
1291
1292         rxq_info->state &= ~SFC_RXQ_INITIALIZED;
1293         rxq_info->entries = 0;
1294
1295         rxq = &sa->rxq_ctrl[sw_index];
1296
1297         sfc_dma_free(sa, &rxq->mem);
1298
1299         sfc_ev_qfini(rxq->evq);
1300         rxq->evq = NULL;
1301 }
1302
1303 /*
1304  * Mapping between RTE RSS hash functions and their EFX counterparts.
1305  */
1306 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1307         { ETH_RSS_NONFRAG_IPV4_TCP,
1308           EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1309         { ETH_RSS_NONFRAG_IPV4_UDP,
1310           EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1311         { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1312           EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1313         { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1314           EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1315         { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1316           EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1317           EFX_RX_HASH(IPV4, 2TUPLE) },
1318         { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1319           ETH_RSS_IPV6_EX,
1320           EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1321           EFX_RX_HASH(IPV6, 2TUPLE) }
1322 };
1323
1324 static efx_rx_hash_type_t
1325 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1326                             unsigned int *hash_type_flags_supported,
1327                             unsigned int nb_hash_type_flags_supported)
1328 {
1329         efx_rx_hash_type_t hash_type_masked = 0;
1330         unsigned int i, j;
1331
1332         for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1333                 unsigned int class_tuple_lbn[] = {
1334                         EFX_RX_CLASS_IPV4_TCP_LBN,
1335                         EFX_RX_CLASS_IPV4_UDP_LBN,
1336                         EFX_RX_CLASS_IPV4_LBN,
1337                         EFX_RX_CLASS_IPV6_TCP_LBN,
1338                         EFX_RX_CLASS_IPV6_UDP_LBN,
1339                         EFX_RX_CLASS_IPV6_LBN
1340                 };
1341
1342                 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1343                         unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1344                         unsigned int flag;
1345
1346                         tuple_mask <<= class_tuple_lbn[j];
1347                         flag = hash_type & tuple_mask;
1348
1349                         if (flag == hash_type_flags_supported[i])
1350                                 hash_type_masked |= flag;
1351                 }
1352         }
1353
1354         return hash_type_masked;
1355 }
1356
1357 int
1358 sfc_rx_hash_init(struct sfc_adapter *sa)
1359 {
1360         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1361         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1362         uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1363         efx_rx_hash_alg_t alg;
1364         unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1365         unsigned int nb_flags_supp;
1366         struct sfc_rss_hf_rte_to_efx *hf_map;
1367         struct sfc_rss_hf_rte_to_efx *entry;
1368         efx_rx_hash_type_t efx_hash_types;
1369         unsigned int i;
1370         int rc;
1371
1372         if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1373                 alg = EFX_RX_HASHALG_TOEPLITZ;
1374         else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1375                 alg = EFX_RX_HASHALG_PACKED_STREAM;
1376         else
1377                 return EINVAL;
1378
1379         rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1380                                          RTE_DIM(flags_supp), &nb_flags_supp);
1381         if (rc != 0)
1382                 return rc;
1383
1384         hf_map = rte_calloc_socket("sfc-rss-hf-map",
1385                                    RTE_DIM(sfc_rss_hf_map),
1386                                    sizeof(*hf_map), 0, sa->socket_id);
1387         if (hf_map == NULL)
1388                 return ENOMEM;
1389
1390         entry = hf_map;
1391         efx_hash_types = 0;
1392         for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1393                 efx_rx_hash_type_t ht;
1394
1395                 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1396                                                  flags_supp, nb_flags_supp);
1397                 if (ht != 0) {
1398                         entry->rte = sfc_rss_hf_map[i].rte;
1399                         entry->efx = ht;
1400                         efx_hash_types |= ht;
1401                         ++entry;
1402                 }
1403         }
1404
1405         rss->hash_alg = alg;
1406         rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1407         rss->hf_map = hf_map;
1408         rss->hash_types = efx_hash_types;
1409
1410         return 0;
1411 }
1412
1413 void
1414 sfc_rx_hash_fini(struct sfc_adapter *sa)
1415 {
1416         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1417
1418         rte_free(rss->hf_map);
1419 }
1420
1421 int
1422 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1423                      efx_rx_hash_type_t *efx)
1424 {
1425         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1426         efx_rx_hash_type_t hash_types = 0;
1427         unsigned int i;
1428
1429         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1430                 uint64_t rte_mask = rss->hf_map[i].rte;
1431
1432                 if ((rte & rte_mask) != 0) {
1433                         rte &= ~rte_mask;
1434                         hash_types |= rss->hf_map[i].efx;
1435                 }
1436         }
1437
1438         if (rte != 0) {
1439                 sfc_err(sa, "unsupported hash functions requested");
1440                 return EINVAL;
1441         }
1442
1443         *efx = hash_types;
1444
1445         return 0;
1446 }
1447
1448 uint64_t
1449 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx)
1450 {
1451         uint64_t rte = 0;
1452         unsigned int i;
1453
1454         for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1455                 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1456
1457                 if ((efx & hash_type) == hash_type)
1458                         rte |= rss->hf_map[i].rte;
1459         }
1460
1461         return rte;
1462 }
1463
1464 static int
1465 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1466                             struct rte_eth_rss_conf *conf)
1467 {
1468         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1469         efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1470         uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types);
1471         int rc;
1472
1473         if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1474                 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1475                     conf->rss_key != NULL)
1476                         return EINVAL;
1477         }
1478
1479         if (conf->rss_hf != 0) {
1480                 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1481                 if (rc != 0)
1482                         return rc;
1483         }
1484
1485         if (conf->rss_key != NULL) {
1486                 if (conf->rss_key_len != sizeof(rss->key)) {
1487                         sfc_err(sa, "RSS key size is wrong (should be %zu)",
1488                                 sizeof(rss->key));
1489                         return EINVAL;
1490                 }
1491                 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1492         }
1493
1494         rss->hash_types = efx_hash_types;
1495
1496         return 0;
1497 }
1498
1499 static int
1500 sfc_rx_rss_config(struct sfc_adapter *sa)
1501 {
1502         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1503         int rc = 0;
1504
1505         if (rss->channels > 0) {
1506                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1507                                            rss->hash_alg, rss->hash_types,
1508                                            B_TRUE);
1509                 if (rc != 0)
1510                         goto finish;
1511
1512                 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1513                                           rss->key, sizeof(rss->key));
1514                 if (rc != 0)
1515                         goto finish;
1516
1517                 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1518                                           rss->tbl, RTE_DIM(rss->tbl));
1519         }
1520
1521 finish:
1522         return rc;
1523 }
1524
1525 struct sfc_rxq_info *
1526 sfc_rxq_info_by_ethdev_qid(struct sfc_adapter_shared *sas,
1527                            sfc_ethdev_qid_t ethdev_qid)
1528 {
1529         sfc_sw_index_t sw_index;
1530
1531         SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1532         SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1533
1534         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1535         return &sas->rxq_info[sw_index];
1536 }
1537
1538 struct sfc_rxq *
1539 sfc_rxq_ctrl_by_ethdev_qid(struct sfc_adapter *sa, sfc_ethdev_qid_t ethdev_qid)
1540 {
1541         struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1542         sfc_sw_index_t sw_index;
1543
1544         SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1545         SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1546
1547         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1548         return &sa->rxq_ctrl[sw_index];
1549 }
1550
1551 int
1552 sfc_rx_start(struct sfc_adapter *sa)
1553 {
1554         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1555         sfc_sw_index_t sw_index;
1556         int rc;
1557
1558         sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1559                      sas->rxq_count);
1560
1561         rc = efx_rx_init(sa->nic);
1562         if (rc != 0)
1563                 goto fail_rx_init;
1564
1565         rc = sfc_rx_rss_config(sa);
1566         if (rc != 0)
1567                 goto fail_rss_config;
1568
1569         for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) {
1570                 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED &&
1571                     (!sas->rxq_info[sw_index].deferred_start ||
1572                      sas->rxq_info[sw_index].deferred_started)) {
1573                         rc = sfc_rx_qstart(sa, sw_index);
1574                         if (rc != 0)
1575                                 goto fail_rx_qstart;
1576                 }
1577         }
1578
1579         return 0;
1580
1581 fail_rx_qstart:
1582         while (sw_index-- > 0)
1583                 sfc_rx_qstop(sa, sw_index);
1584
1585 fail_rss_config:
1586         efx_rx_fini(sa->nic);
1587
1588 fail_rx_init:
1589         sfc_log_init(sa, "failed %d", rc);
1590         return rc;
1591 }
1592
1593 void
1594 sfc_rx_stop(struct sfc_adapter *sa)
1595 {
1596         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1597         sfc_sw_index_t sw_index;
1598
1599         sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1600                      sas->rxq_count);
1601
1602         sw_index = sas->rxq_count;
1603         while (sw_index-- > 0) {
1604                 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED)
1605                         sfc_rx_qstop(sa, sw_index);
1606         }
1607
1608         efx_rx_fini(sa->nic);
1609 }
1610
1611 int
1612 sfc_rx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1613                   unsigned int extra_efx_type_flags)
1614 {
1615         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1616         struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index];
1617         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1618         unsigned int max_entries;
1619
1620         max_entries = encp->enc_rxq_max_ndescs;
1621         SFC_ASSERT(rte_is_power_of_2(max_entries));
1622
1623         rxq_info->max_entries = max_entries;
1624         rxq_info->type_flags = extra_efx_type_flags;
1625
1626         return 0;
1627 }
1628
1629 static int
1630 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1631 {
1632         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1633         uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1634                                       sfc_rx_get_queue_offload_caps(sa);
1635         struct sfc_rss *rss = &sas->rss;
1636         int rc = 0;
1637
1638         switch (rxmode->mq_mode) {
1639         case ETH_MQ_RX_NONE:
1640                 /* No special checks are required */
1641                 break;
1642         case ETH_MQ_RX_RSS:
1643                 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1644                         sfc_err(sa, "RSS is not available");
1645                         rc = EINVAL;
1646                 }
1647                 break;
1648         default:
1649                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1650                         rxmode->mq_mode);
1651                 rc = EINVAL;
1652         }
1653
1654         /*
1655          * Requested offloads are validated against supported by ethdev,
1656          * so unsupported offloads cannot be added as the result of
1657          * below check.
1658          */
1659         if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1660             (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1661                 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1662                 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1663         }
1664
1665         if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1666             (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1667                 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1668                 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1669         }
1670
1671         return rc;
1672 }
1673
1674 /**
1675  * Destroy excess queues that are no longer needed after reconfiguration
1676  * or complete close.
1677  */
1678 static void
1679 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1680 {
1681         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1682         sfc_sw_index_t sw_index;
1683         sfc_ethdev_qid_t ethdev_qid;
1684
1685         SFC_ASSERT(nb_rx_queues <= sas->ethdev_rxq_count);
1686
1687         /*
1688          * Finalize only ethdev queues since other ones are finalized only
1689          * on device close and they may require additional deinitializaton.
1690          */
1691         ethdev_qid = sas->ethdev_rxq_count;
1692         while (--ethdev_qid >= (int)nb_rx_queues) {
1693                 struct sfc_rxq_info *rxq_info;
1694
1695                 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, ethdev_qid);
1696                 if (rxq_info->state & SFC_RXQ_INITIALIZED) {
1697                         sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1698                                                                 ethdev_qid);
1699                         sfc_rx_qfini(sa, sw_index);
1700                 }
1701
1702         }
1703
1704         sas->ethdev_rxq_count = nb_rx_queues;
1705 }
1706
1707 /**
1708  * Initialize Rx subsystem.
1709  *
1710  * Called at device (re)configuration stage when number of receive queues is
1711  * specified together with other device level receive configuration.
1712  *
1713  * It should be used to allocate NUMA-unaware resources.
1714  */
1715 int
1716 sfc_rx_configure(struct sfc_adapter *sa)
1717 {
1718         struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1719         struct sfc_rss *rss = &sas->rss;
1720         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1721         const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1722         const unsigned int nb_rsrv_rx_queues = sfc_nb_reserved_rxq(sas);
1723         const unsigned int nb_rxq_total = nb_rx_queues + nb_rsrv_rx_queues;
1724         bool reconfigure;
1725         int rc;
1726
1727         sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1728                      nb_rx_queues, sas->ethdev_rxq_count);
1729
1730         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1731         if (rc != 0)
1732                 goto fail_check_mode;
1733
1734         if (nb_rxq_total == sas->rxq_count) {
1735                 reconfigure = true;
1736                 goto configure_rss;
1737         }
1738
1739         if (sas->rxq_info == NULL) {
1740                 reconfigure = false;
1741                 rc = ENOMEM;
1742                 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rxq_total,
1743                                                   sizeof(sas->rxq_info[0]), 0,
1744                                                   sa->socket_id);
1745                 if (sas->rxq_info == NULL)
1746                         goto fail_rxqs_alloc;
1747
1748                 /*
1749                  * Allocate primary process only RxQ control from heap
1750                  * since it should not be shared.
1751                  */
1752                 rc = ENOMEM;
1753                 sa->rxq_ctrl = calloc(nb_rxq_total, sizeof(sa->rxq_ctrl[0]));
1754                 if (sa->rxq_ctrl == NULL)
1755                         goto fail_rxqs_ctrl_alloc;
1756         } else {
1757                 struct sfc_rxq_info *new_rxq_info;
1758                 struct sfc_rxq *new_rxq_ctrl;
1759
1760                 reconfigure = true;
1761
1762                 /* Do not ununitialize reserved queues */
1763                 if (nb_rx_queues < sas->ethdev_rxq_count)
1764                         sfc_rx_fini_queues(sa, nb_rx_queues);
1765
1766                 rc = ENOMEM;
1767                 new_rxq_info =
1768                         rte_realloc(sas->rxq_info,
1769                                     nb_rxq_total * sizeof(sas->rxq_info[0]), 0);
1770                 if (new_rxq_info == NULL && nb_rxq_total > 0)
1771                         goto fail_rxqs_realloc;
1772
1773                 rc = ENOMEM;
1774                 new_rxq_ctrl = realloc(sa->rxq_ctrl,
1775                                        nb_rxq_total * sizeof(sa->rxq_ctrl[0]));
1776                 if (new_rxq_ctrl == NULL && nb_rxq_total > 0)
1777                         goto fail_rxqs_ctrl_realloc;
1778
1779                 sas->rxq_info = new_rxq_info;
1780                 sa->rxq_ctrl = new_rxq_ctrl;
1781                 if (nb_rxq_total > sas->rxq_count) {
1782                         unsigned int rxq_count = sas->rxq_count;
1783
1784                         memset(&sas->rxq_info[rxq_count], 0,
1785                                (nb_rxq_total - rxq_count) *
1786                                sizeof(sas->rxq_info[0]));
1787                         memset(&sa->rxq_ctrl[rxq_count], 0,
1788                                (nb_rxq_total - rxq_count) *
1789                                sizeof(sa->rxq_ctrl[0]));
1790                 }
1791         }
1792
1793         while (sas->ethdev_rxq_count < nb_rx_queues) {
1794                 sfc_sw_index_t sw_index;
1795
1796                 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1797                                                         sas->ethdev_rxq_count);
1798                 rc = sfc_rx_qinit_info(sa, sw_index, 0);
1799                 if (rc != 0)
1800                         goto fail_rx_qinit_info;
1801
1802                 sas->ethdev_rxq_count++;
1803         }
1804
1805         sas->rxq_count = sas->ethdev_rxq_count + nb_rsrv_rx_queues;
1806
1807         if (!reconfigure) {
1808                 rc = sfc_mae_counter_rxq_init(sa);
1809                 if (rc != 0)
1810                         goto fail_count_rxq_init;
1811         }
1812
1813 configure_rss:
1814         rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1815                          MIN(sas->ethdev_rxq_count, EFX_MAXRSS) : 0;
1816
1817         if (rss->channels > 0) {
1818                 struct rte_eth_rss_conf *adv_conf_rss;
1819                 sfc_sw_index_t sw_index;
1820
1821                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1822                         rss->tbl[sw_index] = sw_index % rss->channels;
1823
1824                 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1825                 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1826                 if (rc != 0)
1827                         goto fail_rx_process_adv_conf_rss;
1828         }
1829
1830         return 0;
1831
1832 fail_rx_process_adv_conf_rss:
1833         if (!reconfigure)
1834                 sfc_mae_counter_rxq_fini(sa);
1835
1836 fail_count_rxq_init:
1837 fail_rx_qinit_info:
1838 fail_rxqs_ctrl_realloc:
1839 fail_rxqs_realloc:
1840 fail_rxqs_ctrl_alloc:
1841 fail_rxqs_alloc:
1842         sfc_rx_close(sa);
1843
1844 fail_check_mode:
1845         sfc_log_init(sa, "failed %d", rc);
1846         return rc;
1847 }
1848
1849 /**
1850  * Shutdown Rx subsystem.
1851  *
1852  * Called at device close stage, for example, before device shutdown.
1853  */
1854 void
1855 sfc_rx_close(struct sfc_adapter *sa)
1856 {
1857         struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1858
1859         sfc_rx_fini_queues(sa, 0);
1860         sfc_mae_counter_rxq_fini(sa);
1861
1862         rss->channels = 0;
1863
1864         free(sa->rxq_ctrl);
1865         sa->rxq_ctrl = NULL;
1866
1867         rte_free(sfc_sa2shared(sa)->rxq_info);
1868         sfc_sa2shared(sa)->rxq_info = NULL;
1869 }