1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2016-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 #include <rte_mempool.h>
15 #include "sfc_debug.h"
19 #include "sfc_kvargs.h"
20 #include "sfc_tweak.h"
23 * Maximum number of Rx queue flush attempt in the case of failure or
26 #define SFC_RX_QFLUSH_ATTEMPTS (3)
29 * Time to wait between event queue polling attempts when waiting for Rx
30 * queue flush done or failed events.
32 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1)
35 * Maximum number of event queue polling attempts when waiting for Rx queue
36 * flush done or failed events. It defines Rx queue flush attempt timeout
37 * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000)
42 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info)
44 rxq_info->state |= SFC_RXQ_FLUSHED;
45 rxq_info->state &= ~SFC_RXQ_FLUSHING;
49 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info)
51 rxq_info->state |= SFC_RXQ_FLUSH_FAILED;
52 rxq_info->state &= ~SFC_RXQ_FLUSHING;
56 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq)
60 if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) {
61 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr);
63 rxq->evq->read_ptr_primed = rxq->evq->read_ptr;
69 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
71 unsigned int free_space;
73 void *objs[SFC_RX_REFILL_BULK];
74 efsys_dma_addr_t addr[RTE_DIM(objs)];
75 unsigned int added = rxq->added;
78 struct sfc_efx_rx_sw_desc *rxd;
80 uint16_t port_id = rxq->dp.dpq.port_id;
82 free_space = rxq->max_fill_level - (added - rxq->completed);
84 if (free_space < rxq->refill_threshold)
87 bulks = free_space / RTE_DIM(objs);
88 /* refill_threshold guarantees that bulks is positive */
89 SFC_ASSERT(bulks > 0);
91 id = added & rxq->ptr_mask;
93 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
94 RTE_DIM(objs)) < 0)) {
96 * It is hardly a safe way to increment counter
97 * from different contexts, but all PMDs do it.
99 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
101 /* Return if we have posted nothing yet */
102 if (added == rxq->added)
108 for (i = 0; i < RTE_DIM(objs);
109 ++i, id = (id + 1) & rxq->ptr_mask) {
112 __rte_mbuf_raw_sanity_check(m);
114 rxd = &rxq->sw_desc[id];
117 m->data_off = RTE_PKTMBUF_HEADROOM;
120 addr[i] = rte_pktmbuf_iova(m);
123 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
124 RTE_DIM(objs), rxq->completed, added);
125 added += RTE_DIM(objs);
126 } while (--bulks > 0);
128 SFC_ASSERT(added != rxq->added);
130 efx_rx_qpush(rxq->common, added, &rxq->pushed);
134 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
136 uint64_t mbuf_flags = 0;
138 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
139 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
140 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
143 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
146 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
147 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
148 PKT_RX_IP_CKSUM_UNKNOWN);
152 switch ((desc_flags &
153 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
154 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
155 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
156 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
160 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
163 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
164 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
165 PKT_RX_L4_CKSUM_UNKNOWN);
173 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
175 return RTE_PTYPE_L2_ETHER |
176 ((desc_flags & EFX_PKT_IPV4) ?
177 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
178 ((desc_flags & EFX_PKT_IPV6) ?
179 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
180 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
181 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
184 static const uint32_t *
185 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps)
187 static const uint32_t ptypes[] = {
189 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
190 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
200 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
206 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
209 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
211 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
212 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
213 EFX_RX_HASHALG_TOEPLITZ,
216 m->ol_flags |= PKT_RX_RSS_HASH;
221 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
223 struct sfc_dp_rxq *dp_rxq = rx_queue;
224 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
225 unsigned int completed;
226 unsigned int prefix_size = rxq->prefix_size;
227 unsigned int done_pkts = 0;
228 boolean_t discard_next = B_FALSE;
229 struct rte_mbuf *scatter_pkt = NULL;
231 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
234 sfc_ev_qpoll(rxq->evq);
236 completed = rxq->completed;
237 while (completed != rxq->pending && done_pkts < nb_pkts) {
239 struct sfc_efx_rx_sw_desc *rxd;
241 unsigned int seg_len;
242 unsigned int desc_flags;
244 id = completed++ & rxq->ptr_mask;
245 rxd = &rxq->sw_desc[id];
247 desc_flags = rxd->flags;
252 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
255 if (desc_flags & EFX_PKT_PREFIX_LEN) {
259 rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
260 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
264 seg_len = rxd->size - prefix_size;
267 rte_pktmbuf_data_len(m) = seg_len;
268 rte_pktmbuf_pkt_len(m) = seg_len;
270 if (scatter_pkt != NULL) {
271 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
272 rte_pktmbuf_free(scatter_pkt);
275 /* The packet to deliver */
279 if (desc_flags & EFX_PKT_CONT) {
280 /* The packet is scattered, more fragments to come */
282 /* Further fragments have no prefix */
287 /* Scattered packet is done */
289 /* The first fragment of the packet has prefix */
290 prefix_size = rxq->prefix_size;
293 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
295 sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
298 * Extract RSS hash from the packet prefix and
299 * set the corresponding field (if needed and possible)
301 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
303 m->data_off += prefix_size;
310 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
311 rte_mbuf_raw_free(m);
315 /* pending is only moved when entire packet is received */
316 SFC_ASSERT(scatter_pkt == NULL);
318 rxq->completed = completed;
320 sfc_efx_rx_qrefill(rxq);
322 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN)
323 sfc_efx_rx_qprime(rxq);
328 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
330 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
332 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
334 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
337 sfc_ev_qpoll(rxq->evq);
339 return rxq->pending - rxq->completed;
342 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status;
344 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset)
346 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
348 if (unlikely(offset > rxq->ptr_mask))
352 * Poll EvQ to derive up-to-date 'rxq->pending' figure;
353 * it is required for the queue to be running, but the
354 * check is omitted because API design assumes that it
355 * is the duty of the caller to satisfy all conditions
357 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) ==
358 SFC_EFX_RXQ_FLAG_RUNNING);
359 sfc_ev_qpoll(rxq->evq);
362 * There is a handful of reserved entries in the ring,
363 * but an explicit check whether the offset points to
364 * a reserved entry is neglected since the two checks
365 * below rely on the figures which take the HW limits
366 * into account and thus if an entry is reserved, the
367 * checks will fail and UNAVAIL code will be returned
370 if (offset < (rxq->pending - rxq->completed))
371 return RTE_ETH_RX_DESC_DONE;
373 if (offset < (rxq->added - rxq->completed))
374 return RTE_ETH_RX_DESC_AVAIL;
376 return RTE_ETH_RX_DESC_UNAVAIL;
380 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size,
381 boolean_t rx_scatter_enabled, uint32_t rx_scatter_max,
384 uint32_t effective_rx_scatter_max;
385 uint32_t rx_scatter_bufs;
387 effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1;
388 rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size);
390 if (rx_scatter_bufs > effective_rx_scatter_max) {
391 if (rx_scatter_enabled)
392 *error = "Possible number of Rx scatter buffers exceeds maximum number";
394 *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small";
401 /** Get Rx datapath ops by the datapath RxQ handle */
402 const struct sfc_dp_rx *
403 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
405 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
406 struct rte_eth_dev *eth_dev;
407 struct sfc_adapter_priv *sap;
409 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
410 eth_dev = &rte_eth_devices[dpq->port_id];
412 sap = sfc_adapter_priv_by_eth_dev(eth_dev);
417 struct sfc_rxq_info *
418 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
420 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
421 struct rte_eth_dev *eth_dev;
422 struct sfc_adapter_shared *sas;
424 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
425 eth_dev = &rte_eth_devices[dpq->port_id];
427 sas = sfc_adapter_shared_by_eth_dev(eth_dev);
429 SFC_ASSERT(dpq->queue_id < sas->rxq_count);
430 return &sas->rxq_info[dpq->queue_id];
434 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
436 const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
437 struct rte_eth_dev *eth_dev;
438 struct sfc_adapter *sa;
440 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
441 eth_dev = &rte_eth_devices[dpq->port_id];
443 sa = sfc_adapter_by_eth_dev(eth_dev);
445 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count);
446 return &sa->rxq_ctrl[dpq->queue_id];
449 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings;
451 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc,
452 __rte_unused struct sfc_dp_rx_hw_limits *limits,
453 __rte_unused struct rte_mempool *mb_pool,
454 unsigned int *rxq_entries,
455 unsigned int *evq_entries,
456 unsigned int *rxq_max_fill_level)
458 *rxq_entries = nb_rx_desc;
459 *evq_entries = nb_rx_desc;
460 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries);
464 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
466 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
467 const struct rte_pci_addr *pci_addr, int socket_id,
468 const struct sfc_dp_rx_qcreate_info *info,
469 struct sfc_dp_rxq **dp_rxqp)
471 struct sfc_efx_rxq *rxq;
475 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
476 RTE_CACHE_LINE_SIZE, socket_id);
480 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
483 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
485 sizeof(*rxq->sw_desc),
486 RTE_CACHE_LINE_SIZE, socket_id);
487 if (rxq->sw_desc == NULL)
488 goto fail_desc_alloc;
490 /* efx datapath is bound to efx control path */
491 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
492 if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
493 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
494 rxq->ptr_mask = info->rxq_entries - 1;
495 rxq->batch_max = info->batch_max;
496 rxq->prefix_size = info->prefix_size;
497 rxq->max_fill_level = info->max_fill_level;
498 rxq->refill_threshold = info->refill_threshold;
499 rxq->buf_size = info->buf_size;
500 rxq->refill_mb_pool = info->refill_mb_pool;
512 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
514 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
516 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
518 rte_free(rxq->sw_desc);
523 /* Use qstop and qstart functions in the case of qstart failure */
524 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
525 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
528 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
530 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
531 __rte_unused unsigned int evq_read_ptr,
532 const efx_rx_prefix_layout_t *pinfo)
534 /* libefx-based datapath is specific to libefx-based PMD */
535 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
536 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
540 * libefx API is used to extract information from Rx prefix and
541 * it guarantees consistency. Just do length check to ensure
542 * that we reserved space in Rx buffers correctly.
544 if (rxq->prefix_size != pinfo->erpl_length)
547 rxq->common = crxq->common;
549 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
551 sfc_efx_rx_qrefill(rxq);
553 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
555 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) {
556 rc = sfc_efx_rx_qprime(rxq);
564 sfc_efx_rx_qstop(dp_rxq, NULL);
565 sfc_efx_rx_qpurge(dp_rxq);
570 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
571 __rte_unused unsigned int *evq_read_ptr)
573 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
575 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
577 /* libefx-based datapath is bound to libefx-based PMD and uses
578 * event queue structure directly. So, there is no necessity to
579 * return EvQ read pointer.
584 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
586 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
588 struct sfc_efx_rx_sw_desc *rxd;
590 for (i = rxq->completed; i != rxq->added; ++i) {
591 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
592 rte_mbuf_raw_free(rxd->mbuf);
594 /* Packed stream relies on 0 in inactive SW desc.
595 * Rx queue stop is not performance critical, so
596 * there is no harm to do it always.
602 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
605 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable;
607 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq)
609 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
612 rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN;
613 if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) {
614 rc = sfc_efx_rx_qprime(rxq);
616 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
621 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable;
623 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq)
625 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
627 /* Cannot disarm, just disable rearm */
628 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN;
632 struct sfc_dp_rx sfc_efx_rx = {
634 .name = SFC_KVARG_DATAPATH_EFX,
636 .hw_fw_caps = SFC_DP_HW_FW_CAP_RX_EFX,
638 .features = SFC_DP_RX_FEAT_INTR,
639 .dev_offload_capa = DEV_RX_OFFLOAD_CHECKSUM |
640 DEV_RX_OFFLOAD_RSS_HASH,
641 .queue_offload_capa = DEV_RX_OFFLOAD_SCATTER,
642 .qsize_up_rings = sfc_efx_rx_qsize_up_rings,
643 .qcreate = sfc_efx_rx_qcreate,
644 .qdestroy = sfc_efx_rx_qdestroy,
645 .qstart = sfc_efx_rx_qstart,
646 .qstop = sfc_efx_rx_qstop,
647 .qpurge = sfc_efx_rx_qpurge,
648 .supported_ptypes_get = sfc_efx_supported_ptypes_get,
649 .qdesc_npending = sfc_efx_rx_qdesc_npending,
650 .qdesc_status = sfc_efx_rx_qdesc_status,
651 .intr_enable = sfc_efx_rx_intr_enable,
652 .intr_disable = sfc_efx_rx_intr_disable,
653 .pkt_burst = sfc_efx_recv_pkts,
657 sfc_rx_qflush(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
659 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
660 sfc_ethdev_qid_t ethdev_qid;
661 struct sfc_rxq_info *rxq_info;
663 unsigned int retry_count;
664 unsigned int wait_count;
667 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
668 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
669 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
671 rxq = &sa->rxq_ctrl[sw_index];
674 * Retry Rx queue flushing in the case of flush failed or
675 * timeout. In the worst case it can delay for 6 seconds.
677 for (retry_count = 0;
678 ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) &&
679 (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
681 rc = efx_rx_qflush(rxq->common);
683 rxq_info->state |= (rc == EALREADY) ?
684 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED;
687 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED;
688 rxq_info->state |= SFC_RXQ_FLUSHING;
691 * Wait for Rx queue flush done or failed event at least
692 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
693 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
694 * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
698 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
699 sfc_ev_qpoll(rxq->evq);
700 } while ((rxq_info->state & SFC_RXQ_FLUSHING) &&
701 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
703 if (rxq_info->state & SFC_RXQ_FLUSHING)
704 sfc_err(sa, "RxQ %d (internal %u) flush timed out",
705 ethdev_qid, sw_index);
707 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED)
708 sfc_err(sa, "RxQ %d (internal %u) flush failed",
709 ethdev_qid, sw_index);
711 if (rxq_info->state & SFC_RXQ_FLUSHED)
712 sfc_notice(sa, "RxQ %d (internal %u) flushed",
713 ethdev_qid, sw_index);
716 sa->priv.dp_rx->qpurge(rxq_info->dp);
720 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
722 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
723 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE;
724 struct sfc_port *port = &sa->port;
728 * If promiscuous or all-multicast mode has been requested, setting
729 * filter for the default Rx queue might fail, in particular, while
730 * running over PCI function which is not a member of corresponding
731 * privilege groups; if this occurs, few iterations will be made to
732 * repeat this step without promiscuous and all-multicast flags set
735 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss);
738 else if (rc != EOPNOTSUPP)
742 sfc_warn(sa, "promiscuous mode has been requested, "
743 "but the HW rejects it");
744 sfc_warn(sa, "promiscuous mode will be disabled");
746 port->promisc = B_FALSE;
747 sa->eth_dev->data->promiscuous = 0;
748 rc = sfc_set_rx_mode_unchecked(sa);
755 if (port->allmulti) {
756 sfc_warn(sa, "all-multicast mode has been requested, "
757 "but the HW rejects it");
758 sfc_warn(sa, "all-multicast mode will be disabled");
760 port->allmulti = B_FALSE;
761 sa->eth_dev->data->all_multicast = 0;
762 rc = sfc_set_rx_mode_unchecked(sa);
773 sfc_rx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
775 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
776 sfc_ethdev_qid_t ethdev_qid;
777 struct sfc_rxq_info *rxq_info;
780 efx_rx_prefix_layout_t pinfo;
783 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
784 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
786 sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
788 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
789 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
791 rxq = &sa->rxq_ctrl[sw_index];
794 rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index));
798 switch (rxq_info->type) {
799 case EFX_RXQ_TYPE_DEFAULT:
800 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
802 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */,
803 rxq_info->type_flags, evq->common, &rxq->common);
805 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: {
806 struct rte_mempool *mp = rxq_info->refill_mb_pool;
807 struct rte_mempool_info mp_info;
809 rc = rte_mempool_ops_get_info(mp, &mp_info);
811 /* Positive errno is used in the driver */
813 goto fail_mp_get_info;
815 if (mp_info.contig_block_size <= 0) {
817 goto fail_bad_contig_block_size;
819 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0,
820 mp_info.contig_block_size, rxq->buf_size,
821 mp->header_size + mp->elt_size + mp->trailer_size,
822 sa->rxd_wait_timeout_ns,
823 &rxq->mem, rxq_info->entries, rxq_info->type_flags,
824 evq->common, &rxq->common);
831 goto fail_rx_qcreate;
833 rc = efx_rx_prefix_get_layout(rxq->common, &pinfo);
835 goto fail_prefix_get_layout;
837 efx_rx_qenable(rxq->common);
839 rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr, &pinfo);
843 rxq_info->state |= SFC_RXQ_STARTED;
845 if (ethdev_qid == 0 && !sfc_sa2shared(sa)->isolated) {
846 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
848 goto fail_mac_filter_default_rxq_set;
851 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
852 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
853 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
854 RTE_ETH_QUEUE_STATE_STARTED;
858 fail_mac_filter_default_rxq_set:
859 sfc_rx_qflush(sa, sw_index);
860 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
861 rxq_info->state = SFC_RXQ_INITIALIZED;
864 efx_rx_qdestroy(rxq->common);
866 fail_prefix_get_layout:
868 fail_bad_contig_block_size:
877 sfc_rx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
879 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
880 sfc_ethdev_qid_t ethdev_qid;
881 struct sfc_rxq_info *rxq_info;
884 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
885 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
887 sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index);
889 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
891 if (rxq_info->state == SFC_RXQ_INITIALIZED)
893 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED);
895 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
896 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
897 sa->eth_dev->data->rx_queue_state[ethdev_qid] =
898 RTE_ETH_QUEUE_STATE_STOPPED;
900 rxq = &sa->rxq_ctrl[sw_index];
901 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr);
904 efx_mac_filter_default_rxq_clear(sa->nic);
906 sfc_rx_qflush(sa, sw_index);
908 rxq_info->state = SFC_RXQ_INITIALIZED;
910 efx_rx_qdestroy(rxq->common);
912 sfc_ev_qstop(rxq->evq);
916 sfc_rx_get_offload_mask(struct sfc_adapter *sa)
918 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
919 uint64_t no_caps = 0;
921 if (encp->enc_tunnel_encapsulations_supported == 0)
922 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
928 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa)
930 uint64_t caps = sa->priv.dp_rx->dev_offload_capa;
932 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME;
934 return caps & sfc_rx_get_offload_mask(sa);
938 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa)
940 return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa);
944 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level,
945 const struct rte_eth_rxconf *rx_conf,
946 __rte_unused uint64_t offloads)
950 if (rx_conf->rx_thresh.pthresh != 0 ||
951 rx_conf->rx_thresh.hthresh != 0 ||
952 rx_conf->rx_thresh.wthresh != 0) {
954 "RxQ prefetch/host/writeback thresholds are not supported");
957 if (rx_conf->rx_free_thresh > rxq_max_fill_level) {
959 "RxQ free threshold too large: %u vs maximum %u",
960 rx_conf->rx_free_thresh, rxq_max_fill_level);
964 if (rx_conf->rx_drop_en == 0) {
965 sfc_err(sa, "RxQ drop disable is not supported");
973 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
978 /* The mbuf object itself is always cache line aligned */
979 order = rte_bsf32(RTE_CACHE_LINE_SIZE);
981 /* Data offset from mbuf object start */
982 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
983 RTE_PKTMBUF_HEADROOM;
985 order = MIN(order, rte_bsf32(data_off));
991 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
993 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
994 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
995 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
997 unsigned int buf_aligned;
998 unsigned int start_alignment;
999 unsigned int end_padding_alignment;
1001 /* Below it is assumed that both alignments are power of 2 */
1002 SFC_ASSERT(rte_is_power_of_2(nic_align_start));
1003 SFC_ASSERT(rte_is_power_of_2(nic_align_end));
1006 * mbuf is always cache line aligned, double-check
1007 * that it meets rx buffer start alignment requirements.
1010 /* Start from mbuf pool data room size */
1011 buf_size = rte_pktmbuf_data_room_size(mb_pool);
1013 /* Remove headroom */
1014 if (buf_size <= RTE_PKTMBUF_HEADROOM) {
1016 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
1017 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
1020 buf_size -= RTE_PKTMBUF_HEADROOM;
1022 /* Calculate guaranteed data start alignment */
1023 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
1025 /* Reserve space for start alignment */
1026 if (buf_aligned < nic_align_start) {
1027 start_alignment = nic_align_start - buf_aligned;
1028 if (buf_size <= start_alignment) {
1030 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
1032 rte_pktmbuf_data_room_size(mb_pool),
1033 RTE_PKTMBUF_HEADROOM, start_alignment);
1036 buf_aligned = nic_align_start;
1037 buf_size -= start_alignment;
1039 start_alignment = 0;
1042 /* Make sure that end padding does not write beyond the buffer */
1043 if (buf_aligned < nic_align_end) {
1045 * Estimate space which can be lost. If guarnteed buffer
1046 * size is odd, lost space is (nic_align_end - 1). More
1047 * accurate formula is below.
1049 end_padding_alignment = nic_align_end -
1050 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
1051 if (buf_size <= end_padding_alignment) {
1053 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
1055 rte_pktmbuf_data_room_size(mb_pool),
1056 RTE_PKTMBUF_HEADROOM, start_alignment,
1057 end_padding_alignment);
1060 buf_size -= end_padding_alignment;
1063 * Start is aligned the same or better than end,
1064 * just align length.
1066 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end);
1073 sfc_rx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1074 uint16_t nb_rx_desc, unsigned int socket_id,
1075 const struct rte_eth_rxconf *rx_conf,
1076 struct rte_mempool *mb_pool)
1078 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1079 sfc_ethdev_qid_t ethdev_qid;
1080 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1081 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1083 unsigned int rxq_entries;
1084 unsigned int evq_entries;
1085 unsigned int rxq_max_fill_level;
1088 struct sfc_rxq_info *rxq_info;
1089 struct sfc_evq *evq;
1090 struct sfc_rxq *rxq;
1091 struct sfc_dp_rx_qcreate_info info;
1092 struct sfc_dp_rx_hw_limits hw_limits;
1093 uint16_t rx_free_thresh;
1096 memset(&hw_limits, 0, sizeof(hw_limits));
1097 hw_limits.rxq_max_entries = sa->rxq_max_entries;
1098 hw_limits.rxq_min_entries = sa->rxq_min_entries;
1099 hw_limits.evq_max_entries = sa->evq_max_entries;
1100 hw_limits.evq_min_entries = sa->evq_min_entries;
1102 rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool,
1103 &rxq_entries, &evq_entries,
1104 &rxq_max_fill_level);
1106 goto fail_size_up_rings;
1107 SFC_ASSERT(rxq_entries >= sa->rxq_min_entries);
1108 SFC_ASSERT(rxq_entries <= sa->rxq_max_entries);
1109 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc);
1111 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1113 offloads = rx_conf->offloads;
1114 /* Add device level Rx offloads if the queue is an ethdev Rx queue */
1115 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1116 offloads |= sa->eth_dev->data->dev_conf.rxmode.offloads;
1118 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads);
1122 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
1123 if (buf_size == 0) {
1125 "RxQ %d (internal %u) mbuf pool object size is too small",
1126 ethdev_qid, sw_index);
1131 if (!sfc_rx_check_scatter(sa->port.pdu, buf_size,
1132 encp->enc_rx_prefix_size,
1133 (offloads & DEV_RX_OFFLOAD_SCATTER),
1134 encp->enc_rx_scatter_max,
1136 sfc_err(sa, "RxQ %d (internal %u) MTU check failed: %s",
1137 ethdev_qid, sw_index, error);
1139 "RxQ %d (internal %u) calculated Rx buffer size is %u vs "
1140 "PDU size %u plus Rx prefix %u bytes",
1141 ethdev_qid, sw_index, buf_size,
1142 (unsigned int)sa->port.pdu, encp->enc_rx_prefix_size);
1147 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1148 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1150 SFC_ASSERT(rxq_entries <= rxq_info->max_entries);
1151 rxq_info->entries = rxq_entries;
1153 if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER)
1154 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER;
1156 rxq_info->type = EFX_RXQ_TYPE_DEFAULT;
1158 rxq_info->type_flags |=
1159 (offloads & DEV_RX_OFFLOAD_SCATTER) ?
1160 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE;
1162 if ((encp->enc_tunnel_encapsulations_supported != 0) &&
1163 (sfc_dp_rx_offload_capa(sa->priv.dp_rx) &
1164 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0)
1165 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES;
1167 if (offloads & DEV_RX_OFFLOAD_RSS_HASH)
1168 rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH;
1170 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index,
1171 evq_entries, socket_id, &evq);
1175 rxq = &sa->rxq_ctrl[sw_index];
1177 rxq->hw_index = sw_index;
1179 * If Rx refill threshold is specified (its value is non zero) in
1180 * Rx configuration, use specified value. Otherwise use 1/8 of
1181 * the Rx descriptors number as the default. It allows to keep
1182 * Rx ring full-enough and does not refill too aggressive if
1183 * packet rate is high.
1185 * Since PMD refills in bulks waiting for full bulk may be
1186 * refilled (basically round down), it is better to round up
1187 * here to mitigate it a bit.
1189 rx_free_thresh = (rx_conf->rx_free_thresh != 0) ?
1190 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8);
1191 /* Rx refill threshold cannot be smaller than refill bulk */
1192 rxq_info->refill_threshold =
1193 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK);
1194 rxq_info->refill_mb_pool = mb_pool;
1196 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 &&
1197 (offloads & DEV_RX_OFFLOAD_RSS_HASH))
1198 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH;
1200 rxq_info->rxq_flags = 0;
1202 rxq->buf_size = buf_size;
1204 rc = sfc_dma_alloc(sa, "rxq", sw_index,
1205 efx_rxq_size(sa->nic, rxq_info->entries),
1206 socket_id, &rxq->mem);
1208 goto fail_dma_alloc;
1210 memset(&info, 0, sizeof(info));
1211 info.refill_mb_pool = rxq_info->refill_mb_pool;
1212 info.max_fill_level = rxq_max_fill_level;
1213 info.refill_threshold = rxq_info->refill_threshold;
1214 info.buf_size = buf_size;
1215 info.batch_max = encp->enc_rx_batch_max;
1216 info.prefix_size = encp->enc_rx_prefix_size;
1217 info.flags = rxq_info->rxq_flags;
1218 info.rxq_entries = rxq_info->entries;
1219 info.rxq_hw_ring = rxq->mem.esm_base;
1220 info.evq_hw_index = sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index);
1221 info.evq_entries = evq_entries;
1222 info.evq_hw_ring = evq->mem.esm_base;
1223 info.hw_index = rxq->hw_index;
1224 info.mem_bar = sa->mem_bar.esb_base;
1225 info.vi_window_shift = encp->enc_vi_window_shift;
1226 info.fcw_offset = sa->fcw_offset;
1228 rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
1229 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
1230 socket_id, &info, &rxq_info->dp);
1232 goto fail_dp_rx_qcreate;
1234 evq->dp_rxq = rxq_info->dp;
1236 rxq_info->state = SFC_RXQ_INITIALIZED;
1238 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
1243 sfc_dma_free(sa, &rxq->mem);
1249 rxq_info->entries = 0;
1253 sfc_log_init(sa, "failed %d", rc);
1258 sfc_rx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
1260 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1261 sfc_ethdev_qid_t ethdev_qid;
1262 struct sfc_rxq_info *rxq_info;
1263 struct sfc_rxq *rxq;
1265 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count);
1266 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index);
1268 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
1269 sa->eth_dev->data->rx_queues[ethdev_qid] = NULL;
1271 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index];
1273 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED);
1275 sa->priv.dp_rx->qdestroy(rxq_info->dp);
1276 rxq_info->dp = NULL;
1278 rxq_info->state &= ~SFC_RXQ_INITIALIZED;
1279 rxq_info->entries = 0;
1281 rxq = &sa->rxq_ctrl[sw_index];
1283 sfc_dma_free(sa, &rxq->mem);
1285 sfc_ev_qfini(rxq->evq);
1290 * Mapping between RTE RSS hash functions and their EFX counterparts.
1292 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = {
1293 { ETH_RSS_NONFRAG_IPV4_TCP,
1294 EFX_RX_HASH(IPV4_TCP, 4TUPLE) },
1295 { ETH_RSS_NONFRAG_IPV4_UDP,
1296 EFX_RX_HASH(IPV4_UDP, 4TUPLE) },
1297 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX,
1298 EFX_RX_HASH(IPV6_TCP, 4TUPLE) },
1299 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX,
1300 EFX_RX_HASH(IPV6_UDP, 4TUPLE) },
1301 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER,
1302 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) |
1303 EFX_RX_HASH(IPV4, 2TUPLE) },
1304 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER |
1306 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) |
1307 EFX_RX_HASH(IPV6, 2TUPLE) }
1310 static efx_rx_hash_type_t
1311 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type,
1312 unsigned int *hash_type_flags_supported,
1313 unsigned int nb_hash_type_flags_supported)
1315 efx_rx_hash_type_t hash_type_masked = 0;
1318 for (i = 0; i < nb_hash_type_flags_supported; ++i) {
1319 unsigned int class_tuple_lbn[] = {
1320 EFX_RX_CLASS_IPV4_TCP_LBN,
1321 EFX_RX_CLASS_IPV4_UDP_LBN,
1322 EFX_RX_CLASS_IPV4_LBN,
1323 EFX_RX_CLASS_IPV6_TCP_LBN,
1324 EFX_RX_CLASS_IPV6_UDP_LBN,
1325 EFX_RX_CLASS_IPV6_LBN
1328 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) {
1329 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE;
1332 tuple_mask <<= class_tuple_lbn[j];
1333 flag = hash_type & tuple_mask;
1335 if (flag == hash_type_flags_supported[i])
1336 hash_type_masked |= flag;
1340 return hash_type_masked;
1344 sfc_rx_hash_init(struct sfc_adapter *sa)
1346 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1347 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1348 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask;
1349 efx_rx_hash_alg_t alg;
1350 unsigned int flags_supp[EFX_RX_HASH_NFLAGS];
1351 unsigned int nb_flags_supp;
1352 struct sfc_rss_hf_rte_to_efx *hf_map;
1353 struct sfc_rss_hf_rte_to_efx *entry;
1354 efx_rx_hash_type_t efx_hash_types;
1358 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ))
1359 alg = EFX_RX_HASHALG_TOEPLITZ;
1360 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM))
1361 alg = EFX_RX_HASHALG_PACKED_STREAM;
1365 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp,
1366 RTE_DIM(flags_supp), &nb_flags_supp);
1370 hf_map = rte_calloc_socket("sfc-rss-hf-map",
1371 RTE_DIM(sfc_rss_hf_map),
1372 sizeof(*hf_map), 0, sa->socket_id);
1378 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) {
1379 efx_rx_hash_type_t ht;
1381 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx,
1382 flags_supp, nb_flags_supp);
1384 entry->rte = sfc_rss_hf_map[i].rte;
1386 efx_hash_types |= ht;
1391 rss->hash_alg = alg;
1392 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map);
1393 rss->hf_map = hf_map;
1394 rss->hash_types = efx_hash_types;
1400 sfc_rx_hash_fini(struct sfc_adapter *sa)
1402 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1404 rte_free(rss->hf_map);
1408 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte,
1409 efx_rx_hash_type_t *efx)
1411 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1412 efx_rx_hash_type_t hash_types = 0;
1415 for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1416 uint64_t rte_mask = rss->hf_map[i].rte;
1418 if ((rte & rte_mask) != 0) {
1420 hash_types |= rss->hf_map[i].efx;
1425 sfc_err(sa, "unsupported hash functions requested");
1435 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx)
1440 for (i = 0; i < rss->hf_map_nb_entries; ++i) {
1441 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx;
1443 if ((efx & hash_type) == hash_type)
1444 rte |= rss->hf_map[i].rte;
1451 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa,
1452 struct rte_eth_rss_conf *conf)
1454 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1455 efx_rx_hash_type_t efx_hash_types = rss->hash_types;
1456 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types);
1459 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) {
1460 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) ||
1461 conf->rss_key != NULL)
1465 if (conf->rss_hf != 0) {
1466 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types);
1471 if (conf->rss_key != NULL) {
1472 if (conf->rss_key_len != sizeof(rss->key)) {
1473 sfc_err(sa, "RSS key size is wrong (should be %zu)",
1477 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key));
1480 rss->hash_types = efx_hash_types;
1486 sfc_rx_rss_config(struct sfc_adapter *sa)
1488 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1491 if (rss->channels > 0) {
1492 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1493 rss->hash_alg, rss->hash_types,
1498 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1499 rss->key, sizeof(rss->key));
1503 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT,
1504 rss->tbl, RTE_DIM(rss->tbl));
1511 struct sfc_rxq_info *
1512 sfc_rxq_info_by_ethdev_qid(struct sfc_adapter_shared *sas,
1513 sfc_ethdev_qid_t ethdev_qid)
1515 sfc_sw_index_t sw_index;
1517 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1518 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1520 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1521 return &sas->rxq_info[sw_index];
1525 sfc_rxq_ctrl_by_ethdev_qid(struct sfc_adapter *sa, sfc_ethdev_qid_t ethdev_qid)
1527 struct sfc_adapter_shared *sas = sfc_sa2shared(sa);
1528 sfc_sw_index_t sw_index;
1530 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count);
1531 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
1533 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid);
1534 return &sa->rxq_ctrl[sw_index];
1538 sfc_rx_start(struct sfc_adapter *sa)
1540 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1541 sfc_sw_index_t sw_index;
1544 sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1547 rc = efx_rx_init(sa->nic);
1551 rc = sfc_rx_rss_config(sa);
1553 goto fail_rss_config;
1555 for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) {
1556 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED &&
1557 (!sas->rxq_info[sw_index].deferred_start ||
1558 sas->rxq_info[sw_index].deferred_started)) {
1559 rc = sfc_rx_qstart(sa, sw_index);
1561 goto fail_rx_qstart;
1568 while (sw_index-- > 0)
1569 sfc_rx_qstop(sa, sw_index);
1572 efx_rx_fini(sa->nic);
1575 sfc_log_init(sa, "failed %d", rc);
1580 sfc_rx_stop(struct sfc_adapter *sa)
1582 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1583 sfc_sw_index_t sw_index;
1585 sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count,
1588 sw_index = sas->rxq_count;
1589 while (sw_index-- > 0) {
1590 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED)
1591 sfc_rx_qstop(sa, sw_index);
1594 efx_rx_fini(sa->nic);
1598 sfc_rx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
1599 unsigned int extra_efx_type_flags)
1601 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1602 struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index];
1603 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
1604 unsigned int max_entries;
1606 max_entries = encp->enc_rxq_max_ndescs;
1607 SFC_ASSERT(rte_is_power_of_2(max_entries));
1609 rxq_info->max_entries = max_entries;
1610 rxq_info->type_flags = extra_efx_type_flags;
1616 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1618 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1619 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) |
1620 sfc_rx_get_queue_offload_caps(sa);
1621 struct sfc_rss *rss = &sas->rss;
1624 switch (rxmode->mq_mode) {
1625 case ETH_MQ_RX_NONE:
1626 /* No special checks are required */
1629 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) {
1630 sfc_err(sa, "RSS is not available");
1635 sfc_err(sa, "Rx multi-queue mode %u not supported",
1641 * Requested offloads are validated against supported by ethdev,
1642 * so unsupported offloads cannot be added as the result of
1645 if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) !=
1646 (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) {
1647 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)");
1648 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM;
1651 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) &&
1652 (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) {
1653 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on");
1654 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
1661 * Destroy excess queues that are no longer needed after reconfiguration
1662 * or complete close.
1665 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues)
1667 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1668 sfc_sw_index_t sw_index;
1669 sfc_ethdev_qid_t ethdev_qid;
1671 SFC_ASSERT(nb_rx_queues <= sas->ethdev_rxq_count);
1674 * Finalize only ethdev queues since other ones are finalized only
1675 * on device close and they may require additional deinitializaton.
1677 ethdev_qid = sas->ethdev_rxq_count;
1678 while (--ethdev_qid >= (int)nb_rx_queues) {
1679 struct sfc_rxq_info *rxq_info;
1681 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, ethdev_qid);
1682 if (rxq_info->state & SFC_RXQ_INITIALIZED) {
1683 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1685 sfc_rx_qfini(sa, sw_index);
1690 sas->ethdev_rxq_count = nb_rx_queues;
1694 * Initialize Rx subsystem.
1696 * Called at device (re)configuration stage when number of receive queues is
1697 * specified together with other device level receive configuration.
1699 * It should be used to allocate NUMA-unaware resources.
1702 sfc_rx_configure(struct sfc_adapter *sa)
1704 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
1705 struct sfc_rss *rss = &sas->rss;
1706 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1707 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues;
1710 sfc_log_init(sa, "nb_rx_queues=%u (old %u)",
1711 nb_rx_queues, sas->ethdev_rxq_count);
1713 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1715 goto fail_check_mode;
1717 if (nb_rx_queues == sas->rxq_count)
1720 if (sas->rxq_info == NULL) {
1722 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues,
1723 sizeof(sas->rxq_info[0]), 0,
1725 if (sas->rxq_info == NULL)
1726 goto fail_rxqs_alloc;
1729 * Allocate primary process only RxQ control from heap
1730 * since it should not be shared.
1733 sa->rxq_ctrl = calloc(nb_rx_queues, sizeof(sa->rxq_ctrl[0]));
1734 if (sa->rxq_ctrl == NULL)
1735 goto fail_rxqs_ctrl_alloc;
1737 struct sfc_rxq_info *new_rxq_info;
1738 struct sfc_rxq *new_rxq_ctrl;
1740 if (nb_rx_queues < sas->ethdev_rxq_count)
1741 sfc_rx_fini_queues(sa, nb_rx_queues);
1745 rte_realloc(sas->rxq_info,
1746 nb_rx_queues * sizeof(sas->rxq_info[0]), 0);
1747 if (new_rxq_info == NULL && nb_rx_queues > 0)
1748 goto fail_rxqs_realloc;
1751 new_rxq_ctrl = realloc(sa->rxq_ctrl,
1752 nb_rx_queues * sizeof(sa->rxq_ctrl[0]));
1753 if (new_rxq_ctrl == NULL && nb_rx_queues > 0)
1754 goto fail_rxqs_ctrl_realloc;
1756 sas->rxq_info = new_rxq_info;
1757 sa->rxq_ctrl = new_rxq_ctrl;
1758 if (nb_rx_queues > sas->rxq_count) {
1759 unsigned int rxq_count = sas->rxq_count;
1761 memset(&sas->rxq_info[rxq_count], 0,
1762 (nb_rx_queues - rxq_count) *
1763 sizeof(sas->rxq_info[0]));
1764 memset(&sa->rxq_ctrl[rxq_count], 0,
1765 (nb_rx_queues - rxq_count) *
1766 sizeof(sa->rxq_ctrl[0]));
1770 while (sas->ethdev_rxq_count < nb_rx_queues) {
1771 sfc_sw_index_t sw_index;
1773 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas,
1774 sas->ethdev_rxq_count);
1775 rc = sfc_rx_qinit_info(sa, sw_index, 0);
1777 goto fail_rx_qinit_info;
1779 sas->ethdev_rxq_count++;
1782 sas->rxq_count = sas->ethdev_rxq_count;
1785 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1786 MIN(sas->ethdev_rxq_count, EFX_MAXRSS) : 0;
1788 if (rss->channels > 0) {
1789 struct rte_eth_rss_conf *adv_conf_rss;
1790 sfc_sw_index_t sw_index;
1792 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1793 rss->tbl[sw_index] = sw_index % rss->channels;
1795 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf;
1796 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss);
1798 goto fail_rx_process_adv_conf_rss;
1803 fail_rx_process_adv_conf_rss:
1805 fail_rxqs_ctrl_realloc:
1807 fail_rxqs_ctrl_alloc:
1812 sfc_log_init(sa, "failed %d", rc);
1817 * Shutdown Rx subsystem.
1819 * Called at device close stage, for example, before device shutdown.
1822 sfc_rx_close(struct sfc_adapter *sa)
1824 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss;
1826 sfc_rx_fini_queues(sa, 0);
1831 sa->rxq_ctrl = NULL;
1833 rte_free(sfc_sa2shared(sa)->rxq_info);
1834 sfc_sa2shared(sa)->rxq_info = NULL;