1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2016-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
11 #include "sfc_debug.h"
15 #include "sfc_tweak.h"
16 #include "sfc_kvargs.h"
19 * Maximum number of TX queue flush attempts in case of
20 * failure or flush timeout
22 #define SFC_TX_QFLUSH_ATTEMPTS (3)
25 * Time to wait between event queue polling attempts when waiting for TX
26 * queue flush done or flush failed events
28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
31 * Maximum number of event queue polling attempts when waiting for TX queue
32 * flush done or flush failed events; it defines TX queue flush attempt timeout
33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
38 sfc_txq_info_by_ethdev_qid(struct sfc_adapter_shared *sas,
39 sfc_ethdev_qid_t ethdev_qid)
41 sfc_sw_index_t sw_index;
43 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_txq_count);
44 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
46 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid);
47 return &sas->txq_info[sw_index];
51 sfc_tx_get_offload_mask(struct sfc_adapter *sa)
53 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
56 if (!encp->enc_hw_tx_insert_vlan_enabled)
57 no_caps |= DEV_TX_OFFLOAD_VLAN_INSERT;
59 if (!encp->enc_tunnel_encapsulations_supported)
60 no_caps |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
63 no_caps |= DEV_TX_OFFLOAD_TCP_TSO;
66 (encp->enc_tunnel_encapsulations_supported &
67 (1u << EFX_TUNNEL_PROTOCOL_VXLAN)) == 0)
68 no_caps |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
71 (encp->enc_tunnel_encapsulations_supported &
72 (1u << EFX_TUNNEL_PROTOCOL_GENEVE)) == 0)
73 no_caps |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
79 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa)
81 return sa->priv.dp_tx->dev_offload_capa & sfc_tx_get_offload_mask(sa);
85 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa)
87 return sa->priv.dp_tx->queue_offload_capa & sfc_tx_get_offload_mask(sa);
91 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level,
92 const struct rte_eth_txconf *tx_conf,
97 if (tx_conf->tx_rs_thresh != 0) {
98 sfc_err(sa, "RS bit in transmit descriptor is not supported");
102 if (tx_conf->tx_free_thresh > txq_max_fill_level) {
104 "TxQ free threshold too large: %u vs maximum %u",
105 tx_conf->tx_free_thresh, txq_max_fill_level);
109 if (tx_conf->tx_thresh.pthresh != 0 ||
110 tx_conf->tx_thresh.hthresh != 0 ||
111 tx_conf->tx_thresh.wthresh != 0) {
113 "prefetch/host/writeback thresholds are not supported");
116 /* We either perform both TCP and UDP offload, or no offload at all */
117 if (((offloads & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) !=
118 ((offloads & DEV_TX_OFFLOAD_UDP_CKSUM) == 0)) {
119 sfc_err(sa, "TCP and UDP offloads can't be set independently");
127 sfc_tx_qflush_done(struct sfc_txq_info *txq_info)
129 txq_info->state |= SFC_TXQ_FLUSHED;
130 txq_info->state &= ~SFC_TXQ_FLUSHING;
134 sfc_tx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
135 uint16_t nb_tx_desc, unsigned int socket_id,
136 const struct rte_eth_txconf *tx_conf)
138 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
139 sfc_ethdev_qid_t ethdev_qid;
140 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
141 unsigned int txq_entries;
142 unsigned int evq_entries;
143 unsigned int txq_max_fill_level;
144 struct sfc_txq_info *txq_info;
148 struct sfc_dp_tx_qcreate_info info;
150 struct sfc_dp_tx_hw_limits hw_limits;
152 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
154 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
156 memset(&hw_limits, 0, sizeof(hw_limits));
157 hw_limits.txq_max_entries = sa->txq_max_entries;
158 hw_limits.txq_min_entries = sa->txq_min_entries;
160 rc = sa->priv.dp_tx->qsize_up_rings(nb_tx_desc, &hw_limits,
161 &txq_entries, &evq_entries,
162 &txq_max_fill_level);
164 goto fail_size_up_rings;
165 SFC_ASSERT(txq_entries >= sa->txq_min_entries);
166 SFC_ASSERT(txq_entries <= sa->txq_max_entries);
167 SFC_ASSERT(txq_entries >= nb_tx_desc);
168 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc);
170 offloads = tx_conf->offloads;
171 /* Add device level Tx offloads if the queue is an ethdev Tx queue */
172 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
173 offloads |= sa->eth_dev->data->dev_conf.txmode.offloads;
175 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf, offloads);
179 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
180 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
182 txq_info->entries = txq_entries;
184 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
185 evq_entries, socket_id, &evq);
189 txq = &sa->txq_ctrl[sw_index];
190 txq->hw_index = sw_index;
192 txq_info->free_thresh =
193 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
194 SFC_TX_DEFAULT_FREE_THRESH;
195 txq_info->offloads = offloads;
197 rc = sfc_dma_alloc(sa, "txq", sw_index,
198 efx_txq_size(sa->nic, txq_info->entries),
199 socket_id, &txq->mem);
203 memset(&info, 0, sizeof(info));
204 info.max_fill_level = txq_max_fill_level;
205 info.free_thresh = txq_info->free_thresh;
206 info.offloads = offloads;
207 info.txq_entries = txq_info->entries;
208 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
209 info.txq_hw_ring = txq->mem.esm_base;
210 info.evq_entries = evq_entries;
211 info.evq_hw_ring = evq->mem.esm_base;
212 info.hw_index = txq->hw_index;
213 info.mem_bar = sa->mem_bar.esb_base;
214 info.vi_window_shift = encp->enc_vi_window_shift;
215 info.tso_tcp_header_offset_limit =
216 encp->enc_tx_tso_tcp_header_offset_limit;
217 info.tso_max_nb_header_descs =
218 RTE_MIN(encp->enc_tx_tso_max_header_ndescs,
219 (uint32_t)UINT16_MAX);
220 info.tso_max_header_len =
221 RTE_MIN(encp->enc_tx_tso_max_header_length,
222 (uint32_t)UINT16_MAX);
223 info.tso_max_nb_payload_descs =
224 RTE_MIN(encp->enc_tx_tso_max_payload_ndescs,
225 (uint32_t)UINT16_MAX);
226 info.tso_max_payload_len = encp->enc_tx_tso_max_payload_length;
227 info.tso_max_nb_outgoing_frames = encp->enc_tx_tso_max_nframes;
229 rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
230 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
231 socket_id, &info, &txq_info->dp);
233 goto fail_dp_tx_qinit;
235 evq->dp_txq = txq_info->dp;
237 txq_info->state = SFC_TXQ_INITIALIZED;
239 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
244 sfc_dma_free(sa, &txq->mem);
250 txq_info->entries = 0;
254 sfc_log_init(sa, "failed (TxQ = %d (internal %u), rc = %d)", ethdev_qid,
260 sfc_tx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
262 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
263 sfc_ethdev_qid_t ethdev_qid;
264 struct sfc_txq_info *txq_info;
267 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
269 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
271 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
272 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
273 sa->eth_dev->data->tx_queues[ethdev_qid] = NULL;
275 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
277 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
279 sa->priv.dp_tx->qdestroy(txq_info->dp);
282 txq_info->state &= ~SFC_TXQ_INITIALIZED;
283 txq_info->entries = 0;
285 txq = &sa->txq_ctrl[sw_index];
287 sfc_dma_free(sa, &txq->mem);
289 sfc_ev_qfini(txq->evq);
294 sfc_tx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
296 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
297 sfc_ethdev_qid_t ethdev_qid;
299 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
301 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
307 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
311 switch (txmode->mq_mode) {
315 sfc_err(sa, "Tx multi-queue mode %u not supported",
321 * These features are claimed to be i40e-specific,
322 * but it does make sense to double-check their absence
324 if (txmode->hw_vlan_reject_tagged) {
325 sfc_err(sa, "Rejecting tagged packets not supported");
329 if (txmode->hw_vlan_reject_untagged) {
330 sfc_err(sa, "Rejecting untagged packets not supported");
334 if (txmode->hw_vlan_insert_pvid) {
335 sfc_err(sa, "Port-based VLAN insertion not supported");
343 * Destroy excess queues that are no longer needed after reconfiguration
347 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues)
349 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
350 sfc_sw_index_t sw_index;
351 sfc_ethdev_qid_t ethdev_qid;
353 SFC_ASSERT(nb_tx_queues <= sas->ethdev_txq_count);
356 * Finalize only ethdev queues since other ones are finalized only
357 * on device close and they may require additional deinitializaton.
359 ethdev_qid = sas->ethdev_txq_count;
360 while (--ethdev_qid >= (int)nb_tx_queues) {
361 struct sfc_txq_info *txq_info;
363 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid);
364 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid);
365 if (txq_info->state & SFC_TXQ_INITIALIZED)
366 sfc_tx_qfini(sa, sw_index);
369 sas->ethdev_txq_count = nb_tx_queues;
373 sfc_tx_configure(struct sfc_adapter *sa)
375 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
376 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
377 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
378 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues;
381 sfc_log_init(sa, "nb_tx_queues=%u (old %u)",
382 nb_tx_queues, sas->ethdev_txq_count);
385 * The datapath implementation assumes absence of boundary
386 * limits on Tx DMA descriptors. Addition of these checks on
387 * datapath would simply make the datapath slower.
389 if (encp->enc_tx_dma_desc_boundary != 0) {
391 goto fail_tx_dma_desc_boundary;
394 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
396 goto fail_check_mode;
398 if (nb_tx_queues == sas->txq_count)
401 if (sas->txq_info == NULL) {
402 sas->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues,
403 sizeof(sas->txq_info[0]), 0,
405 if (sas->txq_info == NULL)
406 goto fail_txqs_alloc;
409 * Allocate primary process only TxQ control from heap
410 * since it should not be shared.
413 sa->txq_ctrl = calloc(nb_tx_queues, sizeof(sa->txq_ctrl[0]));
414 if (sa->txq_ctrl == NULL)
415 goto fail_txqs_ctrl_alloc;
417 struct sfc_txq_info *new_txq_info;
418 struct sfc_txq *new_txq_ctrl;
420 if (nb_tx_queues < sas->ethdev_txq_count)
421 sfc_tx_fini_queues(sa, nb_tx_queues);
424 rte_realloc(sas->txq_info,
425 nb_tx_queues * sizeof(sas->txq_info[0]), 0);
426 if (new_txq_info == NULL && nb_tx_queues > 0)
427 goto fail_txqs_realloc;
429 new_txq_ctrl = realloc(sa->txq_ctrl,
430 nb_tx_queues * sizeof(sa->txq_ctrl[0]));
431 if (new_txq_ctrl == NULL && nb_tx_queues > 0)
432 goto fail_txqs_ctrl_realloc;
434 sas->txq_info = new_txq_info;
435 sa->txq_ctrl = new_txq_ctrl;
436 if (nb_tx_queues > sas->ethdev_txq_count) {
437 memset(&sas->txq_info[sas->ethdev_txq_count], 0,
438 (nb_tx_queues - sas->ethdev_txq_count) *
439 sizeof(sas->txq_info[0]));
440 memset(&sa->txq_ctrl[sas->ethdev_txq_count], 0,
441 (nb_tx_queues - sas->ethdev_txq_count) *
442 sizeof(sa->txq_ctrl[0]));
446 while (sas->ethdev_txq_count < nb_tx_queues) {
447 sfc_sw_index_t sw_index;
449 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas,
450 sas->ethdev_txq_count);
451 rc = sfc_tx_qinit_info(sa, sw_index);
453 goto fail_tx_qinit_info;
455 sas->ethdev_txq_count++;
458 sas->txq_count = sas->ethdev_txq_count;
464 fail_txqs_ctrl_realloc:
466 fail_txqs_ctrl_alloc:
471 fail_tx_dma_desc_boundary:
472 sfc_log_init(sa, "failed (rc = %d)", rc);
477 sfc_tx_close(struct sfc_adapter *sa)
479 sfc_tx_fini_queues(sa, 0);
484 rte_free(sfc_sa2shared(sa)->txq_info);
485 sfc_sa2shared(sa)->txq_info = NULL;
489 sfc_tx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
491 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
492 sfc_ethdev_qid_t ethdev_qid;
493 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) |
494 sfc_tx_get_queue_offload_caps(sa);
495 struct sfc_txq_info *txq_info;
499 unsigned int desc_index;
502 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
504 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
506 SFC_ASSERT(sw_index < sas->txq_count);
507 txq_info = &sas->txq_info[sw_index];
509 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
511 txq = &sa->txq_ctrl[sw_index];
514 rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_txq_sw_index(sa, sw_index));
518 if (txq_info->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
519 flags |= EFX_TXQ_CKSUM_IPV4;
521 if (txq_info->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
522 flags |= EFX_TXQ_CKSUM_INNER_IPV4;
524 if ((txq_info->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
525 (txq_info->offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
526 flags |= EFX_TXQ_CKSUM_TCPUDP;
528 if (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
529 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP;
532 if (txq_info->offloads & (DEV_TX_OFFLOAD_TCP_TSO |
533 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
534 DEV_TX_OFFLOAD_GENEVE_TNL_TSO))
535 flags |= EFX_TXQ_FATSOV2;
537 rc = efx_tx_qcreate(sa->nic, txq->hw_index, 0, &txq->mem,
538 txq_info->entries, 0 /* not used on EF10 */,
540 &txq->common, &desc_index);
542 if (sa->tso && (rc == ENOSPC))
543 sfc_err(sa, "ran out of TSO contexts");
545 goto fail_tx_qcreate;
548 efx_tx_qenable(txq->common);
550 txq_info->state |= SFC_TXQ_STARTED;
552 rc = sa->priv.dp_tx->qstart(txq_info->dp, evq->read_ptr, desc_index);
556 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) {
557 struct rte_eth_dev_data *dev_data;
560 * It sems to be used by DPDK for debug purposes only
563 dev_data = sa->eth_dev->data;
564 dev_data->tx_queue_state[ethdev_qid] =
565 RTE_ETH_QUEUE_STATE_STARTED;
571 txq_info->state = SFC_TXQ_INITIALIZED;
572 efx_tx_qdestroy(txq->common);
582 sfc_tx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
584 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
585 sfc_ethdev_qid_t ethdev_qid;
586 struct sfc_txq_info *txq_info;
588 unsigned int retry_count;
589 unsigned int wait_count;
592 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
594 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
596 SFC_ASSERT(sw_index < sas->txq_count);
597 txq_info = &sas->txq_info[sw_index];
599 if (txq_info->state == SFC_TXQ_INITIALIZED)
602 SFC_ASSERT(txq_info->state & SFC_TXQ_STARTED);
604 txq = &sa->txq_ctrl[sw_index];
605 sa->priv.dp_tx->qstop(txq_info->dp, &txq->evq->read_ptr);
608 * Retry TX queue flushing in case of flush failed or
609 * timeout; in the worst case it can delay for 6 seconds
611 for (retry_count = 0;
612 ((txq_info->state & SFC_TXQ_FLUSHED) == 0) &&
613 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
615 rc = efx_tx_qflush(txq->common);
617 txq_info->state |= (rc == EALREADY) ?
618 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED;
623 * Wait for TX queue flush done or flush failed event at least
624 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
625 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
626 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
630 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
631 sfc_ev_qpoll(txq->evq);
632 } while ((txq_info->state & SFC_TXQ_FLUSHING) &&
633 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
635 if (txq_info->state & SFC_TXQ_FLUSHING)
636 sfc_err(sa, "TxQ %d (internal %u) flush timed out",
637 ethdev_qid, sw_index);
639 if (txq_info->state & SFC_TXQ_FLUSHED)
640 sfc_notice(sa, "TxQ %d (internal %u) flushed",
641 ethdev_qid, sw_index);
644 sa->priv.dp_tx->qreap(txq_info->dp);
646 txq_info->state = SFC_TXQ_INITIALIZED;
648 efx_tx_qdestroy(txq->common);
650 sfc_ev_qstop(txq->evq);
652 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) {
653 struct rte_eth_dev_data *dev_data;
656 * It seems to be used by DPDK for debug purposes only
659 dev_data = sa->eth_dev->data;
660 dev_data->tx_queue_state[ethdev_qid] =
661 RTE_ETH_QUEUE_STATE_STOPPED;
666 sfc_tx_start(struct sfc_adapter *sa)
668 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
669 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
670 sfc_sw_index_t sw_index;
673 sfc_log_init(sa, "txq_count = %u (internal %u)",
674 sas->ethdev_txq_count, sas->txq_count);
677 if (!encp->enc_fw_assisted_tso_v2_enabled &&
678 !encp->enc_tso_v3_enabled) {
679 sfc_warn(sa, "TSO support was unable to be restored");
681 sa->tso_encap = B_FALSE;
685 if (sa->tso_encap && !encp->enc_fw_assisted_tso_v2_encap_enabled &&
686 !encp->enc_tso_v3_enabled) {
687 sfc_warn(sa, "Encapsulated TSO support was unable to be restored");
688 sa->tso_encap = B_FALSE;
691 rc = efx_tx_init(sa->nic);
693 goto fail_efx_tx_init;
695 for (sw_index = 0; sw_index < sas->txq_count; ++sw_index) {
696 if (sas->txq_info[sw_index].state == SFC_TXQ_INITIALIZED &&
697 (!(sas->txq_info[sw_index].deferred_start) ||
698 sas->txq_info[sw_index].deferred_started)) {
699 rc = sfc_tx_qstart(sa, sw_index);
708 while (sw_index-- > 0)
709 sfc_tx_qstop(sa, sw_index);
711 efx_tx_fini(sa->nic);
714 sfc_log_init(sa, "failed (rc = %d)", rc);
719 sfc_tx_stop(struct sfc_adapter *sa)
721 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
722 sfc_sw_index_t sw_index;
724 sfc_log_init(sa, "txq_count = %u (internal %u)",
725 sas->ethdev_txq_count, sas->txq_count);
727 sw_index = sas->txq_count;
728 while (sw_index-- > 0) {
729 if (sas->txq_info[sw_index].state & SFC_TXQ_STARTED)
730 sfc_tx_qstop(sa, sw_index);
733 efx_tx_fini(sa->nic);
737 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
739 unsigned int completed;
741 sfc_ev_qpoll(txq->evq);
743 for (completed = txq->completed;
744 completed != txq->pending; completed++) {
745 struct sfc_efx_tx_sw_desc *txd;
747 txd = &txq->sw_ring[completed & txq->ptr_mask];
749 if (txd->mbuf != NULL) {
750 rte_pktmbuf_free(txd->mbuf);
755 txq->completed = completed;
759 * The function is used to insert or update VLAN tag;
760 * the firmware has state of the firmware tag to insert per TxQ
761 * (controlled by option descriptors), hence, if the tag of the
762 * packet to be sent is different from one remembered by the firmware,
763 * the function will update it
766 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
769 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
772 if (this_tag == txq->hw_vlan_tci)
776 * The expression inside SFC_ASSERT() is not desired to be checked in
777 * a non-debug build because it might be too expensive on the data path
779 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
781 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
784 txq->hw_vlan_tci = this_tag;
790 sfc_efx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
793 struct sfc_dp_txq *dp_txq = tx_queue;
794 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
795 const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->evq->sa->nic);
798 for (i = 0; i < nb_pkts; i++) {
802 * EFX Tx datapath may require extra VLAN descriptor if VLAN
803 * insertion offload is requested regardless the offload
804 * requested/supported.
806 ret = sfc_dp_tx_prepare_pkt(tx_pkts[i], 0, SFC_TSOH_STD_LEN,
807 encp->enc_tx_tso_tcp_header_offset_limit,
808 txq->max_fill_level, EFX_TX_FATSOV2_OPT_NDESCS,
810 if (unlikely(ret != 0)) {
820 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
822 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
823 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
824 unsigned int added = txq->added;
825 unsigned int pushed = added;
826 unsigned int pkts_sent = 0;
827 efx_desc_t *pend = &txq->pend_desc[0];
828 const unsigned int hard_max_fill = txq->max_fill_level;
829 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
830 unsigned int fill_level = added - txq->completed;
833 struct rte_mbuf **pktp;
835 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
839 * If insufficient space for a single packet is present,
840 * we should reap; otherwise, we shouldn't do that all the time
841 * to avoid latency increase
843 reap_done = (fill_level > soft_max_fill);
846 sfc_efx_tx_reap(txq);
848 * Recalculate fill level since 'txq->completed'
849 * might have changed on reap
851 fill_level = added - txq->completed;
854 for (pkts_sent = 0, pktp = &tx_pkts[0];
855 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
856 pkts_sent++, pktp++) {
857 uint16_t hw_vlan_tci_prev = txq->hw_vlan_tci;
858 struct rte_mbuf *m_seg = *pktp;
859 size_t pkt_len = m_seg->pkt_len;
860 unsigned int pkt_descs = 0;
864 * Here VLAN TCI is expected to be zero in case if no
865 * DEV_TX_OFFLOAD_VLAN_INSERT capability is advertised;
866 * if the calling app ignores the absence of
867 * DEV_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then
868 * TX_ERROR will occur
870 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
872 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
874 * We expect correct 'pkt->l[2, 3, 4]_len' values
875 * to be set correctly by the caller
877 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
878 &pkt_descs, &pkt_len) != 0) {
879 /* We may have reached this place if packet
880 * header linearization is needed but the
881 * header length is greater than
884 * We will deceive RTE saying that we have sent
885 * the packet, but we will actually drop it.
886 * Hence, we should revert 'pend' to the
887 * previous state (in case we have added
888 * VLAN descriptor) and start processing
889 * another one packet. But the original
890 * mbuf shouldn't be orphaned
893 txq->hw_vlan_tci = hw_vlan_tci_prev;
895 rte_pktmbuf_free(*pktp);
901 * We've only added 2 FATSOv2 option descriptors
902 * and 1 descriptor for the linearized packet header.
903 * The outstanding work will be done in the same manner
904 * as for the usual non-TSO path
908 for (; m_seg != NULL; m_seg = m_seg->next) {
909 efsys_dma_addr_t next_frag;
912 seg_len = m_seg->data_len;
913 next_frag = rte_mbuf_data_iova(m_seg);
916 * If we've started TSO transaction few steps earlier,
917 * we'll skip packet header using an offset in the
918 * current segment (which has been set to the
919 * first one containing payload)
926 efsys_dma_addr_t frag_addr = next_frag;
930 * It is assumed here that there is no
931 * limitation on address boundary
932 * crossing by DMA descriptor.
934 frag_len = MIN(seg_len, txq->dma_desc_size_max);
935 next_frag += frag_len;
939 efx_tx_qdesc_dma_create(txq->common,
945 } while (seg_len != 0);
950 fill_level += pkt_descs;
951 if (unlikely(fill_level > hard_max_fill)) {
953 * Our estimation for maximum number of descriptors
954 * required to send a packet seems to be wrong.
955 * Try to reap (if we haven't yet).
958 sfc_efx_tx_reap(txq);
960 fill_level = added - txq->completed;
961 if (fill_level > hard_max_fill) {
963 txq->hw_vlan_tci = hw_vlan_tci_prev;
968 txq->hw_vlan_tci = hw_vlan_tci_prev;
973 /* Assign mbuf to the last used desc */
974 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
977 if (likely(pkts_sent > 0)) {
978 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
979 pend - &txq->pend_desc[0],
980 txq->completed, &txq->added);
983 if (likely(pushed != txq->added)) {
984 efx_tx_qpush(txq->common, txq->added, pushed);
985 txq->dp.dpq.tx_dbells++;
989 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
991 sfc_efx_tx_reap(txq);
998 const struct sfc_dp_tx *
999 sfc_dp_tx_by_dp_txq(const struct sfc_dp_txq *dp_txq)
1001 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
1002 struct rte_eth_dev *eth_dev;
1003 struct sfc_adapter_priv *sap;
1005 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
1006 eth_dev = &rte_eth_devices[dpq->port_id];
1008 sap = sfc_adapter_priv_by_eth_dev(eth_dev);
1013 struct sfc_txq_info *
1014 sfc_txq_info_by_dp_txq(const struct sfc_dp_txq *dp_txq)
1016 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
1017 struct rte_eth_dev *eth_dev;
1018 struct sfc_adapter_shared *sas;
1020 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
1021 eth_dev = &rte_eth_devices[dpq->port_id];
1023 sas = sfc_adapter_shared_by_eth_dev(eth_dev);
1025 SFC_ASSERT(dpq->queue_id < sas->txq_count);
1026 return &sas->txq_info[dpq->queue_id];
1030 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
1032 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
1033 struct rte_eth_dev *eth_dev;
1034 struct sfc_adapter *sa;
1036 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
1037 eth_dev = &rte_eth_devices[dpq->port_id];
1039 sa = sfc_adapter_by_eth_dev(eth_dev);
1041 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->txq_count);
1042 return &sa->txq_ctrl[dpq->queue_id];
1045 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings;
1047 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc,
1048 __rte_unused struct sfc_dp_tx_hw_limits *limits,
1049 unsigned int *txq_entries,
1050 unsigned int *evq_entries,
1051 unsigned int *txq_max_fill_level)
1053 *txq_entries = nb_tx_desc;
1054 *evq_entries = nb_tx_desc;
1055 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries);
1059 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
1061 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
1062 const struct rte_pci_addr *pci_addr,
1064 const struct sfc_dp_tx_qcreate_info *info,
1065 struct sfc_dp_txq **dp_txqp)
1067 struct sfc_efx_txq *txq;
1068 struct sfc_txq *ctrl_txq;
1072 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
1073 RTE_CACHE_LINE_SIZE, socket_id);
1075 goto fail_txq_alloc;
1077 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
1080 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
1081 EFX_TXQ_LIMIT(info->txq_entries),
1082 sizeof(*txq->pend_desc), 0,
1084 if (txq->pend_desc == NULL)
1085 goto fail_pend_desc_alloc;
1088 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
1090 sizeof(*txq->sw_ring),
1091 RTE_CACHE_LINE_SIZE, socket_id);
1092 if (txq->sw_ring == NULL)
1093 goto fail_sw_ring_alloc;
1095 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
1096 if (ctrl_txq->evq->sa->tso) {
1097 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
1098 info->txq_entries, socket_id);
1100 goto fail_alloc_tsoh_objs;
1103 txq->evq = ctrl_txq->evq;
1104 txq->ptr_mask = info->txq_entries - 1;
1105 txq->max_fill_level = info->max_fill_level;
1106 txq->free_thresh = info->free_thresh;
1107 txq->dma_desc_size_max = info->dma_desc_size_max;
1109 *dp_txqp = &txq->dp;
1112 fail_alloc_tsoh_objs:
1113 rte_free(txq->sw_ring);
1116 rte_free(txq->pend_desc);
1118 fail_pend_desc_alloc:
1125 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
1127 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
1129 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1131 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
1132 rte_free(txq->sw_ring);
1133 rte_free(txq->pend_desc);
1137 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
1139 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
1140 __rte_unused unsigned int evq_read_ptr,
1141 unsigned int txq_desc_index)
1143 /* libefx-based datapath is specific to libefx-based PMD */
1144 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1145 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
1147 txq->common = ctrl_txq->common;
1149 txq->pending = txq->completed = txq->added = txq_desc_index;
1150 txq->hw_vlan_tci = 0;
1152 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
1157 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
1159 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
1160 __rte_unused unsigned int *evq_read_ptr)
1162 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1164 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
1167 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
1169 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
1171 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1174 sfc_efx_tx_reap(txq);
1176 for (txds = 0; txds <= txq->ptr_mask; txds++) {
1177 if (txq->sw_ring[txds].mbuf != NULL) {
1178 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
1179 txq->sw_ring[txds].mbuf = NULL;
1183 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
1186 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status;
1188 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
1190 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1192 if (unlikely(offset > txq->ptr_mask))
1195 if (unlikely(offset >= txq->max_fill_level))
1196 return RTE_ETH_TX_DESC_UNAVAIL;
1199 * Poll EvQ to derive up-to-date 'txq->pending' figure;
1200 * it is required for the queue to be running, but the
1201 * check is omitted because API design assumes that it
1202 * is the duty of the caller to satisfy all conditions
1204 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) ==
1205 SFC_EFX_TXQ_FLAG_RUNNING);
1206 sfc_ev_qpoll(txq->evq);
1209 * Ring tail is 'txq->pending', and although descriptors
1210 * between 'txq->completed' and 'txq->pending' are still
1211 * in use by the driver, they should be reported as DONE
1213 if (unlikely(offset < (txq->added - txq->pending)))
1214 return RTE_ETH_TX_DESC_FULL;
1217 * There is no separate return value for unused descriptors;
1218 * the latter will be reported as DONE because genuine DONE
1219 * descriptors will be freed anyway in SW on the next burst
1221 return RTE_ETH_TX_DESC_DONE;
1224 struct sfc_dp_tx sfc_efx_tx = {
1226 .name = SFC_KVARG_DATAPATH_EFX,
1228 .hw_fw_caps = SFC_DP_HW_FW_CAP_TX_EFX,
1231 .dev_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1232 DEV_TX_OFFLOAD_MULTI_SEGS,
1233 .queue_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1234 DEV_TX_OFFLOAD_UDP_CKSUM |
1235 DEV_TX_OFFLOAD_TCP_CKSUM |
1236 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1237 DEV_TX_OFFLOAD_TCP_TSO,
1238 .qsize_up_rings = sfc_efx_tx_qsize_up_rings,
1239 .qcreate = sfc_efx_tx_qcreate,
1240 .qdestroy = sfc_efx_tx_qdestroy,
1241 .qstart = sfc_efx_tx_qstart,
1242 .qstop = sfc_efx_tx_qstop,
1243 .qreap = sfc_efx_tx_qreap,
1244 .qdesc_status = sfc_efx_tx_qdesc_status,
1245 .pkt_prepare = sfc_efx_prepare_pkts,
1246 .pkt_burst = sfc_efx_xmit_pkts,