1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
11 #include "sfc_debug.h"
15 #include "sfc_tweak.h"
16 #include "sfc_kvargs.h"
19 * Maximum number of TX queue flush attempts in case of
20 * failure or flush timeout
22 #define SFC_TX_QFLUSH_ATTEMPTS (3)
25 * Time to wait between event queue polling attempts when waiting for TX
26 * queue flush done or flush failed events
28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
31 * Maximum number of event queue polling attempts when waiting for TX queue
32 * flush done or flush failed events; it defines TX queue flush attempt timeout
33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
38 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa)
40 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
43 if ((sa->priv.dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) &&
44 encp->enc_hw_tx_insert_vlan_enabled)
45 caps |= DEV_TX_OFFLOAD_VLAN_INSERT;
47 if (sa->priv.dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG)
48 caps |= DEV_TX_OFFLOAD_MULTI_SEGS;
50 if ((~sa->priv.dp_tx->features & SFC_DP_TX_FEAT_MULTI_POOL) &&
51 (~sa->priv.dp_tx->features & SFC_DP_TX_FEAT_REFCNT))
52 caps |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
58 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa)
60 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
63 caps |= DEV_TX_OFFLOAD_IPV4_CKSUM;
64 caps |= DEV_TX_OFFLOAD_UDP_CKSUM;
65 caps |= DEV_TX_OFFLOAD_TCP_CKSUM;
67 if (encp->enc_tunnel_encapsulations_supported)
68 caps |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
71 caps |= DEV_TX_OFFLOAD_TCP_TSO;
77 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level,
78 const struct rte_eth_txconf *tx_conf,
83 if (tx_conf->tx_rs_thresh != 0) {
84 sfc_err(sa, "RS bit in transmit descriptor is not supported");
88 if (tx_conf->tx_free_thresh > txq_max_fill_level) {
90 "TxQ free threshold too large: %u vs maximum %u",
91 tx_conf->tx_free_thresh, txq_max_fill_level);
95 if (tx_conf->tx_thresh.pthresh != 0 ||
96 tx_conf->tx_thresh.hthresh != 0 ||
97 tx_conf->tx_thresh.wthresh != 0) {
99 "prefetch/host/writeback thresholds are not supported");
102 /* We either perform both TCP and UDP offload, or no offload at all */
103 if (((offloads & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) !=
104 ((offloads & DEV_TX_OFFLOAD_UDP_CKSUM) == 0)) {
105 sfc_err(sa, "TCP and UDP offloads can't be set independently");
113 sfc_tx_qflush_done(struct sfc_txq_info *txq_info)
115 txq_info->state |= SFC_TXQ_FLUSHED;
116 txq_info->state &= ~SFC_TXQ_FLUSHING;
120 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
121 uint16_t nb_tx_desc, unsigned int socket_id,
122 const struct rte_eth_txconf *tx_conf)
124 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
125 unsigned int txq_entries;
126 unsigned int evq_entries;
127 unsigned int txq_max_fill_level;
128 struct sfc_txq_info *txq_info;
132 struct sfc_dp_tx_qcreate_info info;
135 sfc_log_init(sa, "TxQ = %u", sw_index);
137 rc = sa->priv.dp_tx->qsize_up_rings(nb_tx_desc, &txq_entries,
138 &evq_entries, &txq_max_fill_level);
140 goto fail_size_up_rings;
141 SFC_ASSERT(txq_entries >= EFX_TXQ_MINNDESCS);
142 SFC_ASSERT(txq_entries <= sa->txq_max_entries);
143 SFC_ASSERT(txq_entries >= nb_tx_desc);
144 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc);
146 offloads = tx_conf->offloads |
147 sa->eth_dev->data->dev_conf.txmode.offloads;
148 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf, offloads);
152 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
153 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
155 txq_info->entries = txq_entries;
157 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
158 evq_entries, socket_id, &evq);
162 txq = &sa->txq_ctrl[sw_index];
163 txq->hw_index = sw_index;
165 txq_info->free_thresh =
166 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
167 SFC_TX_DEFAULT_FREE_THRESH;
168 txq_info->offloads = offloads;
170 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
171 socket_id, &txq->mem);
175 memset(&info, 0, sizeof(info));
176 info.max_fill_level = txq_max_fill_level;
177 info.free_thresh = txq_info->free_thresh;
178 info.offloads = offloads;
179 info.txq_entries = txq_info->entries;
180 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
181 info.txq_hw_ring = txq->mem.esm_base;
182 info.evq_entries = evq_entries;
183 info.evq_hw_ring = evq->mem.esm_base;
184 info.hw_index = txq->hw_index;
185 info.mem_bar = sa->mem_bar.esb_base;
186 info.vi_window_shift = encp->enc_vi_window_shift;
187 info.tso_tcp_header_offset_limit =
188 encp->enc_tx_tso_tcp_header_offset_limit;
190 rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
191 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
192 socket_id, &info, &txq_info->dp);
194 goto fail_dp_tx_qinit;
196 evq->dp_txq = txq_info->dp;
198 txq_info->state = SFC_TXQ_INITIALIZED;
200 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
205 sfc_dma_free(sa, &txq->mem);
211 txq_info->entries = 0;
215 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
220 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
222 struct sfc_txq_info *txq_info;
225 sfc_log_init(sa, "TxQ = %u", sw_index);
227 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
228 sa->eth_dev->data->tx_queues[sw_index] = NULL;
230 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
232 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
234 sa->priv.dp_tx->qdestroy(txq_info->dp);
237 txq_info->state &= ~SFC_TXQ_INITIALIZED;
238 txq_info->entries = 0;
240 txq = &sa->txq_ctrl[sw_index];
242 sfc_dma_free(sa, &txq->mem);
244 sfc_ev_qfini(txq->evq);
249 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
251 sfc_log_init(sa, "TxQ = %u", sw_index);
257 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
261 switch (txmode->mq_mode) {
265 sfc_err(sa, "Tx multi-queue mode %u not supported",
271 * These features are claimed to be i40e-specific,
272 * but it does make sense to double-check their absence
274 if (txmode->hw_vlan_reject_tagged) {
275 sfc_err(sa, "Rejecting tagged packets not supported");
279 if (txmode->hw_vlan_reject_untagged) {
280 sfc_err(sa, "Rejecting untagged packets not supported");
284 if (txmode->hw_vlan_insert_pvid) {
285 sfc_err(sa, "Port-based VLAN insertion not supported");
293 * Destroy excess queues that are no longer needed after reconfiguration
297 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues)
299 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
302 SFC_ASSERT(nb_tx_queues <= sas->txq_count);
304 sw_index = sas->txq_count;
305 while (--sw_index >= (int)nb_tx_queues) {
306 if (sas->txq_info[sw_index].state & SFC_TXQ_INITIALIZED)
307 sfc_tx_qfini(sa, sw_index);
310 sas->txq_count = nb_tx_queues;
314 sfc_tx_configure(struct sfc_adapter *sa)
316 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
317 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
318 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
319 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues;
322 sfc_log_init(sa, "nb_tx_queues=%u (old %u)",
323 nb_tx_queues, sas->txq_count);
326 * The datapath implementation assumes absence of boundary
327 * limits on Tx DMA descriptors. Addition of these checks on
328 * datapath would simply make the datapath slower.
330 if (encp->enc_tx_dma_desc_boundary != 0) {
332 goto fail_tx_dma_desc_boundary;
335 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
337 goto fail_check_mode;
339 if (nb_tx_queues == sas->txq_count)
342 if (sas->txq_info == NULL) {
343 sas->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues,
344 sizeof(sas->txq_info[0]), 0,
346 if (sas->txq_info == NULL)
347 goto fail_txqs_alloc;
350 * Allocate primary process only TxQ control from heap
351 * since it should not be shared.
354 sa->txq_ctrl = calloc(nb_tx_queues, sizeof(sa->txq_ctrl[0]));
355 if (sa->txq_ctrl == NULL)
356 goto fail_txqs_ctrl_alloc;
358 struct sfc_txq_info *new_txq_info;
359 struct sfc_txq *new_txq_ctrl;
361 if (nb_tx_queues < sas->txq_count)
362 sfc_tx_fini_queues(sa, nb_tx_queues);
365 rte_realloc(sas->txq_info,
366 nb_tx_queues * sizeof(sas->txq_info[0]), 0);
367 if (new_txq_info == NULL && nb_tx_queues > 0)
368 goto fail_txqs_realloc;
370 new_txq_ctrl = realloc(sa->txq_ctrl,
371 nb_tx_queues * sizeof(sa->txq_ctrl[0]));
372 if (new_txq_ctrl == NULL && nb_tx_queues > 0)
373 goto fail_txqs_ctrl_realloc;
375 sas->txq_info = new_txq_info;
376 sa->txq_ctrl = new_txq_ctrl;
377 if (nb_tx_queues > sas->txq_count) {
378 memset(&sas->txq_info[sas->txq_count], 0,
379 (nb_tx_queues - sas->txq_count) *
380 sizeof(sas->txq_info[0]));
381 memset(&sa->txq_ctrl[sas->txq_count], 0,
382 (nb_tx_queues - sas->txq_count) *
383 sizeof(sa->txq_ctrl[0]));
387 while (sas->txq_count < nb_tx_queues) {
388 rc = sfc_tx_qinit_info(sa, sas->txq_count);
390 goto fail_tx_qinit_info;
399 fail_txqs_ctrl_realloc:
401 fail_txqs_ctrl_alloc:
406 fail_tx_dma_desc_boundary:
407 sfc_log_init(sa, "failed (rc = %d)", rc);
412 sfc_tx_close(struct sfc_adapter *sa)
414 sfc_tx_fini_queues(sa, 0);
419 rte_free(sfc_sa2shared(sa)->txq_info);
420 sfc_sa2shared(sa)->txq_info = NULL;
424 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
426 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
427 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) |
428 sfc_tx_get_queue_offload_caps(sa);
429 struct rte_eth_dev_data *dev_data;
430 struct sfc_txq_info *txq_info;
434 unsigned int desc_index;
437 sfc_log_init(sa, "TxQ = %u", sw_index);
439 SFC_ASSERT(sw_index < sas->txq_count);
440 txq_info = &sas->txq_info[sw_index];
442 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
444 txq = &sa->txq_ctrl[sw_index];
447 rc = sfc_ev_qstart(evq, sfc_evq_index_by_txq_sw_index(sa, sw_index));
451 if (txq_info->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
452 flags |= EFX_TXQ_CKSUM_IPV4;
454 if (txq_info->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
455 flags |= EFX_TXQ_CKSUM_INNER_IPV4;
457 if ((txq_info->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
458 (txq_info->offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
459 flags |= EFX_TXQ_CKSUM_TCPUDP;
461 if (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
462 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP;
465 if (txq_info->offloads & DEV_TX_OFFLOAD_TCP_TSO)
466 flags |= EFX_TXQ_FATSOV2;
468 rc = efx_tx_qcreate(sa->nic, txq->hw_index, 0, &txq->mem,
469 txq_info->entries, 0 /* not used on EF10 */,
471 &txq->common, &desc_index);
473 if (sa->tso && (rc == ENOSPC))
474 sfc_err(sa, "ran out of TSO contexts");
476 goto fail_tx_qcreate;
479 efx_tx_qenable(txq->common);
481 txq_info->state |= SFC_TXQ_STARTED;
483 rc = sa->priv.dp_tx->qstart(txq_info->dp, evq->read_ptr, desc_index);
488 * It seems to be used by DPDK for debug purposes only ('rte_ether')
490 dev_data = sa->eth_dev->data;
491 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
496 txq_info->state = SFC_TXQ_INITIALIZED;
497 efx_tx_qdestroy(txq->common);
507 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
509 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
510 struct rte_eth_dev_data *dev_data;
511 struct sfc_txq_info *txq_info;
513 unsigned int retry_count;
514 unsigned int wait_count;
517 sfc_log_init(sa, "TxQ = %u", sw_index);
519 SFC_ASSERT(sw_index < sas->txq_count);
520 txq_info = &sas->txq_info[sw_index];
522 if (txq_info->state == SFC_TXQ_INITIALIZED)
525 SFC_ASSERT(txq_info->state & SFC_TXQ_STARTED);
527 txq = &sa->txq_ctrl[sw_index];
528 sa->priv.dp_tx->qstop(txq_info->dp, &txq->evq->read_ptr);
531 * Retry TX queue flushing in case of flush failed or
532 * timeout; in the worst case it can delay for 6 seconds
534 for (retry_count = 0;
535 ((txq_info->state & SFC_TXQ_FLUSHED) == 0) &&
536 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
538 rc = efx_tx_qflush(txq->common);
540 txq_info->state |= (rc == EALREADY) ?
541 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED;
546 * Wait for TX queue flush done or flush failed event at least
547 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
548 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
549 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
553 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
554 sfc_ev_qpoll(txq->evq);
555 } while ((txq_info->state & SFC_TXQ_FLUSHING) &&
556 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
558 if (txq_info->state & SFC_TXQ_FLUSHING)
559 sfc_err(sa, "TxQ %u flush timed out", sw_index);
561 if (txq_info->state & SFC_TXQ_FLUSHED)
562 sfc_notice(sa, "TxQ %u flushed", sw_index);
565 sa->priv.dp_tx->qreap(txq_info->dp);
567 txq_info->state = SFC_TXQ_INITIALIZED;
569 efx_tx_qdestroy(txq->common);
571 sfc_ev_qstop(txq->evq);
574 * It seems to be used by DPDK for debug purposes only ('rte_ether')
576 dev_data = sa->eth_dev->data;
577 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
581 sfc_tx_start(struct sfc_adapter *sa)
583 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
584 unsigned int sw_index;
587 sfc_log_init(sa, "txq_count = %u", sas->txq_count);
590 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
591 sfc_warn(sa, "TSO support was unable to be restored");
596 rc = efx_tx_init(sa->nic);
598 goto fail_efx_tx_init;
600 for (sw_index = 0; sw_index < sas->txq_count; ++sw_index) {
601 if (sas->txq_info[sw_index].state == SFC_TXQ_INITIALIZED &&
602 (!(sas->txq_info[sw_index].deferred_start) ||
603 sas->txq_info[sw_index].deferred_started)) {
604 rc = sfc_tx_qstart(sa, sw_index);
613 while (sw_index-- > 0)
614 sfc_tx_qstop(sa, sw_index);
616 efx_tx_fini(sa->nic);
619 sfc_log_init(sa, "failed (rc = %d)", rc);
624 sfc_tx_stop(struct sfc_adapter *sa)
626 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
627 unsigned int sw_index;
629 sfc_log_init(sa, "txq_count = %u", sas->txq_count);
631 sw_index = sas->txq_count;
632 while (sw_index-- > 0) {
633 if (sas->txq_info[sw_index].state & SFC_TXQ_STARTED)
634 sfc_tx_qstop(sa, sw_index);
637 efx_tx_fini(sa->nic);
641 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
643 unsigned int completed;
645 sfc_ev_qpoll(txq->evq);
647 for (completed = txq->completed;
648 completed != txq->pending; completed++) {
649 struct sfc_efx_tx_sw_desc *txd;
651 txd = &txq->sw_ring[completed & txq->ptr_mask];
653 if (txd->mbuf != NULL) {
654 rte_pktmbuf_free(txd->mbuf);
659 txq->completed = completed;
663 * The function is used to insert or update VLAN tag;
664 * the firmware has state of the firmware tag to insert per TxQ
665 * (controlled by option descriptors), hence, if the tag of the
666 * packet to be sent is different from one remembered by the firmware,
667 * the function will update it
670 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
673 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
676 if (this_tag == txq->hw_vlan_tci)
680 * The expression inside SFC_ASSERT() is not desired to be checked in
681 * a non-debug build because it might be too expensive on the data path
683 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
685 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
688 txq->hw_vlan_tci = this_tag;
694 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
696 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
697 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
698 unsigned int added = txq->added;
699 unsigned int pushed = added;
700 unsigned int pkts_sent = 0;
701 efx_desc_t *pend = &txq->pend_desc[0];
702 const unsigned int hard_max_fill = txq->max_fill_level;
703 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
704 unsigned int fill_level = added - txq->completed;
707 struct rte_mbuf **pktp;
709 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
713 * If insufficient space for a single packet is present,
714 * we should reap; otherwise, we shouldn't do that all the time
715 * to avoid latency increase
717 reap_done = (fill_level > soft_max_fill);
720 sfc_efx_tx_reap(txq);
722 * Recalculate fill level since 'txq->completed'
723 * might have changed on reap
725 fill_level = added - txq->completed;
728 for (pkts_sent = 0, pktp = &tx_pkts[0];
729 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
730 pkts_sent++, pktp++) {
731 uint16_t hw_vlan_tci_prev = txq->hw_vlan_tci;
732 struct rte_mbuf *m_seg = *pktp;
733 size_t pkt_len = m_seg->pkt_len;
734 unsigned int pkt_descs = 0;
738 * Here VLAN TCI is expected to be zero in case if no
739 * DEV_TX_OFFLOAD_VLAN_INSERT capability is advertised;
740 * if the calling app ignores the absence of
741 * DEV_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then
742 * TX_ERROR will occur
744 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
746 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
748 * We expect correct 'pkt->l[2, 3, 4]_len' values
749 * to be set correctly by the caller
751 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
752 &pkt_descs, &pkt_len) != 0) {
753 /* We may have reached this place for
754 * one of the following reasons:
756 * 1) Packet header length is greater
757 * than SFC_TSOH_STD_LEN
758 * 2) TCP header starts at more then
759 * 208 bytes into the frame
761 * We will deceive RTE saying that we have sent
762 * the packet, but we will actually drop it.
763 * Hence, we should revert 'pend' to the
764 * previous state (in case we have added
765 * VLAN descriptor) and start processing
766 * another one packet. But the original
767 * mbuf shouldn't be orphaned
770 txq->hw_vlan_tci = hw_vlan_tci_prev;
772 rte_pktmbuf_free(*pktp);
778 * We've only added 2 FATSOv2 option descriptors
779 * and 1 descriptor for the linearized packet header.
780 * The outstanding work will be done in the same manner
781 * as for the usual non-TSO path
785 for (; m_seg != NULL; m_seg = m_seg->next) {
786 efsys_dma_addr_t next_frag;
789 seg_len = m_seg->data_len;
790 next_frag = rte_mbuf_data_iova(m_seg);
793 * If we've started TSO transaction few steps earlier,
794 * we'll skip packet header using an offset in the
795 * current segment (which has been set to the
796 * first one containing payload)
803 efsys_dma_addr_t frag_addr = next_frag;
807 * It is assumed here that there is no
808 * limitation on address boundary
809 * crossing by DMA descriptor.
811 frag_len = MIN(seg_len, txq->dma_desc_size_max);
812 next_frag += frag_len;
816 efx_tx_qdesc_dma_create(txq->common,
822 } while (seg_len != 0);
827 fill_level += pkt_descs;
828 if (unlikely(fill_level > hard_max_fill)) {
830 * Our estimation for maximum number of descriptors
831 * required to send a packet seems to be wrong.
832 * Try to reap (if we haven't yet).
835 sfc_efx_tx_reap(txq);
837 fill_level = added - txq->completed;
838 if (fill_level > hard_max_fill) {
840 txq->hw_vlan_tci = hw_vlan_tci_prev;
845 txq->hw_vlan_tci = hw_vlan_tci_prev;
850 /* Assign mbuf to the last used desc */
851 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
854 if (likely(pkts_sent > 0)) {
855 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
856 pend - &txq->pend_desc[0],
857 txq->completed, &txq->added);
860 if (likely(pushed != txq->added))
861 efx_tx_qpush(txq->common, txq->added, pushed);
864 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
866 sfc_efx_tx_reap(txq);
873 const struct sfc_dp_tx *
874 sfc_dp_tx_by_dp_txq(const struct sfc_dp_txq *dp_txq)
876 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
877 struct rte_eth_dev *eth_dev;
878 struct sfc_adapter_priv *sap;
880 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
881 eth_dev = &rte_eth_devices[dpq->port_id];
883 sap = sfc_adapter_priv_by_eth_dev(eth_dev);
888 struct sfc_txq_info *
889 sfc_txq_info_by_dp_txq(const struct sfc_dp_txq *dp_txq)
891 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
892 struct rte_eth_dev *eth_dev;
893 struct sfc_adapter_shared *sas;
895 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
896 eth_dev = &rte_eth_devices[dpq->port_id];
898 sas = sfc_adapter_shared_by_eth_dev(eth_dev);
900 SFC_ASSERT(dpq->queue_id < sas->txq_count);
901 return &sas->txq_info[dpq->queue_id];
905 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
907 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
908 struct rte_eth_dev *eth_dev;
909 struct sfc_adapter *sa;
911 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
912 eth_dev = &rte_eth_devices[dpq->port_id];
914 sa = eth_dev->data->dev_private;
916 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->txq_count);
917 return &sa->txq_ctrl[dpq->queue_id];
920 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings;
922 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc,
923 unsigned int *txq_entries,
924 unsigned int *evq_entries,
925 unsigned int *txq_max_fill_level)
927 *txq_entries = nb_tx_desc;
928 *evq_entries = nb_tx_desc;
929 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries);
933 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
935 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
936 const struct rte_pci_addr *pci_addr,
938 const struct sfc_dp_tx_qcreate_info *info,
939 struct sfc_dp_txq **dp_txqp)
941 struct sfc_efx_txq *txq;
942 struct sfc_txq *ctrl_txq;
946 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
947 RTE_CACHE_LINE_SIZE, socket_id);
951 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
954 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
955 EFX_TXQ_LIMIT(info->txq_entries),
956 sizeof(*txq->pend_desc), 0,
958 if (txq->pend_desc == NULL)
959 goto fail_pend_desc_alloc;
962 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
964 sizeof(*txq->sw_ring),
965 RTE_CACHE_LINE_SIZE, socket_id);
966 if (txq->sw_ring == NULL)
967 goto fail_sw_ring_alloc;
969 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
970 if (ctrl_txq->evq->sa->tso) {
971 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
972 info->txq_entries, socket_id);
974 goto fail_alloc_tsoh_objs;
977 txq->evq = ctrl_txq->evq;
978 txq->ptr_mask = info->txq_entries - 1;
979 txq->max_fill_level = info->max_fill_level;
980 txq->free_thresh = info->free_thresh;
981 txq->dma_desc_size_max = info->dma_desc_size_max;
986 fail_alloc_tsoh_objs:
987 rte_free(txq->sw_ring);
990 rte_free(txq->pend_desc);
992 fail_pend_desc_alloc:
999 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
1001 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
1003 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1005 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
1006 rte_free(txq->sw_ring);
1007 rte_free(txq->pend_desc);
1011 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
1013 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
1014 __rte_unused unsigned int evq_read_ptr,
1015 unsigned int txq_desc_index)
1017 /* libefx-based datapath is specific to libefx-based PMD */
1018 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1019 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
1021 txq->common = ctrl_txq->common;
1023 txq->pending = txq->completed = txq->added = txq_desc_index;
1024 txq->hw_vlan_tci = 0;
1026 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
1031 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
1033 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
1034 __rte_unused unsigned int *evq_read_ptr)
1036 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1038 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
1041 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
1043 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
1045 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1048 sfc_efx_tx_reap(txq);
1050 for (txds = 0; txds <= txq->ptr_mask; txds++) {
1051 if (txq->sw_ring[txds].mbuf != NULL) {
1052 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
1053 txq->sw_ring[txds].mbuf = NULL;
1057 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
1060 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status;
1062 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
1064 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1066 if (unlikely(offset > txq->ptr_mask))
1069 if (unlikely(offset >= txq->max_fill_level))
1070 return RTE_ETH_TX_DESC_UNAVAIL;
1073 * Poll EvQ to derive up-to-date 'txq->pending' figure;
1074 * it is required for the queue to be running, but the
1075 * check is omitted because API design assumes that it
1076 * is the duty of the caller to satisfy all conditions
1078 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) ==
1079 SFC_EFX_TXQ_FLAG_RUNNING);
1080 sfc_ev_qpoll(txq->evq);
1083 * Ring tail is 'txq->pending', and although descriptors
1084 * between 'txq->completed' and 'txq->pending' are still
1085 * in use by the driver, they should be reported as DONE
1087 if (unlikely(offset < (txq->added - txq->pending)))
1088 return RTE_ETH_TX_DESC_FULL;
1091 * There is no separate return value for unused descriptors;
1092 * the latter will be reported as DONE because genuine DONE
1093 * descriptors will be freed anyway in SW on the next burst
1095 return RTE_ETH_TX_DESC_DONE;
1098 struct sfc_dp_tx sfc_efx_tx = {
1100 .name = SFC_KVARG_DATAPATH_EFX,
1104 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
1105 SFC_DP_TX_FEAT_TSO |
1106 SFC_DP_TX_FEAT_MULTI_POOL |
1107 SFC_DP_TX_FEAT_REFCNT |
1108 SFC_DP_TX_FEAT_MULTI_SEG,
1109 .qsize_up_rings = sfc_efx_tx_qsize_up_rings,
1110 .qcreate = sfc_efx_tx_qcreate,
1111 .qdestroy = sfc_efx_tx_qdestroy,
1112 .qstart = sfc_efx_tx_qstart,
1113 .qstop = sfc_efx_tx_qstop,
1114 .qreap = sfc_efx_tx_qreap,
1115 .qdesc_status = sfc_efx_tx_qdesc_status,
1116 .pkt_burst = sfc_efx_xmit_pkts,