1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2018 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
11 #include "sfc_debug.h"
15 #include "sfc_tweak.h"
16 #include "sfc_kvargs.h"
19 * Maximum number of TX queue flush attempts in case of
20 * failure or flush timeout
22 #define SFC_TX_QFLUSH_ATTEMPTS (3)
25 * Time to wait between event queue polling attempts when waiting for TX
26 * queue flush done or flush failed events
28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
31 * Maximum number of event queue polling attempts when waiting for TX queue
32 * flush done or flush failed events; it defines TX queue flush attempt timeout
33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
38 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa)
40 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
43 if ((sa->priv.dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) &&
44 encp->enc_hw_tx_insert_vlan_enabled)
45 caps |= DEV_TX_OFFLOAD_VLAN_INSERT;
47 if (sa->priv.dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG)
48 caps |= DEV_TX_OFFLOAD_MULTI_SEGS;
50 if ((~sa->priv.dp_tx->features & SFC_DP_TX_FEAT_MULTI_POOL) &&
51 (~sa->priv.dp_tx->features & SFC_DP_TX_FEAT_REFCNT))
52 caps |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
58 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa)
60 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
63 caps |= DEV_TX_OFFLOAD_IPV4_CKSUM;
64 caps |= DEV_TX_OFFLOAD_UDP_CKSUM;
65 caps |= DEV_TX_OFFLOAD_TCP_CKSUM;
67 if (encp->enc_tunnel_encapsulations_supported)
68 caps |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
71 caps |= DEV_TX_OFFLOAD_TCP_TSO;
77 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level,
78 const struct rte_eth_txconf *tx_conf,
83 if (tx_conf->tx_rs_thresh != 0) {
84 sfc_err(sa, "RS bit in transmit descriptor is not supported");
88 if (tx_conf->tx_free_thresh > txq_max_fill_level) {
90 "TxQ free threshold too large: %u vs maximum %u",
91 tx_conf->tx_free_thresh, txq_max_fill_level);
95 if (tx_conf->tx_thresh.pthresh != 0 ||
96 tx_conf->tx_thresh.hthresh != 0 ||
97 tx_conf->tx_thresh.wthresh != 0) {
99 "prefetch/host/writeback thresholds are not supported");
102 /* We either perform both TCP and UDP offload, or no offload at all */
103 if (((offloads & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) !=
104 ((offloads & DEV_TX_OFFLOAD_UDP_CKSUM) == 0)) {
105 sfc_err(sa, "TCP and UDP offloads can't be set independently");
113 sfc_tx_qflush_done(struct sfc_txq_info *txq_info)
115 txq_info->state |= SFC_TXQ_FLUSHED;
116 txq_info->state &= ~SFC_TXQ_FLUSHING;
120 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
121 uint16_t nb_tx_desc, unsigned int socket_id,
122 const struct rte_eth_txconf *tx_conf)
124 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
125 unsigned int txq_entries;
126 unsigned int evq_entries;
127 unsigned int txq_max_fill_level;
128 struct sfc_txq_info *txq_info;
132 struct sfc_dp_tx_qcreate_info info;
134 struct sfc_dp_tx_hw_limits hw_limits;
136 sfc_log_init(sa, "TxQ = %u", sw_index);
138 memset(&hw_limits, 0, sizeof(hw_limits));
139 hw_limits.txq_max_entries = sa->txq_max_entries;
140 hw_limits.txq_min_entries = sa->txq_min_entries;
142 rc = sa->priv.dp_tx->qsize_up_rings(nb_tx_desc, &hw_limits,
143 &txq_entries, &evq_entries,
144 &txq_max_fill_level);
146 goto fail_size_up_rings;
147 SFC_ASSERT(txq_entries >= sa->txq_min_entries);
148 SFC_ASSERT(txq_entries <= sa->txq_max_entries);
149 SFC_ASSERT(txq_entries >= nb_tx_desc);
150 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc);
152 offloads = tx_conf->offloads |
153 sa->eth_dev->data->dev_conf.txmode.offloads;
154 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf, offloads);
158 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
159 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
161 txq_info->entries = txq_entries;
163 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
164 evq_entries, socket_id, &evq);
168 txq = &sa->txq_ctrl[sw_index];
169 txq->hw_index = sw_index;
171 txq_info->free_thresh =
172 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
173 SFC_TX_DEFAULT_FREE_THRESH;
174 txq_info->offloads = offloads;
176 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
177 socket_id, &txq->mem);
181 memset(&info, 0, sizeof(info));
182 info.max_fill_level = txq_max_fill_level;
183 info.free_thresh = txq_info->free_thresh;
184 info.offloads = offloads;
185 info.txq_entries = txq_info->entries;
186 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
187 info.txq_hw_ring = txq->mem.esm_base;
188 info.evq_entries = evq_entries;
189 info.evq_hw_ring = evq->mem.esm_base;
190 info.hw_index = txq->hw_index;
191 info.mem_bar = sa->mem_bar.esb_base;
192 info.vi_window_shift = encp->enc_vi_window_shift;
193 info.tso_tcp_header_offset_limit =
194 encp->enc_tx_tso_tcp_header_offset_limit;
196 rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
197 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
198 socket_id, &info, &txq_info->dp);
200 goto fail_dp_tx_qinit;
202 evq->dp_txq = txq_info->dp;
204 txq_info->state = SFC_TXQ_INITIALIZED;
206 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
211 sfc_dma_free(sa, &txq->mem);
217 txq_info->entries = 0;
221 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
226 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
228 struct sfc_txq_info *txq_info;
231 sfc_log_init(sa, "TxQ = %u", sw_index);
233 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
234 sa->eth_dev->data->tx_queues[sw_index] = NULL;
236 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
238 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
240 sa->priv.dp_tx->qdestroy(txq_info->dp);
243 txq_info->state &= ~SFC_TXQ_INITIALIZED;
244 txq_info->entries = 0;
246 txq = &sa->txq_ctrl[sw_index];
248 sfc_dma_free(sa, &txq->mem);
250 sfc_ev_qfini(txq->evq);
255 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
257 sfc_log_init(sa, "TxQ = %u", sw_index);
263 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
267 switch (txmode->mq_mode) {
271 sfc_err(sa, "Tx multi-queue mode %u not supported",
277 * These features are claimed to be i40e-specific,
278 * but it does make sense to double-check their absence
280 if (txmode->hw_vlan_reject_tagged) {
281 sfc_err(sa, "Rejecting tagged packets not supported");
285 if (txmode->hw_vlan_reject_untagged) {
286 sfc_err(sa, "Rejecting untagged packets not supported");
290 if (txmode->hw_vlan_insert_pvid) {
291 sfc_err(sa, "Port-based VLAN insertion not supported");
299 * Destroy excess queues that are no longer needed after reconfiguration
303 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues)
305 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
308 SFC_ASSERT(nb_tx_queues <= sas->txq_count);
310 sw_index = sas->txq_count;
311 while (--sw_index >= (int)nb_tx_queues) {
312 if (sas->txq_info[sw_index].state & SFC_TXQ_INITIALIZED)
313 sfc_tx_qfini(sa, sw_index);
316 sas->txq_count = nb_tx_queues;
320 sfc_tx_configure(struct sfc_adapter *sa)
322 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
323 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
324 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
325 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues;
328 sfc_log_init(sa, "nb_tx_queues=%u (old %u)",
329 nb_tx_queues, sas->txq_count);
332 * The datapath implementation assumes absence of boundary
333 * limits on Tx DMA descriptors. Addition of these checks on
334 * datapath would simply make the datapath slower.
336 if (encp->enc_tx_dma_desc_boundary != 0) {
338 goto fail_tx_dma_desc_boundary;
341 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
343 goto fail_check_mode;
345 if (nb_tx_queues == sas->txq_count)
348 if (sas->txq_info == NULL) {
349 sas->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues,
350 sizeof(sas->txq_info[0]), 0,
352 if (sas->txq_info == NULL)
353 goto fail_txqs_alloc;
356 * Allocate primary process only TxQ control from heap
357 * since it should not be shared.
360 sa->txq_ctrl = calloc(nb_tx_queues, sizeof(sa->txq_ctrl[0]));
361 if (sa->txq_ctrl == NULL)
362 goto fail_txqs_ctrl_alloc;
364 struct sfc_txq_info *new_txq_info;
365 struct sfc_txq *new_txq_ctrl;
367 if (nb_tx_queues < sas->txq_count)
368 sfc_tx_fini_queues(sa, nb_tx_queues);
371 rte_realloc(sas->txq_info,
372 nb_tx_queues * sizeof(sas->txq_info[0]), 0);
373 if (new_txq_info == NULL && nb_tx_queues > 0)
374 goto fail_txqs_realloc;
376 new_txq_ctrl = realloc(sa->txq_ctrl,
377 nb_tx_queues * sizeof(sa->txq_ctrl[0]));
378 if (new_txq_ctrl == NULL && nb_tx_queues > 0)
379 goto fail_txqs_ctrl_realloc;
381 sas->txq_info = new_txq_info;
382 sa->txq_ctrl = new_txq_ctrl;
383 if (nb_tx_queues > sas->txq_count) {
384 memset(&sas->txq_info[sas->txq_count], 0,
385 (nb_tx_queues - sas->txq_count) *
386 sizeof(sas->txq_info[0]));
387 memset(&sa->txq_ctrl[sas->txq_count], 0,
388 (nb_tx_queues - sas->txq_count) *
389 sizeof(sa->txq_ctrl[0]));
393 while (sas->txq_count < nb_tx_queues) {
394 rc = sfc_tx_qinit_info(sa, sas->txq_count);
396 goto fail_tx_qinit_info;
405 fail_txqs_ctrl_realloc:
407 fail_txqs_ctrl_alloc:
412 fail_tx_dma_desc_boundary:
413 sfc_log_init(sa, "failed (rc = %d)", rc);
418 sfc_tx_close(struct sfc_adapter *sa)
420 sfc_tx_fini_queues(sa, 0);
425 rte_free(sfc_sa2shared(sa)->txq_info);
426 sfc_sa2shared(sa)->txq_info = NULL;
430 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
432 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
433 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) |
434 sfc_tx_get_queue_offload_caps(sa);
435 struct rte_eth_dev_data *dev_data;
436 struct sfc_txq_info *txq_info;
440 unsigned int desc_index;
443 sfc_log_init(sa, "TxQ = %u", sw_index);
445 SFC_ASSERT(sw_index < sas->txq_count);
446 txq_info = &sas->txq_info[sw_index];
448 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
450 txq = &sa->txq_ctrl[sw_index];
453 rc = sfc_ev_qstart(evq, sfc_evq_index_by_txq_sw_index(sa, sw_index));
457 if (txq_info->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
458 flags |= EFX_TXQ_CKSUM_IPV4;
460 if (txq_info->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
461 flags |= EFX_TXQ_CKSUM_INNER_IPV4;
463 if ((txq_info->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
464 (txq_info->offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
465 flags |= EFX_TXQ_CKSUM_TCPUDP;
467 if (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
468 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP;
471 if (txq_info->offloads & DEV_TX_OFFLOAD_TCP_TSO)
472 flags |= EFX_TXQ_FATSOV2;
474 rc = efx_tx_qcreate(sa->nic, txq->hw_index, 0, &txq->mem,
475 txq_info->entries, 0 /* not used on EF10 */,
477 &txq->common, &desc_index);
479 if (sa->tso && (rc == ENOSPC))
480 sfc_err(sa, "ran out of TSO contexts");
482 goto fail_tx_qcreate;
485 efx_tx_qenable(txq->common);
487 txq_info->state |= SFC_TXQ_STARTED;
489 rc = sa->priv.dp_tx->qstart(txq_info->dp, evq->read_ptr, desc_index);
494 * It seems to be used by DPDK for debug purposes only ('rte_ether')
496 dev_data = sa->eth_dev->data;
497 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
502 txq_info->state = SFC_TXQ_INITIALIZED;
503 efx_tx_qdestroy(txq->common);
513 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
515 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
516 struct rte_eth_dev_data *dev_data;
517 struct sfc_txq_info *txq_info;
519 unsigned int retry_count;
520 unsigned int wait_count;
523 sfc_log_init(sa, "TxQ = %u", sw_index);
525 SFC_ASSERT(sw_index < sas->txq_count);
526 txq_info = &sas->txq_info[sw_index];
528 if (txq_info->state == SFC_TXQ_INITIALIZED)
531 SFC_ASSERT(txq_info->state & SFC_TXQ_STARTED);
533 txq = &sa->txq_ctrl[sw_index];
534 sa->priv.dp_tx->qstop(txq_info->dp, &txq->evq->read_ptr);
537 * Retry TX queue flushing in case of flush failed or
538 * timeout; in the worst case it can delay for 6 seconds
540 for (retry_count = 0;
541 ((txq_info->state & SFC_TXQ_FLUSHED) == 0) &&
542 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
544 rc = efx_tx_qflush(txq->common);
546 txq_info->state |= (rc == EALREADY) ?
547 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED;
552 * Wait for TX queue flush done or flush failed event at least
553 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
554 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
555 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
559 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
560 sfc_ev_qpoll(txq->evq);
561 } while ((txq_info->state & SFC_TXQ_FLUSHING) &&
562 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
564 if (txq_info->state & SFC_TXQ_FLUSHING)
565 sfc_err(sa, "TxQ %u flush timed out", sw_index);
567 if (txq_info->state & SFC_TXQ_FLUSHED)
568 sfc_notice(sa, "TxQ %u flushed", sw_index);
571 sa->priv.dp_tx->qreap(txq_info->dp);
573 txq_info->state = SFC_TXQ_INITIALIZED;
575 efx_tx_qdestroy(txq->common);
577 sfc_ev_qstop(txq->evq);
580 * It seems to be used by DPDK for debug purposes only ('rte_ether')
582 dev_data = sa->eth_dev->data;
583 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
587 sfc_tx_start(struct sfc_adapter *sa)
589 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
590 unsigned int sw_index;
593 sfc_log_init(sa, "txq_count = %u", sas->txq_count);
596 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
597 sfc_warn(sa, "TSO support was unable to be restored");
602 rc = efx_tx_init(sa->nic);
604 goto fail_efx_tx_init;
606 for (sw_index = 0; sw_index < sas->txq_count; ++sw_index) {
607 if (sas->txq_info[sw_index].state == SFC_TXQ_INITIALIZED &&
608 (!(sas->txq_info[sw_index].deferred_start) ||
609 sas->txq_info[sw_index].deferred_started)) {
610 rc = sfc_tx_qstart(sa, sw_index);
619 while (sw_index-- > 0)
620 sfc_tx_qstop(sa, sw_index);
622 efx_tx_fini(sa->nic);
625 sfc_log_init(sa, "failed (rc = %d)", rc);
630 sfc_tx_stop(struct sfc_adapter *sa)
632 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
633 unsigned int sw_index;
635 sfc_log_init(sa, "txq_count = %u", sas->txq_count);
637 sw_index = sas->txq_count;
638 while (sw_index-- > 0) {
639 if (sas->txq_info[sw_index].state & SFC_TXQ_STARTED)
640 sfc_tx_qstop(sa, sw_index);
643 efx_tx_fini(sa->nic);
647 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
649 unsigned int completed;
651 sfc_ev_qpoll(txq->evq);
653 for (completed = txq->completed;
654 completed != txq->pending; completed++) {
655 struct sfc_efx_tx_sw_desc *txd;
657 txd = &txq->sw_ring[completed & txq->ptr_mask];
659 if (txd->mbuf != NULL) {
660 rte_pktmbuf_free(txd->mbuf);
665 txq->completed = completed;
669 * The function is used to insert or update VLAN tag;
670 * the firmware has state of the firmware tag to insert per TxQ
671 * (controlled by option descriptors), hence, if the tag of the
672 * packet to be sent is different from one remembered by the firmware,
673 * the function will update it
676 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
679 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
682 if (this_tag == txq->hw_vlan_tci)
686 * The expression inside SFC_ASSERT() is not desired to be checked in
687 * a non-debug build because it might be too expensive on the data path
689 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
691 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
694 txq->hw_vlan_tci = this_tag;
700 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
702 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
703 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
704 unsigned int added = txq->added;
705 unsigned int pushed = added;
706 unsigned int pkts_sent = 0;
707 efx_desc_t *pend = &txq->pend_desc[0];
708 const unsigned int hard_max_fill = txq->max_fill_level;
709 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
710 unsigned int fill_level = added - txq->completed;
713 struct rte_mbuf **pktp;
715 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
719 * If insufficient space for a single packet is present,
720 * we should reap; otherwise, we shouldn't do that all the time
721 * to avoid latency increase
723 reap_done = (fill_level > soft_max_fill);
726 sfc_efx_tx_reap(txq);
728 * Recalculate fill level since 'txq->completed'
729 * might have changed on reap
731 fill_level = added - txq->completed;
734 for (pkts_sent = 0, pktp = &tx_pkts[0];
735 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
736 pkts_sent++, pktp++) {
737 uint16_t hw_vlan_tci_prev = txq->hw_vlan_tci;
738 struct rte_mbuf *m_seg = *pktp;
739 size_t pkt_len = m_seg->pkt_len;
740 unsigned int pkt_descs = 0;
744 * Here VLAN TCI is expected to be zero in case if no
745 * DEV_TX_OFFLOAD_VLAN_INSERT capability is advertised;
746 * if the calling app ignores the absence of
747 * DEV_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then
748 * TX_ERROR will occur
750 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
752 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
754 * We expect correct 'pkt->l[2, 3, 4]_len' values
755 * to be set correctly by the caller
757 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
758 &pkt_descs, &pkt_len) != 0) {
759 /* We may have reached this place for
760 * one of the following reasons:
762 * 1) Packet header length is greater
763 * than SFC_TSOH_STD_LEN
764 * 2) TCP header starts at more then
765 * 208 bytes into the frame
767 * We will deceive RTE saying that we have sent
768 * the packet, but we will actually drop it.
769 * Hence, we should revert 'pend' to the
770 * previous state (in case we have added
771 * VLAN descriptor) and start processing
772 * another one packet. But the original
773 * mbuf shouldn't be orphaned
776 txq->hw_vlan_tci = hw_vlan_tci_prev;
778 rte_pktmbuf_free(*pktp);
784 * We've only added 2 FATSOv2 option descriptors
785 * and 1 descriptor for the linearized packet header.
786 * The outstanding work will be done in the same manner
787 * as for the usual non-TSO path
791 for (; m_seg != NULL; m_seg = m_seg->next) {
792 efsys_dma_addr_t next_frag;
795 seg_len = m_seg->data_len;
796 next_frag = rte_mbuf_data_iova(m_seg);
799 * If we've started TSO transaction few steps earlier,
800 * we'll skip packet header using an offset in the
801 * current segment (which has been set to the
802 * first one containing payload)
809 efsys_dma_addr_t frag_addr = next_frag;
813 * It is assumed here that there is no
814 * limitation on address boundary
815 * crossing by DMA descriptor.
817 frag_len = MIN(seg_len, txq->dma_desc_size_max);
818 next_frag += frag_len;
822 efx_tx_qdesc_dma_create(txq->common,
828 } while (seg_len != 0);
833 fill_level += pkt_descs;
834 if (unlikely(fill_level > hard_max_fill)) {
836 * Our estimation for maximum number of descriptors
837 * required to send a packet seems to be wrong.
838 * Try to reap (if we haven't yet).
841 sfc_efx_tx_reap(txq);
843 fill_level = added - txq->completed;
844 if (fill_level > hard_max_fill) {
846 txq->hw_vlan_tci = hw_vlan_tci_prev;
851 txq->hw_vlan_tci = hw_vlan_tci_prev;
856 /* Assign mbuf to the last used desc */
857 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
860 if (likely(pkts_sent > 0)) {
861 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
862 pend - &txq->pend_desc[0],
863 txq->completed, &txq->added);
866 if (likely(pushed != txq->added))
867 efx_tx_qpush(txq->common, txq->added, pushed);
870 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
872 sfc_efx_tx_reap(txq);
879 const struct sfc_dp_tx *
880 sfc_dp_tx_by_dp_txq(const struct sfc_dp_txq *dp_txq)
882 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
883 struct rte_eth_dev *eth_dev;
884 struct sfc_adapter_priv *sap;
886 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
887 eth_dev = &rte_eth_devices[dpq->port_id];
889 sap = sfc_adapter_priv_by_eth_dev(eth_dev);
894 struct sfc_txq_info *
895 sfc_txq_info_by_dp_txq(const struct sfc_dp_txq *dp_txq)
897 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
898 struct rte_eth_dev *eth_dev;
899 struct sfc_adapter_shared *sas;
901 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
902 eth_dev = &rte_eth_devices[dpq->port_id];
904 sas = sfc_adapter_shared_by_eth_dev(eth_dev);
906 SFC_ASSERT(dpq->queue_id < sas->txq_count);
907 return &sas->txq_info[dpq->queue_id];
911 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
913 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
914 struct rte_eth_dev *eth_dev;
915 struct sfc_adapter *sa;
917 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
918 eth_dev = &rte_eth_devices[dpq->port_id];
920 sa = sfc_adapter_by_eth_dev(eth_dev);
922 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->txq_count);
923 return &sa->txq_ctrl[dpq->queue_id];
926 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings;
928 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc,
929 __rte_unused struct sfc_dp_tx_hw_limits *limits,
930 unsigned int *txq_entries,
931 unsigned int *evq_entries,
932 unsigned int *txq_max_fill_level)
934 *txq_entries = nb_tx_desc;
935 *evq_entries = nb_tx_desc;
936 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries);
940 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
942 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
943 const struct rte_pci_addr *pci_addr,
945 const struct sfc_dp_tx_qcreate_info *info,
946 struct sfc_dp_txq **dp_txqp)
948 struct sfc_efx_txq *txq;
949 struct sfc_txq *ctrl_txq;
953 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
954 RTE_CACHE_LINE_SIZE, socket_id);
958 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
961 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
962 EFX_TXQ_LIMIT(info->txq_entries),
963 sizeof(*txq->pend_desc), 0,
965 if (txq->pend_desc == NULL)
966 goto fail_pend_desc_alloc;
969 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
971 sizeof(*txq->sw_ring),
972 RTE_CACHE_LINE_SIZE, socket_id);
973 if (txq->sw_ring == NULL)
974 goto fail_sw_ring_alloc;
976 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
977 if (ctrl_txq->evq->sa->tso) {
978 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
979 info->txq_entries, socket_id);
981 goto fail_alloc_tsoh_objs;
984 txq->evq = ctrl_txq->evq;
985 txq->ptr_mask = info->txq_entries - 1;
986 txq->max_fill_level = info->max_fill_level;
987 txq->free_thresh = info->free_thresh;
988 txq->dma_desc_size_max = info->dma_desc_size_max;
993 fail_alloc_tsoh_objs:
994 rte_free(txq->sw_ring);
997 rte_free(txq->pend_desc);
999 fail_pend_desc_alloc:
1006 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
1008 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
1010 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1012 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
1013 rte_free(txq->sw_ring);
1014 rte_free(txq->pend_desc);
1018 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
1020 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
1021 __rte_unused unsigned int evq_read_ptr,
1022 unsigned int txq_desc_index)
1024 /* libefx-based datapath is specific to libefx-based PMD */
1025 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1026 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
1028 txq->common = ctrl_txq->common;
1030 txq->pending = txq->completed = txq->added = txq_desc_index;
1031 txq->hw_vlan_tci = 0;
1033 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
1038 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
1040 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
1041 __rte_unused unsigned int *evq_read_ptr)
1043 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1045 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
1048 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
1050 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
1052 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1055 sfc_efx_tx_reap(txq);
1057 for (txds = 0; txds <= txq->ptr_mask; txds++) {
1058 if (txq->sw_ring[txds].mbuf != NULL) {
1059 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
1060 txq->sw_ring[txds].mbuf = NULL;
1064 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
1067 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status;
1069 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
1071 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1073 if (unlikely(offset > txq->ptr_mask))
1076 if (unlikely(offset >= txq->max_fill_level))
1077 return RTE_ETH_TX_DESC_UNAVAIL;
1080 * Poll EvQ to derive up-to-date 'txq->pending' figure;
1081 * it is required for the queue to be running, but the
1082 * check is omitted because API design assumes that it
1083 * is the duty of the caller to satisfy all conditions
1085 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) ==
1086 SFC_EFX_TXQ_FLAG_RUNNING);
1087 sfc_ev_qpoll(txq->evq);
1090 * Ring tail is 'txq->pending', and although descriptors
1091 * between 'txq->completed' and 'txq->pending' are still
1092 * in use by the driver, they should be reported as DONE
1094 if (unlikely(offset < (txq->added - txq->pending)))
1095 return RTE_ETH_TX_DESC_FULL;
1098 * There is no separate return value for unused descriptors;
1099 * the latter will be reported as DONE because genuine DONE
1100 * descriptors will be freed anyway in SW on the next burst
1102 return RTE_ETH_TX_DESC_DONE;
1105 struct sfc_dp_tx sfc_efx_tx = {
1107 .name = SFC_KVARG_DATAPATH_EFX,
1111 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
1112 SFC_DP_TX_FEAT_TSO |
1113 SFC_DP_TX_FEAT_MULTI_POOL |
1114 SFC_DP_TX_FEAT_REFCNT |
1115 SFC_DP_TX_FEAT_MULTI_SEG,
1116 .qsize_up_rings = sfc_efx_tx_qsize_up_rings,
1117 .qcreate = sfc_efx_tx_qcreate,
1118 .qdestroy = sfc_efx_tx_qdestroy,
1119 .qstart = sfc_efx_tx_qstart,
1120 .qstop = sfc_efx_tx_qstop,
1121 .qreap = sfc_efx_tx_qreap,
1122 .qdesc_status = sfc_efx_tx_qdesc_status,
1123 .pkt_burst = sfc_efx_xmit_pkts,