4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "sfc_debug.h"
37 #include "sfc_tweak.h"
38 #include "sfc_kvargs.h"
41 * Maximum number of TX queue flush attempts in case of
42 * failure or flush timeout
44 #define SFC_TX_QFLUSH_ATTEMPTS (3)
47 * Time to wait between event queue polling attempts when waiting for TX
48 * queue flush done or flush failed events
50 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
53 * Maximum number of event queue polling attempts when waiting for TX queue
54 * flush done or flush failed events; it defines TX queue flush attempt timeout
55 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
57 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
60 sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc,
61 const struct rte_eth_txconf *tx_conf)
63 unsigned int flags = tx_conf->txq_flags;
64 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
67 if (tx_conf->tx_rs_thresh != 0) {
68 sfc_err(sa, "RS bit in transmit descriptor is not supported");
72 if (tx_conf->tx_free_thresh > EFX_TXQ_LIMIT(nb_tx_desc)) {
74 "TxQ free threshold too large: %u vs maximum %u",
75 tx_conf->tx_free_thresh, EFX_TXQ_LIMIT(nb_tx_desc));
79 if (tx_conf->tx_thresh.pthresh != 0 ||
80 tx_conf->tx_thresh.hthresh != 0 ||
81 tx_conf->tx_thresh.wthresh != 0) {
83 "prefetch/host/writeback thresholds are not supported");
87 if ((flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
88 if (!encp->enc_hw_tx_insert_vlan_enabled) {
89 sfc_err(sa, "VLAN offload is not supported");
91 } else if (~sa->dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) {
93 "VLAN offload is not supported by %s datapath",
99 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
100 sfc_err(sa, "SCTP offload is not supported");
104 /* We either perform both TCP and UDP offload, or no offload at all */
105 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
106 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
107 sfc_err(sa, "TCP and UDP offloads can't be set independently");
115 sfc_tx_qflush_done(struct sfc_txq *txq)
117 txq->state |= SFC_TXQ_FLUSHED;
118 txq->state &= ~SFC_TXQ_FLUSHING;
122 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
123 uint16_t nb_tx_desc, unsigned int socket_id,
124 const struct rte_eth_txconf *tx_conf)
126 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
127 struct sfc_txq_info *txq_info;
130 unsigned int evq_index = sfc_evq_index_by_txq_sw_index(sa, sw_index);
132 struct sfc_dp_tx_qcreate_info info;
134 sfc_log_init(sa, "TxQ = %u", sw_index);
136 rc = sfc_tx_qcheck_conf(sa, nb_tx_desc, tx_conf);
140 SFC_ASSERT(sw_index < sa->txq_count);
141 txq_info = &sa->txq_info[sw_index];
143 SFC_ASSERT(nb_tx_desc <= sa->txq_max_entries);
144 txq_info->entries = nb_tx_desc;
146 rc = sfc_ev_qinit(sa, evq_index, txq_info->entries, socket_id);
150 evq = sa->evq_info[evq_index].evq;
153 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
159 txq->hw_index = sw_index;
162 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
163 SFC_TX_DEFAULT_FREE_THRESH;
164 txq->flags = tx_conf->txq_flags;
166 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
167 socket_id, &txq->mem);
171 memset(&info, 0, sizeof(info));
172 info.free_thresh = txq->free_thresh;
173 info.flags = tx_conf->txq_flags;
174 info.txq_entries = txq_info->entries;
175 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
176 info.txq_hw_ring = txq->mem.esm_base;
177 info.evq_entries = txq_info->entries;
178 info.evq_hw_ring = evq->mem.esm_base;
179 info.hw_index = txq->hw_index;
180 info.mem_bar = sa->mem_bar.esb_base;
182 rc = sa->dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
183 &SFC_DEV_TO_PCI(sa->eth_dev)->addr,
184 socket_id, &info, &txq->dp);
186 goto fail_dp_tx_qinit;
188 evq->dp_txq = txq->dp;
190 txq->state = SFC_TXQ_INITIALIZED;
192 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
197 sfc_dma_free(sa, &txq->mem);
200 txq_info->txq = NULL;
204 sfc_ev_qfini(sa, evq_index);
207 txq_info->entries = 0;
210 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
215 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
217 struct sfc_txq_info *txq_info;
220 sfc_log_init(sa, "TxQ = %u", sw_index);
222 SFC_ASSERT(sw_index < sa->txq_count);
223 txq_info = &sa->txq_info[sw_index];
226 SFC_ASSERT(txq != NULL);
227 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
229 sa->dp_tx->qdestroy(txq->dp);
232 txq_info->txq = NULL;
233 txq_info->entries = 0;
235 sfc_dma_free(sa, &txq->mem);
240 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
242 sfc_log_init(sa, "TxQ = %u", sw_index);
248 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
252 switch (txmode->mq_mode) {
256 sfc_err(sa, "Tx multi-queue mode %u not supported",
262 * These features are claimed to be i40e-specific,
263 * but it does make sense to double-check their absence
265 if (txmode->hw_vlan_reject_tagged) {
266 sfc_err(sa, "Rejecting tagged packets not supported");
270 if (txmode->hw_vlan_reject_untagged) {
271 sfc_err(sa, "Rejecting untagged packets not supported");
275 if (txmode->hw_vlan_insert_pvid) {
276 sfc_err(sa, "Port-based VLAN insertion not supported");
284 sfc_tx_init(struct sfc_adapter *sa)
286 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
287 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
288 unsigned int sw_index;
292 * The datapath implementation assumes absence of boundary
293 * limits on Tx DMA descriptors. Addition of these checks on
294 * datapath would simply make the datapath slower.
296 if (encp->enc_tx_dma_desc_boundary != 0) {
298 goto fail_tx_dma_desc_boundary;
301 if (~sa->dp_tx->features & SFC_DP_TX_FEAT_TSO)
304 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
306 goto fail_check_mode;
308 sa->txq_count = sa->eth_dev->data->nb_tx_queues;
310 sa->txq_info = rte_calloc_socket("sfc-txqs", sa->txq_count,
311 sizeof(sa->txq_info[0]), 0,
313 if (sa->txq_info == NULL)
314 goto fail_txqs_alloc;
316 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
317 rc = sfc_tx_qinit_info(sa, sw_index);
319 goto fail_tx_qinit_info;
325 rte_free(sa->txq_info);
332 fail_tx_dma_desc_boundary:
333 sfc_log_init(sa, "failed (rc = %d)", rc);
338 sfc_tx_fini(struct sfc_adapter *sa)
342 sw_index = sa->txq_count;
343 while (--sw_index >= 0) {
344 if (sa->txq_info[sw_index].txq != NULL)
345 sfc_tx_qfini(sa, sw_index);
348 rte_free(sa->txq_info);
354 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
356 struct rte_eth_dev_data *dev_data;
357 struct sfc_txq_info *txq_info;
361 unsigned int desc_index;
364 sfc_log_init(sa, "TxQ = %u", sw_index);
366 SFC_ASSERT(sw_index < sa->txq_count);
367 txq_info = &sa->txq_info[sw_index];
371 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
375 rc = sfc_ev_qstart(sa, evq->evq_index);
380 * It seems that DPDK has no controls regarding IPv4 offloads,
381 * hence, we always enable it here
383 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
384 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP)) {
385 flags = EFX_TXQ_CKSUM_IPV4;
387 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
390 flags |= EFX_TXQ_FATSOV2;
393 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
394 txq_info->entries, 0 /* not used on EF10 */,
396 &txq->common, &desc_index);
398 if (sa->tso && (rc == ENOSPC))
399 sfc_err(sa, "ran out of TSO contexts");
401 goto fail_tx_qcreate;
404 efx_tx_qenable(txq->common);
406 txq->state |= SFC_TXQ_STARTED;
408 rc = sa->dp_tx->qstart(txq->dp, evq->read_ptr, desc_index);
413 * It seems to be used by DPDK for debug purposes only ('rte_ether')
415 dev_data = sa->eth_dev->data;
416 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
421 txq->state = SFC_TXQ_INITIALIZED;
422 efx_tx_qdestroy(txq->common);
425 sfc_ev_qstop(sa, evq->evq_index);
432 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
434 struct rte_eth_dev_data *dev_data;
435 struct sfc_txq_info *txq_info;
437 unsigned int retry_count;
438 unsigned int wait_count;
440 sfc_log_init(sa, "TxQ = %u", sw_index);
442 SFC_ASSERT(sw_index < sa->txq_count);
443 txq_info = &sa->txq_info[sw_index];
447 if (txq->state == SFC_TXQ_INITIALIZED)
450 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
452 sa->dp_tx->qstop(txq->dp, &txq->evq->read_ptr);
455 * Retry TX queue flushing in case of flush failed or
456 * timeout; in the worst case it can delay for 6 seconds
458 for (retry_count = 0;
459 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
460 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
462 if (efx_tx_qflush(txq->common) != 0) {
463 txq->state |= SFC_TXQ_FLUSHING;
468 * Wait for TX queue flush done or flush failed event at least
469 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
470 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
471 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
475 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
476 sfc_ev_qpoll(txq->evq);
477 } while ((txq->state & SFC_TXQ_FLUSHING) &&
478 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
480 if (txq->state & SFC_TXQ_FLUSHING)
481 sfc_err(sa, "TxQ %u flush timed out", sw_index);
483 if (txq->state & SFC_TXQ_FLUSHED)
484 sfc_info(sa, "TxQ %u flushed", sw_index);
487 sa->dp_tx->qreap(txq->dp);
489 txq->state = SFC_TXQ_INITIALIZED;
491 efx_tx_qdestroy(txq->common);
493 sfc_ev_qstop(sa, txq->evq->evq_index);
496 * It seems to be used by DPDK for debug purposes only ('rte_ether')
498 dev_data = sa->eth_dev->data;
499 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
503 sfc_tx_start(struct sfc_adapter *sa)
505 unsigned int sw_index;
508 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
511 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
512 sfc_warn(sa, "TSO support was unable to be restored");
517 rc = efx_tx_init(sa->nic);
519 goto fail_efx_tx_init;
521 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
522 if (!(sa->txq_info[sw_index].deferred_start) ||
523 sa->txq_info[sw_index].deferred_started) {
524 rc = sfc_tx_qstart(sa, sw_index);
533 while (sw_index-- > 0)
534 sfc_tx_qstop(sa, sw_index);
536 efx_tx_fini(sa->nic);
539 sfc_log_init(sa, "failed (rc = %d)", rc);
544 sfc_tx_stop(struct sfc_adapter *sa)
546 unsigned int sw_index;
548 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
550 sw_index = sa->txq_count;
551 while (sw_index-- > 0) {
552 if (sa->txq_info[sw_index].txq != NULL)
553 sfc_tx_qstop(sa, sw_index);
556 efx_tx_fini(sa->nic);
560 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
562 unsigned int completed;
564 sfc_ev_qpoll(txq->evq);
566 for (completed = txq->completed;
567 completed != txq->pending; completed++) {
568 struct sfc_efx_tx_sw_desc *txd;
570 txd = &txq->sw_ring[completed & txq->ptr_mask];
572 if (txd->mbuf != NULL) {
573 rte_pktmbuf_free(txd->mbuf);
578 txq->completed = completed;
582 * The function is used to insert or update VLAN tag;
583 * the firmware has state of the firmware tag to insert per TxQ
584 * (controlled by option descriptors), hence, if the tag of the
585 * packet to be sent is different from one remembered by the firmware,
586 * the function will update it
589 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
592 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
595 if (this_tag == txq->hw_vlan_tci)
599 * The expression inside SFC_ASSERT() is not desired to be checked in
600 * a non-debug build because it might be too expensive on the data path
602 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
604 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
607 txq->hw_vlan_tci = this_tag;
613 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
615 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
616 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
617 unsigned int added = txq->added;
618 unsigned int pushed = added;
619 unsigned int pkts_sent = 0;
620 efx_desc_t *pend = &txq->pend_desc[0];
621 const unsigned int hard_max_fill = EFX_TXQ_LIMIT(txq->ptr_mask + 1);
622 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
623 unsigned int fill_level = added - txq->completed;
626 struct rte_mbuf **pktp;
628 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
632 * If insufficient space for a single packet is present,
633 * we should reap; otherwise, we shouldn't do that all the time
634 * to avoid latency increase
636 reap_done = (fill_level > soft_max_fill);
639 sfc_efx_tx_reap(txq);
641 * Recalculate fill level since 'txq->completed'
642 * might have changed on reap
644 fill_level = added - txq->completed;
647 for (pkts_sent = 0, pktp = &tx_pkts[0];
648 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
649 pkts_sent++, pktp++) {
650 struct rte_mbuf *m_seg = *pktp;
651 size_t pkt_len = m_seg->pkt_len;
652 unsigned int pkt_descs = 0;
656 * Here VLAN TCI is expected to be zero in case if no
657 * DEV_TX_VLAN_OFFLOAD capability is advertised;
658 * if the calling app ignores the absence of
659 * DEV_TX_VLAN_OFFLOAD and pushes VLAN TCI, then
660 * TX_ERROR will occur
662 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
664 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
666 * We expect correct 'pkt->l[2, 3, 4]_len' values
667 * to be set correctly by the caller
669 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
670 &pkt_descs, &pkt_len) != 0) {
671 /* We may have reached this place for
672 * one of the following reasons:
674 * 1) Packet header length is greater
675 * than SFC_TSOH_STD_LEN
676 * 2) TCP header starts at more then
677 * 208 bytes into the frame
679 * We will deceive RTE saying that we have sent
680 * the packet, but we will actually drop it.
681 * Hence, we should revert 'pend' to the
682 * previous state (in case we have added
683 * VLAN descriptor) and start processing
684 * another one packet. But the original
685 * mbuf shouldn't be orphaned
689 rte_pktmbuf_free(*pktp);
695 * We've only added 2 FATSOv2 option descriptors
696 * and 1 descriptor for the linearized packet header.
697 * The outstanding work will be done in the same manner
698 * as for the usual non-TSO path
702 for (; m_seg != NULL; m_seg = m_seg->next) {
703 efsys_dma_addr_t next_frag;
706 seg_len = m_seg->data_len;
707 next_frag = rte_mbuf_data_dma_addr(m_seg);
710 * If we've started TSO transaction few steps earlier,
711 * we'll skip packet header using an offset in the
712 * current segment (which has been set to the
713 * first one containing payload)
720 efsys_dma_addr_t frag_addr = next_frag;
724 * It is assumed here that there is no
725 * limitation on address boundary
726 * crossing by DMA descriptor.
728 frag_len = MIN(seg_len, txq->dma_desc_size_max);
729 next_frag += frag_len;
733 efx_tx_qdesc_dma_create(txq->common,
739 } while (seg_len != 0);
744 fill_level += pkt_descs;
745 if (unlikely(fill_level > hard_max_fill)) {
747 * Our estimation for maximum number of descriptors
748 * required to send a packet seems to be wrong.
749 * Try to reap (if we haven't yet).
752 sfc_efx_tx_reap(txq);
754 fill_level = added - txq->completed;
755 if (fill_level > hard_max_fill) {
765 /* Assign mbuf to the last used desc */
766 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
769 if (likely(pkts_sent > 0)) {
770 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
771 pend - &txq->pend_desc[0],
772 txq->completed, &txq->added);
775 if (likely(pushed != txq->added))
776 efx_tx_qpush(txq->common, txq->added, pushed);
779 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
781 sfc_efx_tx_reap(txq);
789 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
791 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
792 struct rte_eth_dev *eth_dev;
793 struct sfc_adapter *sa;
796 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
797 eth_dev = &rte_eth_devices[dpq->port_id];
799 sa = eth_dev->data->dev_private;
801 SFC_ASSERT(dpq->queue_id < sa->txq_count);
802 txq = sa->txq_info[dpq->queue_id].txq;
804 SFC_ASSERT(txq != NULL);
808 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
810 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
811 const struct rte_pci_addr *pci_addr,
813 const struct sfc_dp_tx_qcreate_info *info,
814 struct sfc_dp_txq **dp_txqp)
816 struct sfc_efx_txq *txq;
817 struct sfc_txq *ctrl_txq;
821 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
822 RTE_CACHE_LINE_SIZE, socket_id);
826 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
829 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
830 EFX_TXQ_LIMIT(info->txq_entries),
831 sizeof(*txq->pend_desc), 0,
833 if (txq->pend_desc == NULL)
834 goto fail_pend_desc_alloc;
837 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
839 sizeof(*txq->sw_ring),
840 RTE_CACHE_LINE_SIZE, socket_id);
841 if (txq->sw_ring == NULL)
842 goto fail_sw_ring_alloc;
844 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
845 if (ctrl_txq->evq->sa->tso) {
846 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
847 info->txq_entries, socket_id);
849 goto fail_alloc_tsoh_objs;
852 txq->evq = ctrl_txq->evq;
853 txq->ptr_mask = info->txq_entries - 1;
854 txq->free_thresh = info->free_thresh;
855 txq->dma_desc_size_max = info->dma_desc_size_max;
860 fail_alloc_tsoh_objs:
861 rte_free(txq->sw_ring);
864 rte_free(txq->pend_desc);
866 fail_pend_desc_alloc:
873 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
875 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
877 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
879 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
880 rte_free(txq->sw_ring);
881 rte_free(txq->pend_desc);
885 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
887 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
888 __rte_unused unsigned int evq_read_ptr,
889 unsigned int txq_desc_index)
891 /* libefx-based datapath is specific to libefx-based PMD */
892 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
893 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
895 txq->common = ctrl_txq->common;
897 txq->pending = txq->completed = txq->added = txq_desc_index;
898 txq->hw_vlan_tci = 0;
900 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
905 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
907 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
908 __rte_unused unsigned int *evq_read_ptr)
910 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
912 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
915 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
917 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
919 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
922 sfc_efx_tx_reap(txq);
924 for (txds = 0; txds <= txq->ptr_mask; txds++) {
925 if (txq->sw_ring[txds].mbuf != NULL) {
926 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
927 txq->sw_ring[txds].mbuf = NULL;
931 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
934 struct sfc_dp_tx sfc_efx_tx = {
936 .name = SFC_KVARG_DATAPATH_EFX,
940 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
942 .qcreate = sfc_efx_tx_qcreate,
943 .qdestroy = sfc_efx_tx_qdestroy,
944 .qstart = sfc_efx_tx_qstart,
945 .qstop = sfc_efx_tx_qstop,
946 .qreap = sfc_efx_tx_qreap,
947 .pkt_burst = sfc_efx_xmit_pkts,