4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "sfc_debug.h"
37 #include "sfc_tweak.h"
38 #include "sfc_kvargs.h"
41 * Maximum number of TX queue flush attempts in case of
42 * failure or flush timeout
44 #define SFC_TX_QFLUSH_ATTEMPTS (3)
47 * Time to wait between event queue polling attempts when waiting for TX
48 * queue flush done or flush failed events
50 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
53 * Maximum number of event queue polling attempts when waiting for TX queue
54 * flush done or flush failed events; it defines TX queue flush attempt timeout
55 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
57 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
60 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level,
61 const struct rte_eth_txconf *tx_conf)
63 unsigned int flags = tx_conf->txq_flags;
64 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
67 if (tx_conf->tx_rs_thresh != 0) {
68 sfc_err(sa, "RS bit in transmit descriptor is not supported");
72 if (tx_conf->tx_free_thresh > txq_max_fill_level) {
74 "TxQ free threshold too large: %u vs maximum %u",
75 tx_conf->tx_free_thresh, txq_max_fill_level);
79 if (tx_conf->tx_thresh.pthresh != 0 ||
80 tx_conf->tx_thresh.hthresh != 0 ||
81 tx_conf->tx_thresh.wthresh != 0) {
83 "prefetch/host/writeback thresholds are not supported");
86 if (((flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) &&
87 (~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG)) {
88 sfc_err(sa, "Multi-segment is not supported by %s datapath",
93 if (((flags & ETH_TXQ_FLAGS_NOMULTMEMP) == 0) &&
94 (~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_POOL)) {
95 sfc_err(sa, "multi-mempool is not supported by %s datapath",
100 if (((flags & ETH_TXQ_FLAGS_NOREFCOUNT) == 0) &&
101 (~sa->dp_tx->features & SFC_DP_TX_FEAT_REFCNT)) {
103 "mbuf reference counters are neglected by %s datapath",
108 if ((flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
109 if (!encp->enc_hw_tx_insert_vlan_enabled) {
110 sfc_err(sa, "VLAN offload is not supported");
112 } else if (~sa->dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) {
114 "VLAN offload is not supported by %s datapath",
120 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
121 sfc_err(sa, "SCTP offload is not supported");
125 /* We either perform both TCP and UDP offload, or no offload at all */
126 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
127 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
128 sfc_err(sa, "TCP and UDP offloads can't be set independently");
136 sfc_tx_qflush_done(struct sfc_txq *txq)
138 txq->state |= SFC_TXQ_FLUSHED;
139 txq->state &= ~SFC_TXQ_FLUSHING;
143 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
144 uint16_t nb_tx_desc, unsigned int socket_id,
145 const struct rte_eth_txconf *tx_conf)
147 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
148 unsigned int txq_entries;
149 unsigned int evq_entries;
150 unsigned int txq_max_fill_level;
151 struct sfc_txq_info *txq_info;
155 struct sfc_dp_tx_qcreate_info info;
157 sfc_log_init(sa, "TxQ = %u", sw_index);
159 rc = sa->dp_tx->qsize_up_rings(nb_tx_desc, &txq_entries, &evq_entries,
160 &txq_max_fill_level);
162 goto fail_size_up_rings;
163 SFC_ASSERT(txq_entries >= EFX_TXQ_MINNDESCS);
164 SFC_ASSERT(txq_entries <= sa->txq_max_entries);
165 SFC_ASSERT(txq_entries >= nb_tx_desc);
166 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc);
168 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf);
172 SFC_ASSERT(sw_index < sa->txq_count);
173 txq_info = &sa->txq_info[sw_index];
175 txq_info->entries = txq_entries;
177 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
178 evq_entries, socket_id, &evq);
183 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
189 txq->hw_index = sw_index;
192 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
193 SFC_TX_DEFAULT_FREE_THRESH;
194 txq->flags = tx_conf->txq_flags;
196 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
197 socket_id, &txq->mem);
201 memset(&info, 0, sizeof(info));
202 info.max_fill_level = txq_max_fill_level;
203 info.free_thresh = txq->free_thresh;
204 info.flags = tx_conf->txq_flags;
205 info.txq_entries = txq_info->entries;
206 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
207 info.txq_hw_ring = txq->mem.esm_base;
208 info.evq_entries = evq_entries;
209 info.evq_hw_ring = evq->mem.esm_base;
210 info.hw_index = txq->hw_index;
211 info.mem_bar = sa->mem_bar.esb_base;
213 rc = sa->dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
214 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
215 socket_id, &info, &txq->dp);
217 goto fail_dp_tx_qinit;
219 evq->dp_txq = txq->dp;
221 txq->state = SFC_TXQ_INITIALIZED;
223 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
228 sfc_dma_free(sa, &txq->mem);
231 txq_info->txq = NULL;
238 txq_info->entries = 0;
242 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
247 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
249 struct sfc_txq_info *txq_info;
252 sfc_log_init(sa, "TxQ = %u", sw_index);
254 SFC_ASSERT(sw_index < sa->txq_count);
255 txq_info = &sa->txq_info[sw_index];
258 SFC_ASSERT(txq != NULL);
259 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
261 sa->dp_tx->qdestroy(txq->dp);
264 txq_info->txq = NULL;
265 txq_info->entries = 0;
267 sfc_dma_free(sa, &txq->mem);
269 sfc_ev_qfini(txq->evq);
276 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
278 sfc_log_init(sa, "TxQ = %u", sw_index);
284 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
288 switch (txmode->mq_mode) {
292 sfc_err(sa, "Tx multi-queue mode %u not supported",
298 * These features are claimed to be i40e-specific,
299 * but it does make sense to double-check their absence
301 if (txmode->hw_vlan_reject_tagged) {
302 sfc_err(sa, "Rejecting tagged packets not supported");
306 if (txmode->hw_vlan_reject_untagged) {
307 sfc_err(sa, "Rejecting untagged packets not supported");
311 if (txmode->hw_vlan_insert_pvid) {
312 sfc_err(sa, "Port-based VLAN insertion not supported");
320 * Destroy excess queues that are no longer needed after reconfiguration
324 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues)
328 SFC_ASSERT(nb_tx_queues <= sa->txq_count);
330 sw_index = sa->txq_count;
331 while (--sw_index >= (int)nb_tx_queues) {
332 if (sa->txq_info[sw_index].txq != NULL)
333 sfc_tx_qfini(sa, sw_index);
336 sa->txq_count = nb_tx_queues;
340 sfc_tx_configure(struct sfc_adapter *sa)
342 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
343 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
344 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues;
347 sfc_log_init(sa, "nb_tx_queues=%u (old %u)",
348 nb_tx_queues, sa->txq_count);
351 * The datapath implementation assumes absence of boundary
352 * limits on Tx DMA descriptors. Addition of these checks on
353 * datapath would simply make the datapath slower.
355 if (encp->enc_tx_dma_desc_boundary != 0) {
357 goto fail_tx_dma_desc_boundary;
360 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
362 goto fail_check_mode;
364 if (nb_tx_queues == sa->txq_count)
367 if (sa->txq_info == NULL) {
368 sa->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues,
369 sizeof(sa->txq_info[0]), 0,
371 if (sa->txq_info == NULL)
372 goto fail_txqs_alloc;
374 struct sfc_txq_info *new_txq_info;
376 if (nb_tx_queues < sa->txq_count)
377 sfc_tx_fini_queues(sa, nb_tx_queues);
380 rte_realloc(sa->txq_info,
381 nb_tx_queues * sizeof(sa->txq_info[0]), 0);
382 if (new_txq_info == NULL && nb_tx_queues > 0)
383 goto fail_txqs_realloc;
385 sa->txq_info = new_txq_info;
386 if (nb_tx_queues > sa->txq_count)
387 memset(&sa->txq_info[sa->txq_count], 0,
388 (nb_tx_queues - sa->txq_count) *
389 sizeof(sa->txq_info[0]));
392 while (sa->txq_count < nb_tx_queues) {
393 rc = sfc_tx_qinit_info(sa, sa->txq_count);
395 goto fail_tx_qinit_info;
409 fail_tx_dma_desc_boundary:
410 sfc_log_init(sa, "failed (rc = %d)", rc);
415 sfc_tx_close(struct sfc_adapter *sa)
417 sfc_tx_fini_queues(sa, 0);
419 rte_free(sa->txq_info);
424 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
426 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
427 struct rte_eth_dev_data *dev_data;
428 struct sfc_txq_info *txq_info;
432 unsigned int desc_index;
435 sfc_log_init(sa, "TxQ = %u", sw_index);
437 SFC_ASSERT(sw_index < sa->txq_count);
438 txq_info = &sa->txq_info[sw_index];
442 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
446 rc = sfc_ev_qstart(evq, sfc_evq_index_by_txq_sw_index(sa, sw_index));
451 * It seems that DPDK has no controls regarding IPv4 offloads,
452 * hence, we always enable it here
454 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
455 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP)) {
456 flags = EFX_TXQ_CKSUM_IPV4;
458 if (encp->enc_tunnel_encapsulations_supported != 0)
459 flags |= EFX_TXQ_CKSUM_INNER_IPV4;
461 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
463 if (encp->enc_tunnel_encapsulations_supported != 0)
464 flags |= EFX_TXQ_CKSUM_INNER_IPV4 |
465 EFX_TXQ_CKSUM_INNER_TCPUDP;
468 flags |= EFX_TXQ_FATSOV2;
471 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
472 txq_info->entries, 0 /* not used on EF10 */,
474 &txq->common, &desc_index);
476 if (sa->tso && (rc == ENOSPC))
477 sfc_err(sa, "ran out of TSO contexts");
479 goto fail_tx_qcreate;
482 efx_tx_qenable(txq->common);
484 txq->state |= SFC_TXQ_STARTED;
486 rc = sa->dp_tx->qstart(txq->dp, evq->read_ptr, desc_index);
491 * It seems to be used by DPDK for debug purposes only ('rte_ether')
493 dev_data = sa->eth_dev->data;
494 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
499 txq->state = SFC_TXQ_INITIALIZED;
500 efx_tx_qdestroy(txq->common);
510 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
512 struct rte_eth_dev_data *dev_data;
513 struct sfc_txq_info *txq_info;
515 unsigned int retry_count;
516 unsigned int wait_count;
519 sfc_log_init(sa, "TxQ = %u", sw_index);
521 SFC_ASSERT(sw_index < sa->txq_count);
522 txq_info = &sa->txq_info[sw_index];
526 if (txq->state == SFC_TXQ_INITIALIZED)
529 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
531 sa->dp_tx->qstop(txq->dp, &txq->evq->read_ptr);
534 * Retry TX queue flushing in case of flush failed or
535 * timeout; in the worst case it can delay for 6 seconds
537 for (retry_count = 0;
538 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
539 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
541 rc = efx_tx_qflush(txq->common);
543 txq->state |= (rc == EALREADY) ?
544 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED;
549 * Wait for TX queue flush done or flush failed event at least
550 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
551 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
552 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
556 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
557 sfc_ev_qpoll(txq->evq);
558 } while ((txq->state & SFC_TXQ_FLUSHING) &&
559 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
561 if (txq->state & SFC_TXQ_FLUSHING)
562 sfc_err(sa, "TxQ %u flush timed out", sw_index);
564 if (txq->state & SFC_TXQ_FLUSHED)
565 sfc_info(sa, "TxQ %u flushed", sw_index);
568 sa->dp_tx->qreap(txq->dp);
570 txq->state = SFC_TXQ_INITIALIZED;
572 efx_tx_qdestroy(txq->common);
574 sfc_ev_qstop(txq->evq);
577 * It seems to be used by DPDK for debug purposes only ('rte_ether')
579 dev_data = sa->eth_dev->data;
580 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
584 sfc_tx_start(struct sfc_adapter *sa)
586 unsigned int sw_index;
589 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
592 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
593 sfc_warn(sa, "TSO support was unable to be restored");
598 rc = efx_tx_init(sa->nic);
600 goto fail_efx_tx_init;
602 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
603 if (!(sa->txq_info[sw_index].deferred_start) ||
604 sa->txq_info[sw_index].deferred_started) {
605 rc = sfc_tx_qstart(sa, sw_index);
614 while (sw_index-- > 0)
615 sfc_tx_qstop(sa, sw_index);
617 efx_tx_fini(sa->nic);
620 sfc_log_init(sa, "failed (rc = %d)", rc);
625 sfc_tx_stop(struct sfc_adapter *sa)
627 unsigned int sw_index;
629 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
631 sw_index = sa->txq_count;
632 while (sw_index-- > 0) {
633 if (sa->txq_info[sw_index].txq != NULL)
634 sfc_tx_qstop(sa, sw_index);
637 efx_tx_fini(sa->nic);
641 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
643 unsigned int completed;
645 sfc_ev_qpoll(txq->evq);
647 for (completed = txq->completed;
648 completed != txq->pending; completed++) {
649 struct sfc_efx_tx_sw_desc *txd;
651 txd = &txq->sw_ring[completed & txq->ptr_mask];
653 if (txd->mbuf != NULL) {
654 rte_pktmbuf_free(txd->mbuf);
659 txq->completed = completed;
663 * The function is used to insert or update VLAN tag;
664 * the firmware has state of the firmware tag to insert per TxQ
665 * (controlled by option descriptors), hence, if the tag of the
666 * packet to be sent is different from one remembered by the firmware,
667 * the function will update it
670 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
673 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
676 if (this_tag == txq->hw_vlan_tci)
680 * The expression inside SFC_ASSERT() is not desired to be checked in
681 * a non-debug build because it might be too expensive on the data path
683 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
685 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
688 txq->hw_vlan_tci = this_tag;
694 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
696 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
697 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
698 unsigned int added = txq->added;
699 unsigned int pushed = added;
700 unsigned int pkts_sent = 0;
701 efx_desc_t *pend = &txq->pend_desc[0];
702 const unsigned int hard_max_fill = txq->max_fill_level;
703 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
704 unsigned int fill_level = added - txq->completed;
707 struct rte_mbuf **pktp;
709 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
713 * If insufficient space for a single packet is present,
714 * we should reap; otherwise, we shouldn't do that all the time
715 * to avoid latency increase
717 reap_done = (fill_level > soft_max_fill);
720 sfc_efx_tx_reap(txq);
722 * Recalculate fill level since 'txq->completed'
723 * might have changed on reap
725 fill_level = added - txq->completed;
728 for (pkts_sent = 0, pktp = &tx_pkts[0];
729 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
730 pkts_sent++, pktp++) {
731 struct rte_mbuf *m_seg = *pktp;
732 size_t pkt_len = m_seg->pkt_len;
733 unsigned int pkt_descs = 0;
737 * Here VLAN TCI is expected to be zero in case if no
738 * DEV_TX_VLAN_OFFLOAD capability is advertised;
739 * if the calling app ignores the absence of
740 * DEV_TX_VLAN_OFFLOAD and pushes VLAN TCI, then
741 * TX_ERROR will occur
743 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
745 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
747 * We expect correct 'pkt->l[2, 3, 4]_len' values
748 * to be set correctly by the caller
750 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
751 &pkt_descs, &pkt_len) != 0) {
752 /* We may have reached this place for
753 * one of the following reasons:
755 * 1) Packet header length is greater
756 * than SFC_TSOH_STD_LEN
757 * 2) TCP header starts at more then
758 * 208 bytes into the frame
760 * We will deceive RTE saying that we have sent
761 * the packet, but we will actually drop it.
762 * Hence, we should revert 'pend' to the
763 * previous state (in case we have added
764 * VLAN descriptor) and start processing
765 * another one packet. But the original
766 * mbuf shouldn't be orphaned
770 rte_pktmbuf_free(*pktp);
776 * We've only added 2 FATSOv2 option descriptors
777 * and 1 descriptor for the linearized packet header.
778 * The outstanding work will be done in the same manner
779 * as for the usual non-TSO path
783 for (; m_seg != NULL; m_seg = m_seg->next) {
784 efsys_dma_addr_t next_frag;
787 seg_len = m_seg->data_len;
788 next_frag = rte_mbuf_data_iova(m_seg);
791 * If we've started TSO transaction few steps earlier,
792 * we'll skip packet header using an offset in the
793 * current segment (which has been set to the
794 * first one containing payload)
801 efsys_dma_addr_t frag_addr = next_frag;
805 * It is assumed here that there is no
806 * limitation on address boundary
807 * crossing by DMA descriptor.
809 frag_len = MIN(seg_len, txq->dma_desc_size_max);
810 next_frag += frag_len;
814 efx_tx_qdesc_dma_create(txq->common,
820 } while (seg_len != 0);
825 fill_level += pkt_descs;
826 if (unlikely(fill_level > hard_max_fill)) {
828 * Our estimation for maximum number of descriptors
829 * required to send a packet seems to be wrong.
830 * Try to reap (if we haven't yet).
833 sfc_efx_tx_reap(txq);
835 fill_level = added - txq->completed;
836 if (fill_level > hard_max_fill) {
846 /* Assign mbuf to the last used desc */
847 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
850 if (likely(pkts_sent > 0)) {
851 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
852 pend - &txq->pend_desc[0],
853 txq->completed, &txq->added);
856 if (likely(pushed != txq->added))
857 efx_tx_qpush(txq->common, txq->added, pushed);
860 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
862 sfc_efx_tx_reap(txq);
870 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
872 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
873 struct rte_eth_dev *eth_dev;
874 struct sfc_adapter *sa;
877 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
878 eth_dev = &rte_eth_devices[dpq->port_id];
880 sa = eth_dev->data->dev_private;
882 SFC_ASSERT(dpq->queue_id < sa->txq_count);
883 txq = sa->txq_info[dpq->queue_id].txq;
885 SFC_ASSERT(txq != NULL);
889 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings;
891 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc,
892 unsigned int *txq_entries,
893 unsigned int *evq_entries,
894 unsigned int *txq_max_fill_level)
896 *txq_entries = nb_tx_desc;
897 *evq_entries = nb_tx_desc;
898 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries);
902 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
904 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
905 const struct rte_pci_addr *pci_addr,
907 const struct sfc_dp_tx_qcreate_info *info,
908 struct sfc_dp_txq **dp_txqp)
910 struct sfc_efx_txq *txq;
911 struct sfc_txq *ctrl_txq;
915 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
916 RTE_CACHE_LINE_SIZE, socket_id);
920 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
923 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
924 EFX_TXQ_LIMIT(info->txq_entries),
925 sizeof(*txq->pend_desc), 0,
927 if (txq->pend_desc == NULL)
928 goto fail_pend_desc_alloc;
931 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
933 sizeof(*txq->sw_ring),
934 RTE_CACHE_LINE_SIZE, socket_id);
935 if (txq->sw_ring == NULL)
936 goto fail_sw_ring_alloc;
938 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
939 if (ctrl_txq->evq->sa->tso) {
940 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
941 info->txq_entries, socket_id);
943 goto fail_alloc_tsoh_objs;
946 txq->evq = ctrl_txq->evq;
947 txq->ptr_mask = info->txq_entries - 1;
948 txq->max_fill_level = info->max_fill_level;
949 txq->free_thresh = info->free_thresh;
950 txq->dma_desc_size_max = info->dma_desc_size_max;
955 fail_alloc_tsoh_objs:
956 rte_free(txq->sw_ring);
959 rte_free(txq->pend_desc);
961 fail_pend_desc_alloc:
968 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
970 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
972 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
974 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
975 rte_free(txq->sw_ring);
976 rte_free(txq->pend_desc);
980 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
982 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
983 __rte_unused unsigned int evq_read_ptr,
984 unsigned int txq_desc_index)
986 /* libefx-based datapath is specific to libefx-based PMD */
987 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
988 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
990 txq->common = ctrl_txq->common;
992 txq->pending = txq->completed = txq->added = txq_desc_index;
993 txq->hw_vlan_tci = 0;
995 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
1000 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
1002 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
1003 __rte_unused unsigned int *evq_read_ptr)
1005 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1007 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
1010 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
1012 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
1014 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1017 sfc_efx_tx_reap(txq);
1019 for (txds = 0; txds <= txq->ptr_mask; txds++) {
1020 if (txq->sw_ring[txds].mbuf != NULL) {
1021 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
1022 txq->sw_ring[txds].mbuf = NULL;
1026 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
1029 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status;
1031 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
1033 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1035 if (unlikely(offset > txq->ptr_mask))
1038 if (unlikely(offset >= txq->max_fill_level))
1039 return RTE_ETH_TX_DESC_UNAVAIL;
1042 * Poll EvQ to derive up-to-date 'txq->pending' figure;
1043 * it is required for the queue to be running, but the
1044 * check is omitted because API design assumes that it
1045 * is the duty of the caller to satisfy all conditions
1047 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) ==
1048 SFC_EFX_TXQ_FLAG_RUNNING);
1049 sfc_ev_qpoll(txq->evq);
1052 * Ring tail is 'txq->pending', and although descriptors
1053 * between 'txq->completed' and 'txq->pending' are still
1054 * in use by the driver, they should be reported as DONE
1056 if (unlikely(offset < (txq->added - txq->pending)))
1057 return RTE_ETH_TX_DESC_FULL;
1060 * There is no separate return value for unused descriptors;
1061 * the latter will be reported as DONE because genuine DONE
1062 * descriptors will be freed anyway in SW on the next burst
1064 return RTE_ETH_TX_DESC_DONE;
1067 struct sfc_dp_tx sfc_efx_tx = {
1069 .name = SFC_KVARG_DATAPATH_EFX,
1073 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
1074 SFC_DP_TX_FEAT_TSO |
1075 SFC_DP_TX_FEAT_MULTI_POOL |
1076 SFC_DP_TX_FEAT_REFCNT |
1077 SFC_DP_TX_FEAT_MULTI_SEG,
1078 .qsize_up_rings = sfc_efx_tx_qsize_up_rings,
1079 .qcreate = sfc_efx_tx_qcreate,
1080 .qdestroy = sfc_efx_tx_qdestroy,
1081 .qstart = sfc_efx_tx_qstart,
1082 .qstop = sfc_efx_tx_qstop,
1083 .qreap = sfc_efx_tx_qreap,
1084 .qdesc_status = sfc_efx_tx_qdesc_status,
1085 .pkt_burst = sfc_efx_xmit_pkts,