1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2016-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
11 #include "sfc_debug.h"
15 #include "sfc_tweak.h"
16 #include "sfc_kvargs.h"
19 * Maximum number of TX queue flush attempts in case of
20 * failure or flush timeout
22 #define SFC_TX_QFLUSH_ATTEMPTS (3)
25 * Time to wait between event queue polling attempts when waiting for TX
26 * queue flush done or flush failed events
28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
31 * Maximum number of event queue polling attempts when waiting for TX queue
32 * flush done or flush failed events; it defines TX queue flush attempt timeout
33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
38 sfc_txq_info_by_ethdev_qid(struct sfc_adapter_shared *sas,
39 sfc_ethdev_qid_t ethdev_qid)
41 sfc_sw_index_t sw_index;
43 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_txq_count);
44 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID);
46 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid);
47 return &sas->txq_info[sw_index];
51 sfc_tx_get_offload_mask(struct sfc_adapter *sa)
53 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
56 if (!encp->enc_hw_tx_insert_vlan_enabled)
57 no_caps |= DEV_TX_OFFLOAD_VLAN_INSERT;
59 if (!encp->enc_tunnel_encapsulations_supported)
60 no_caps |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
63 no_caps |= DEV_TX_OFFLOAD_TCP_TSO;
66 (encp->enc_tunnel_encapsulations_supported &
67 (1u << EFX_TUNNEL_PROTOCOL_VXLAN)) == 0)
68 no_caps |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
71 (encp->enc_tunnel_encapsulations_supported &
72 (1u << EFX_TUNNEL_PROTOCOL_GENEVE)) == 0)
73 no_caps |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
79 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa)
81 return sa->priv.dp_tx->dev_offload_capa & sfc_tx_get_offload_mask(sa);
85 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa)
87 return sa->priv.dp_tx->queue_offload_capa & sfc_tx_get_offload_mask(sa);
91 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level,
92 const struct rte_eth_txconf *tx_conf,
97 if (tx_conf->tx_rs_thresh != 0) {
98 sfc_err(sa, "RS bit in transmit descriptor is not supported");
102 if (tx_conf->tx_free_thresh > txq_max_fill_level) {
104 "TxQ free threshold too large: %u vs maximum %u",
105 tx_conf->tx_free_thresh, txq_max_fill_level);
109 if (tx_conf->tx_thresh.pthresh != 0 ||
110 tx_conf->tx_thresh.hthresh != 0 ||
111 tx_conf->tx_thresh.wthresh != 0) {
113 "prefetch/host/writeback thresholds are not supported");
116 /* We either perform both TCP and UDP offload, or no offload at all */
117 if (((offloads & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) !=
118 ((offloads & DEV_TX_OFFLOAD_UDP_CKSUM) == 0)) {
119 sfc_err(sa, "TCP and UDP offloads can't be set independently");
127 sfc_tx_qflush_done(struct sfc_txq_info *txq_info)
129 txq_info->state |= SFC_TXQ_FLUSHED;
130 txq_info->state &= ~SFC_TXQ_FLUSHING;
134 sfc_tx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index,
135 uint16_t nb_tx_desc, unsigned int socket_id,
136 const struct rte_eth_txconf *tx_conf)
138 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
139 sfc_ethdev_qid_t ethdev_qid;
140 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
141 unsigned int txq_entries;
142 unsigned int evq_entries;
143 unsigned int txq_max_fill_level;
144 struct sfc_txq_info *txq_info;
148 struct sfc_dp_tx_qcreate_info info;
150 struct sfc_dp_tx_hw_limits hw_limits;
152 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
154 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
156 memset(&hw_limits, 0, sizeof(hw_limits));
157 hw_limits.txq_max_entries = sa->txq_max_entries;
158 hw_limits.txq_min_entries = sa->txq_min_entries;
160 rc = sa->priv.dp_tx->qsize_up_rings(nb_tx_desc, &hw_limits,
161 &txq_entries, &evq_entries,
162 &txq_max_fill_level);
164 goto fail_size_up_rings;
165 SFC_ASSERT(txq_entries >= sa->txq_min_entries);
166 SFC_ASSERT(txq_entries <= sa->txq_max_entries);
167 SFC_ASSERT(txq_entries >= nb_tx_desc);
168 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc);
170 offloads = tx_conf->offloads;
171 /* Add device level Tx offloads if the queue is an ethdev Tx queue */
172 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
173 offloads |= sa->eth_dev->data->dev_conf.txmode.offloads;
175 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf, offloads);
179 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
180 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
182 txq_info->entries = txq_entries;
184 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
185 evq_entries, socket_id, &evq);
189 txq = &sa->txq_ctrl[sw_index];
190 txq->hw_index = sw_index;
192 txq_info->free_thresh =
193 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
194 SFC_TX_DEFAULT_FREE_THRESH;
195 txq_info->offloads = offloads;
197 rc = sfc_dma_alloc(sa, "txq", sw_index,
198 efx_txq_size(sa->nic, txq_info->entries),
199 socket_id, &txq->mem);
203 memset(&info, 0, sizeof(info));
204 info.max_fill_level = txq_max_fill_level;
205 info.free_thresh = txq_info->free_thresh;
206 info.offloads = offloads;
207 info.txq_entries = txq_info->entries;
208 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
209 info.txq_hw_ring = txq->mem.esm_base;
210 info.evq_entries = evq_entries;
211 info.evq_hw_ring = evq->mem.esm_base;
212 info.hw_index = txq->hw_index;
213 info.mem_bar = sa->mem_bar.esb_base;
214 info.vi_window_shift = encp->enc_vi_window_shift;
215 info.tso_tcp_header_offset_limit =
216 encp->enc_tx_tso_tcp_header_offset_limit;
217 info.tso_max_nb_header_descs =
218 RTE_MIN(encp->enc_tx_tso_max_header_ndescs,
219 (uint32_t)UINT16_MAX);
220 info.tso_max_header_len =
221 RTE_MIN(encp->enc_tx_tso_max_header_length,
222 (uint32_t)UINT16_MAX);
223 info.tso_max_nb_payload_descs =
224 RTE_MIN(encp->enc_tx_tso_max_payload_ndescs,
225 (uint32_t)UINT16_MAX);
226 info.tso_max_payload_len = encp->enc_tx_tso_max_payload_length;
227 info.tso_max_nb_outgoing_frames = encp->enc_tx_tso_max_nframes;
229 rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
230 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
231 socket_id, &info, &txq_info->dp);
233 goto fail_dp_tx_qinit;
235 evq->dp_txq = txq_info->dp;
237 txq_info->state = SFC_TXQ_INITIALIZED;
239 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
244 sfc_dma_free(sa, &txq->mem);
250 txq_info->entries = 0;
254 sfc_log_init(sa, "failed (TxQ = %d (internal %u), rc = %d)", ethdev_qid,
260 sfc_tx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
262 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
263 sfc_ethdev_qid_t ethdev_qid;
264 struct sfc_txq_info *txq_info;
267 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
269 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
271 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count);
272 if (ethdev_qid != SFC_ETHDEV_QID_INVALID)
273 sa->eth_dev->data->tx_queues[ethdev_qid] = NULL;
275 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index];
277 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
279 sa->priv.dp_tx->qdestroy(txq_info->dp);
282 txq_info->state &= ~SFC_TXQ_INITIALIZED;
283 txq_info->entries = 0;
285 txq = &sa->txq_ctrl[sw_index];
287 sfc_dma_free(sa, &txq->mem);
289 sfc_ev_qfini(txq->evq);
294 sfc_tx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
296 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
297 sfc_ethdev_qid_t ethdev_qid;
299 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
301 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
307 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
311 switch (txmode->mq_mode) {
315 sfc_err(sa, "Tx multi-queue mode %u not supported",
321 * These features are claimed to be i40e-specific,
322 * but it does make sense to double-check their absence
324 if (txmode->hw_vlan_reject_tagged) {
325 sfc_err(sa, "Rejecting tagged packets not supported");
329 if (txmode->hw_vlan_reject_untagged) {
330 sfc_err(sa, "Rejecting untagged packets not supported");
334 if (txmode->hw_vlan_insert_pvid) {
335 sfc_err(sa, "Port-based VLAN insertion not supported");
343 * Destroy excess queues that are no longer needed after reconfiguration
347 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues)
349 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
350 sfc_sw_index_t sw_index;
351 sfc_ethdev_qid_t ethdev_qid;
353 SFC_ASSERT(nb_tx_queues <= sas->ethdev_txq_count);
356 * Finalize only ethdev queues since other ones are finalized only
357 * on device close and they may require additional deinitializaton.
359 ethdev_qid = sas->ethdev_txq_count;
360 while (--ethdev_qid >= (int)nb_tx_queues) {
361 struct sfc_txq_info *txq_info;
363 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid);
364 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid);
365 if (txq_info->state & SFC_TXQ_INITIALIZED)
366 sfc_tx_qfini(sa, sw_index);
369 sas->ethdev_txq_count = nb_tx_queues;
373 sfc_tx_configure(struct sfc_adapter *sa)
375 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
376 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
377 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
378 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues;
379 const unsigned int nb_rsvd_tx_queues = sfc_nb_txq_reserved(sas);
380 const unsigned int nb_txq_total = nb_tx_queues + nb_rsvd_tx_queues;
383 sfc_log_init(sa, "nb_tx_queues=%u (old %u)",
384 nb_tx_queues, sas->ethdev_txq_count);
387 * The datapath implementation assumes absence of boundary
388 * limits on Tx DMA descriptors. Addition of these checks on
389 * datapath would simply make the datapath slower.
391 if (encp->enc_tx_dma_desc_boundary != 0) {
393 goto fail_tx_dma_desc_boundary;
396 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
398 goto fail_check_mode;
400 if (nb_txq_total == sas->txq_count)
403 if (sas->txq_info == NULL) {
404 sas->txq_info = rte_calloc_socket("sfc-txqs", nb_txq_total,
405 sizeof(sas->txq_info[0]), 0,
407 if (sas->txq_info == NULL)
408 goto fail_txqs_alloc;
411 * Allocate primary process only TxQ control from heap
412 * since it should not be shared.
415 sa->txq_ctrl = calloc(nb_txq_total, sizeof(sa->txq_ctrl[0]));
416 if (sa->txq_ctrl == NULL)
417 goto fail_txqs_ctrl_alloc;
419 struct sfc_txq_info *new_txq_info;
420 struct sfc_txq *new_txq_ctrl;
422 if (nb_tx_queues < sas->ethdev_txq_count)
423 sfc_tx_fini_queues(sa, nb_tx_queues);
426 rte_realloc(sas->txq_info,
427 nb_txq_total * sizeof(sas->txq_info[0]), 0);
428 if (new_txq_info == NULL && nb_txq_total > 0)
429 goto fail_txqs_realloc;
431 new_txq_ctrl = realloc(sa->txq_ctrl,
432 nb_txq_total * sizeof(sa->txq_ctrl[0]));
433 if (new_txq_ctrl == NULL && nb_txq_total > 0)
434 goto fail_txqs_ctrl_realloc;
436 sas->txq_info = new_txq_info;
437 sa->txq_ctrl = new_txq_ctrl;
438 if (nb_txq_total > sas->txq_count) {
439 memset(&sas->txq_info[sas->txq_count], 0,
440 (nb_txq_total - sas->txq_count) *
441 sizeof(sas->txq_info[0]));
442 memset(&sa->txq_ctrl[sas->txq_count], 0,
443 (nb_txq_total - sas->txq_count) *
444 sizeof(sa->txq_ctrl[0]));
448 while (sas->ethdev_txq_count < nb_tx_queues) {
449 sfc_sw_index_t sw_index;
451 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas,
452 sas->ethdev_txq_count);
453 rc = sfc_tx_qinit_info(sa, sw_index);
455 goto fail_tx_qinit_info;
457 sas->ethdev_txq_count++;
460 /* TODO: initialize reserved queues when supported. */
461 sas->txq_count = sas->ethdev_txq_count + nb_rsvd_tx_queues;
467 fail_txqs_ctrl_realloc:
469 fail_txqs_ctrl_alloc:
474 fail_tx_dma_desc_boundary:
475 sfc_log_init(sa, "failed (rc = %d)", rc);
480 sfc_tx_close(struct sfc_adapter *sa)
482 sfc_tx_fini_queues(sa, 0);
487 rte_free(sfc_sa2shared(sa)->txq_info);
488 sfc_sa2shared(sa)->txq_info = NULL;
492 sfc_tx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
494 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
495 sfc_ethdev_qid_t ethdev_qid;
496 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) |
497 sfc_tx_get_queue_offload_caps(sa);
498 struct sfc_txq_info *txq_info;
502 unsigned int desc_index;
505 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
507 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
509 SFC_ASSERT(sw_index < sas->txq_count);
510 txq_info = &sas->txq_info[sw_index];
512 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED);
514 txq = &sa->txq_ctrl[sw_index];
517 rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_txq_sw_index(sa, sw_index));
521 if (txq_info->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
522 flags |= EFX_TXQ_CKSUM_IPV4;
524 if (txq_info->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
525 flags |= EFX_TXQ_CKSUM_INNER_IPV4;
527 if ((txq_info->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
528 (txq_info->offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
529 flags |= EFX_TXQ_CKSUM_TCPUDP;
531 if (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)
532 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP;
535 if (txq_info->offloads & (DEV_TX_OFFLOAD_TCP_TSO |
536 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
537 DEV_TX_OFFLOAD_GENEVE_TNL_TSO))
538 flags |= EFX_TXQ_FATSOV2;
540 rc = efx_tx_qcreate(sa->nic, txq->hw_index, 0, &txq->mem,
541 txq_info->entries, 0 /* not used on EF10 */,
543 &txq->common, &desc_index);
545 if (sa->tso && (rc == ENOSPC))
546 sfc_err(sa, "ran out of TSO contexts");
548 goto fail_tx_qcreate;
551 efx_tx_qenable(txq->common);
553 txq_info->state |= SFC_TXQ_STARTED;
555 rc = sa->priv.dp_tx->qstart(txq_info->dp, evq->read_ptr, desc_index);
559 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) {
560 struct rte_eth_dev_data *dev_data;
563 * It sems to be used by DPDK for debug purposes only
566 dev_data = sa->eth_dev->data;
567 dev_data->tx_queue_state[ethdev_qid] =
568 RTE_ETH_QUEUE_STATE_STARTED;
574 txq_info->state = SFC_TXQ_INITIALIZED;
575 efx_tx_qdestroy(txq->common);
585 sfc_tx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index)
587 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
588 sfc_ethdev_qid_t ethdev_qid;
589 struct sfc_txq_info *txq_info;
591 unsigned int retry_count;
592 unsigned int wait_count;
595 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index);
597 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index);
599 SFC_ASSERT(sw_index < sas->txq_count);
600 txq_info = &sas->txq_info[sw_index];
602 if (txq_info->state == SFC_TXQ_INITIALIZED)
605 SFC_ASSERT(txq_info->state & SFC_TXQ_STARTED);
607 txq = &sa->txq_ctrl[sw_index];
608 sa->priv.dp_tx->qstop(txq_info->dp, &txq->evq->read_ptr);
611 * Retry TX queue flushing in case of flush failed or
612 * timeout; in the worst case it can delay for 6 seconds
614 for (retry_count = 0;
615 ((txq_info->state & SFC_TXQ_FLUSHED) == 0) &&
616 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
618 rc = efx_tx_qflush(txq->common);
620 txq_info->state |= (rc == EALREADY) ?
621 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED;
626 * Wait for TX queue flush done or flush failed event at least
627 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
628 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
629 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
633 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
634 sfc_ev_qpoll(txq->evq);
635 } while ((txq_info->state & SFC_TXQ_FLUSHING) &&
636 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
638 if (txq_info->state & SFC_TXQ_FLUSHING)
639 sfc_err(sa, "TxQ %d (internal %u) flush timed out",
640 ethdev_qid, sw_index);
642 if (txq_info->state & SFC_TXQ_FLUSHED)
643 sfc_notice(sa, "TxQ %d (internal %u) flushed",
644 ethdev_qid, sw_index);
647 sa->priv.dp_tx->qreap(txq_info->dp);
649 txq_info->state = SFC_TXQ_INITIALIZED;
651 efx_tx_qdestroy(txq->common);
653 sfc_ev_qstop(txq->evq);
655 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) {
656 struct rte_eth_dev_data *dev_data;
659 * It seems to be used by DPDK for debug purposes only
662 dev_data = sa->eth_dev->data;
663 dev_data->tx_queue_state[ethdev_qid] =
664 RTE_ETH_QUEUE_STATE_STOPPED;
669 sfc_tx_start(struct sfc_adapter *sa)
671 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
672 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
673 sfc_sw_index_t sw_index;
676 sfc_log_init(sa, "txq_count = %u (internal %u)",
677 sas->ethdev_txq_count, sas->txq_count);
680 if (!encp->enc_fw_assisted_tso_v2_enabled &&
681 !encp->enc_tso_v3_enabled) {
682 sfc_warn(sa, "TSO support was unable to be restored");
684 sa->tso_encap = B_FALSE;
688 if (sa->tso_encap && !encp->enc_fw_assisted_tso_v2_encap_enabled &&
689 !encp->enc_tso_v3_enabled) {
690 sfc_warn(sa, "Encapsulated TSO support was unable to be restored");
691 sa->tso_encap = B_FALSE;
694 rc = efx_tx_init(sa->nic);
696 goto fail_efx_tx_init;
698 for (sw_index = 0; sw_index < sas->txq_count; ++sw_index) {
699 if (sas->txq_info[sw_index].state == SFC_TXQ_INITIALIZED &&
700 (!(sas->txq_info[sw_index].deferred_start) ||
701 sas->txq_info[sw_index].deferred_started)) {
702 rc = sfc_tx_qstart(sa, sw_index);
711 while (sw_index-- > 0)
712 sfc_tx_qstop(sa, sw_index);
714 efx_tx_fini(sa->nic);
717 sfc_log_init(sa, "failed (rc = %d)", rc);
722 sfc_tx_stop(struct sfc_adapter *sa)
724 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa);
725 sfc_sw_index_t sw_index;
727 sfc_log_init(sa, "txq_count = %u (internal %u)",
728 sas->ethdev_txq_count, sas->txq_count);
730 sw_index = sas->txq_count;
731 while (sw_index-- > 0) {
732 if (sas->txq_info[sw_index].state & SFC_TXQ_STARTED)
733 sfc_tx_qstop(sa, sw_index);
736 efx_tx_fini(sa->nic);
740 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
742 unsigned int completed;
744 sfc_ev_qpoll(txq->evq);
746 for (completed = txq->completed;
747 completed != txq->pending; completed++) {
748 struct sfc_efx_tx_sw_desc *txd;
750 txd = &txq->sw_ring[completed & txq->ptr_mask];
752 if (txd->mbuf != NULL) {
753 rte_pktmbuf_free(txd->mbuf);
758 txq->completed = completed;
762 * The function is used to insert or update VLAN tag;
763 * the firmware has state of the firmware tag to insert per TxQ
764 * (controlled by option descriptors), hence, if the tag of the
765 * packet to be sent is different from one remembered by the firmware,
766 * the function will update it
769 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
772 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
775 if (this_tag == txq->hw_vlan_tci)
779 * The expression inside SFC_ASSERT() is not desired to be checked in
780 * a non-debug build because it might be too expensive on the data path
782 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
784 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
787 txq->hw_vlan_tci = this_tag;
793 sfc_efx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
796 struct sfc_dp_txq *dp_txq = tx_queue;
797 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
798 const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->evq->sa->nic);
801 for (i = 0; i < nb_pkts; i++) {
805 * EFX Tx datapath may require extra VLAN descriptor if VLAN
806 * insertion offload is requested regardless the offload
807 * requested/supported.
809 ret = sfc_dp_tx_prepare_pkt(tx_pkts[i], 0, SFC_TSOH_STD_LEN,
810 encp->enc_tx_tso_tcp_header_offset_limit,
811 txq->max_fill_level, EFX_TX_FATSOV2_OPT_NDESCS,
813 if (unlikely(ret != 0)) {
823 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
825 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
826 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
827 unsigned int added = txq->added;
828 unsigned int pushed = added;
829 unsigned int pkts_sent = 0;
830 efx_desc_t *pend = &txq->pend_desc[0];
831 const unsigned int hard_max_fill = txq->max_fill_level;
832 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
833 unsigned int fill_level = added - txq->completed;
836 struct rte_mbuf **pktp;
838 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
842 * If insufficient space for a single packet is present,
843 * we should reap; otherwise, we shouldn't do that all the time
844 * to avoid latency increase
846 reap_done = (fill_level > soft_max_fill);
849 sfc_efx_tx_reap(txq);
851 * Recalculate fill level since 'txq->completed'
852 * might have changed on reap
854 fill_level = added - txq->completed;
857 for (pkts_sent = 0, pktp = &tx_pkts[0];
858 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
859 pkts_sent++, pktp++) {
860 uint16_t hw_vlan_tci_prev = txq->hw_vlan_tci;
861 struct rte_mbuf *m_seg = *pktp;
862 size_t pkt_len = m_seg->pkt_len;
863 unsigned int pkt_descs = 0;
867 * Here VLAN TCI is expected to be zero in case if no
868 * DEV_TX_OFFLOAD_VLAN_INSERT capability is advertised;
869 * if the calling app ignores the absence of
870 * DEV_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then
871 * TX_ERROR will occur
873 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
875 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
877 * We expect correct 'pkt->l[2, 3, 4]_len' values
878 * to be set correctly by the caller
880 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
881 &pkt_descs, &pkt_len) != 0) {
882 /* We may have reached this place if packet
883 * header linearization is needed but the
884 * header length is greater than
887 * We will deceive RTE saying that we have sent
888 * the packet, but we will actually drop it.
889 * Hence, we should revert 'pend' to the
890 * previous state (in case we have added
891 * VLAN descriptor) and start processing
892 * another one packet. But the original
893 * mbuf shouldn't be orphaned
896 txq->hw_vlan_tci = hw_vlan_tci_prev;
898 rte_pktmbuf_free(*pktp);
904 * We've only added 2 FATSOv2 option descriptors
905 * and 1 descriptor for the linearized packet header.
906 * The outstanding work will be done in the same manner
907 * as for the usual non-TSO path
911 for (; m_seg != NULL; m_seg = m_seg->next) {
912 efsys_dma_addr_t next_frag;
915 seg_len = m_seg->data_len;
916 next_frag = rte_mbuf_data_iova(m_seg);
919 * If we've started TSO transaction few steps earlier,
920 * we'll skip packet header using an offset in the
921 * current segment (which has been set to the
922 * first one containing payload)
929 efsys_dma_addr_t frag_addr = next_frag;
933 * It is assumed here that there is no
934 * limitation on address boundary
935 * crossing by DMA descriptor.
937 frag_len = MIN(seg_len, txq->dma_desc_size_max);
938 next_frag += frag_len;
942 efx_tx_qdesc_dma_create(txq->common,
948 } while (seg_len != 0);
953 fill_level += pkt_descs;
954 if (unlikely(fill_level > hard_max_fill)) {
956 * Our estimation for maximum number of descriptors
957 * required to send a packet seems to be wrong.
958 * Try to reap (if we haven't yet).
961 sfc_efx_tx_reap(txq);
963 fill_level = added - txq->completed;
964 if (fill_level > hard_max_fill) {
966 txq->hw_vlan_tci = hw_vlan_tci_prev;
971 txq->hw_vlan_tci = hw_vlan_tci_prev;
976 /* Assign mbuf to the last used desc */
977 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
980 if (likely(pkts_sent > 0)) {
981 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
982 pend - &txq->pend_desc[0],
983 txq->completed, &txq->added);
986 if (likely(pushed != txq->added)) {
987 efx_tx_qpush(txq->common, txq->added, pushed);
988 txq->dp.dpq.tx_dbells++;
992 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
994 sfc_efx_tx_reap(txq);
1001 const struct sfc_dp_tx *
1002 sfc_dp_tx_by_dp_txq(const struct sfc_dp_txq *dp_txq)
1004 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
1005 struct rte_eth_dev *eth_dev;
1006 struct sfc_adapter_priv *sap;
1008 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
1009 eth_dev = &rte_eth_devices[dpq->port_id];
1011 sap = sfc_adapter_priv_by_eth_dev(eth_dev);
1016 struct sfc_txq_info *
1017 sfc_txq_info_by_dp_txq(const struct sfc_dp_txq *dp_txq)
1019 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
1020 struct rte_eth_dev *eth_dev;
1021 struct sfc_adapter_shared *sas;
1023 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
1024 eth_dev = &rte_eth_devices[dpq->port_id];
1026 sas = sfc_adapter_shared_by_eth_dev(eth_dev);
1028 SFC_ASSERT(dpq->queue_id < sas->txq_count);
1029 return &sas->txq_info[dpq->queue_id];
1033 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
1035 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
1036 struct rte_eth_dev *eth_dev;
1037 struct sfc_adapter *sa;
1039 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
1040 eth_dev = &rte_eth_devices[dpq->port_id];
1042 sa = sfc_adapter_by_eth_dev(eth_dev);
1044 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->txq_count);
1045 return &sa->txq_ctrl[dpq->queue_id];
1048 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings;
1050 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc,
1051 __rte_unused struct sfc_dp_tx_hw_limits *limits,
1052 unsigned int *txq_entries,
1053 unsigned int *evq_entries,
1054 unsigned int *txq_max_fill_level)
1056 *txq_entries = nb_tx_desc;
1057 *evq_entries = nb_tx_desc;
1058 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries);
1062 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
1064 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
1065 const struct rte_pci_addr *pci_addr,
1067 const struct sfc_dp_tx_qcreate_info *info,
1068 struct sfc_dp_txq **dp_txqp)
1070 struct sfc_efx_txq *txq;
1071 struct sfc_txq *ctrl_txq;
1075 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
1076 RTE_CACHE_LINE_SIZE, socket_id);
1078 goto fail_txq_alloc;
1080 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
1083 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
1084 EFX_TXQ_LIMIT(info->txq_entries),
1085 sizeof(*txq->pend_desc), 0,
1087 if (txq->pend_desc == NULL)
1088 goto fail_pend_desc_alloc;
1091 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
1093 sizeof(*txq->sw_ring),
1094 RTE_CACHE_LINE_SIZE, socket_id);
1095 if (txq->sw_ring == NULL)
1096 goto fail_sw_ring_alloc;
1098 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
1099 if (ctrl_txq->evq->sa->tso) {
1100 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
1101 info->txq_entries, socket_id);
1103 goto fail_alloc_tsoh_objs;
1106 txq->evq = ctrl_txq->evq;
1107 txq->ptr_mask = info->txq_entries - 1;
1108 txq->max_fill_level = info->max_fill_level;
1109 txq->free_thresh = info->free_thresh;
1110 txq->dma_desc_size_max = info->dma_desc_size_max;
1112 *dp_txqp = &txq->dp;
1115 fail_alloc_tsoh_objs:
1116 rte_free(txq->sw_ring);
1119 rte_free(txq->pend_desc);
1121 fail_pend_desc_alloc:
1128 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
1130 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
1132 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1134 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
1135 rte_free(txq->sw_ring);
1136 rte_free(txq->pend_desc);
1140 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
1142 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
1143 __rte_unused unsigned int evq_read_ptr,
1144 unsigned int txq_desc_index)
1146 /* libefx-based datapath is specific to libefx-based PMD */
1147 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1148 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
1150 txq->common = ctrl_txq->common;
1152 txq->pending = txq->completed = txq->added = txq_desc_index;
1153 txq->hw_vlan_tci = 0;
1155 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
1160 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
1162 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
1163 __rte_unused unsigned int *evq_read_ptr)
1165 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1167 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
1170 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
1172 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
1174 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1177 sfc_efx_tx_reap(txq);
1179 for (txds = 0; txds <= txq->ptr_mask; txds++) {
1180 if (txq->sw_ring[txds].mbuf != NULL) {
1181 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
1182 txq->sw_ring[txds].mbuf = NULL;
1186 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
1189 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status;
1191 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
1193 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1195 if (unlikely(offset > txq->ptr_mask))
1198 if (unlikely(offset >= txq->max_fill_level))
1199 return RTE_ETH_TX_DESC_UNAVAIL;
1202 * Poll EvQ to derive up-to-date 'txq->pending' figure;
1203 * it is required for the queue to be running, but the
1204 * check is omitted because API design assumes that it
1205 * is the duty of the caller to satisfy all conditions
1207 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) ==
1208 SFC_EFX_TXQ_FLAG_RUNNING);
1209 sfc_ev_qpoll(txq->evq);
1212 * Ring tail is 'txq->pending', and although descriptors
1213 * between 'txq->completed' and 'txq->pending' are still
1214 * in use by the driver, they should be reported as DONE
1216 if (unlikely(offset < (txq->added - txq->pending)))
1217 return RTE_ETH_TX_DESC_FULL;
1220 * There is no separate return value for unused descriptors;
1221 * the latter will be reported as DONE because genuine DONE
1222 * descriptors will be freed anyway in SW on the next burst
1224 return RTE_ETH_TX_DESC_DONE;
1227 struct sfc_dp_tx sfc_efx_tx = {
1229 .name = SFC_KVARG_DATAPATH_EFX,
1231 .hw_fw_caps = SFC_DP_HW_FW_CAP_TX_EFX,
1234 .dev_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1235 DEV_TX_OFFLOAD_MULTI_SEGS,
1236 .queue_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1237 DEV_TX_OFFLOAD_UDP_CKSUM |
1238 DEV_TX_OFFLOAD_TCP_CKSUM |
1239 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1240 DEV_TX_OFFLOAD_TCP_TSO,
1241 .qsize_up_rings = sfc_efx_tx_qsize_up_rings,
1242 .qcreate = sfc_efx_tx_qcreate,
1243 .qdestroy = sfc_efx_tx_qdestroy,
1244 .qstart = sfc_efx_tx_qstart,
1245 .qstop = sfc_efx_tx_qstop,
1246 .qreap = sfc_efx_tx_qreap,
1247 .qdesc_status = sfc_efx_tx_qdesc_status,
1248 .pkt_prepare = sfc_efx_prepare_pkts,
1249 .pkt_burst = sfc_efx_xmit_pkts,