4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "sfc_debug.h"
37 #include "sfc_tweak.h"
38 #include "sfc_kvargs.h"
41 * Maximum number of TX queue flush attempts in case of
42 * failure or flush timeout
44 #define SFC_TX_QFLUSH_ATTEMPTS (3)
47 * Time to wait between event queue polling attempts when waiting for TX
48 * queue flush done or flush failed events
50 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
53 * Maximum number of event queue polling attempts when waiting for TX queue
54 * flush done or flush failed events; it defines TX queue flush attempt timeout
55 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
57 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
60 sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc,
61 const struct rte_eth_txconf *tx_conf)
63 unsigned int flags = tx_conf->txq_flags;
64 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
67 if (tx_conf->tx_rs_thresh != 0) {
68 sfc_err(sa, "RS bit in transmit descriptor is not supported");
72 if (tx_conf->tx_free_thresh > EFX_TXQ_LIMIT(nb_tx_desc)) {
74 "TxQ free threshold too large: %u vs maximum %u",
75 tx_conf->tx_free_thresh, EFX_TXQ_LIMIT(nb_tx_desc));
79 if (tx_conf->tx_thresh.pthresh != 0 ||
80 tx_conf->tx_thresh.hthresh != 0 ||
81 tx_conf->tx_thresh.wthresh != 0) {
83 "prefetch/host/writeback thresholds are not supported");
86 if (((flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) &&
87 (~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG)) {
88 sfc_err(sa, "Multi-segment is not supported by %s datapath",
93 if (((flags & ETH_TXQ_FLAGS_NOMULTMEMP) == 0) &&
94 (~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_POOL)) {
95 sfc_err(sa, "multi-mempool is not supported by %s datapath",
100 if (((flags & ETH_TXQ_FLAGS_NOREFCOUNT) == 0) &&
101 (~sa->dp_tx->features & SFC_DP_TX_FEAT_REFCNT)) {
103 "mbuf reference counters are neglected by %s datapath",
108 if ((flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
109 if (!encp->enc_hw_tx_insert_vlan_enabled) {
110 sfc_err(sa, "VLAN offload is not supported");
112 } else if (~sa->dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) {
114 "VLAN offload is not supported by %s datapath",
120 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
121 sfc_err(sa, "SCTP offload is not supported");
125 /* We either perform both TCP and UDP offload, or no offload at all */
126 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
127 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
128 sfc_err(sa, "TCP and UDP offloads can't be set independently");
136 sfc_tx_qflush_done(struct sfc_txq *txq)
138 txq->state |= SFC_TXQ_FLUSHED;
139 txq->state &= ~SFC_TXQ_FLUSHING;
143 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
144 uint16_t nb_tx_desc, unsigned int socket_id,
145 const struct rte_eth_txconf *tx_conf)
147 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
148 struct sfc_txq_info *txq_info;
152 struct sfc_dp_tx_qcreate_info info;
154 sfc_log_init(sa, "TxQ = %u", sw_index);
156 rc = sfc_tx_qcheck_conf(sa, nb_tx_desc, tx_conf);
160 SFC_ASSERT(sw_index < sa->txq_count);
161 txq_info = &sa->txq_info[sw_index];
163 SFC_ASSERT(nb_tx_desc <= sa->txq_max_entries);
164 txq_info->entries = nb_tx_desc;
166 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
167 txq_info->entries, socket_id, &evq);
172 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
178 txq->hw_index = sw_index;
181 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
182 SFC_TX_DEFAULT_FREE_THRESH;
183 txq->flags = tx_conf->txq_flags;
185 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
186 socket_id, &txq->mem);
190 memset(&info, 0, sizeof(info));
191 info.free_thresh = txq->free_thresh;
192 info.flags = tx_conf->txq_flags;
193 info.txq_entries = txq_info->entries;
194 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
195 info.txq_hw_ring = txq->mem.esm_base;
196 info.evq_entries = txq_info->entries;
197 info.evq_hw_ring = evq->mem.esm_base;
198 info.hw_index = txq->hw_index;
199 info.mem_bar = sa->mem_bar.esb_base;
201 rc = sa->dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
202 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
203 socket_id, &info, &txq->dp);
205 goto fail_dp_tx_qinit;
207 evq->dp_txq = txq->dp;
209 txq->state = SFC_TXQ_INITIALIZED;
211 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
216 sfc_dma_free(sa, &txq->mem);
219 txq_info->txq = NULL;
226 txq_info->entries = 0;
229 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
234 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
236 struct sfc_txq_info *txq_info;
239 sfc_log_init(sa, "TxQ = %u", sw_index);
241 SFC_ASSERT(sw_index < sa->txq_count);
242 txq_info = &sa->txq_info[sw_index];
245 SFC_ASSERT(txq != NULL);
246 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
248 sa->dp_tx->qdestroy(txq->dp);
251 txq_info->txq = NULL;
252 txq_info->entries = 0;
254 sfc_dma_free(sa, &txq->mem);
256 sfc_ev_qfini(txq->evq);
263 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
265 sfc_log_init(sa, "TxQ = %u", sw_index);
271 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
275 switch (txmode->mq_mode) {
279 sfc_err(sa, "Tx multi-queue mode %u not supported",
285 * These features are claimed to be i40e-specific,
286 * but it does make sense to double-check their absence
288 if (txmode->hw_vlan_reject_tagged) {
289 sfc_err(sa, "Rejecting tagged packets not supported");
293 if (txmode->hw_vlan_reject_untagged) {
294 sfc_err(sa, "Rejecting untagged packets not supported");
298 if (txmode->hw_vlan_insert_pvid) {
299 sfc_err(sa, "Port-based VLAN insertion not supported");
307 * Destroy excess queues that are no longer needed after reconfiguration
311 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues)
315 SFC_ASSERT(nb_tx_queues <= sa->txq_count);
317 sw_index = sa->txq_count;
318 while (--sw_index >= (int)nb_tx_queues) {
319 if (sa->txq_info[sw_index].txq != NULL)
320 sfc_tx_qfini(sa, sw_index);
323 sa->txq_count = nb_tx_queues;
327 sfc_tx_configure(struct sfc_adapter *sa)
329 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
330 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
331 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues;
334 sfc_log_init(sa, "nb_tx_queues=%u (old %u)",
335 nb_tx_queues, sa->txq_count);
338 * The datapath implementation assumes absence of boundary
339 * limits on Tx DMA descriptors. Addition of these checks on
340 * datapath would simply make the datapath slower.
342 if (encp->enc_tx_dma_desc_boundary != 0) {
344 goto fail_tx_dma_desc_boundary;
347 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
349 goto fail_check_mode;
351 if (nb_tx_queues == sa->txq_count)
354 if (sa->txq_info == NULL) {
355 sa->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues,
356 sizeof(sa->txq_info[0]), 0,
358 if (sa->txq_info == NULL)
359 goto fail_txqs_alloc;
361 struct sfc_txq_info *new_txq_info;
363 if (nb_tx_queues < sa->txq_count)
364 sfc_tx_fini_queues(sa, nb_tx_queues);
367 rte_realloc(sa->txq_info,
368 nb_tx_queues * sizeof(sa->txq_info[0]), 0);
369 if (new_txq_info == NULL && nb_tx_queues > 0)
370 goto fail_txqs_realloc;
372 sa->txq_info = new_txq_info;
373 if (nb_tx_queues > sa->txq_count)
374 memset(&sa->txq_info[sa->txq_count], 0,
375 (nb_tx_queues - sa->txq_count) *
376 sizeof(sa->txq_info[0]));
379 while (sa->txq_count < nb_tx_queues) {
380 rc = sfc_tx_qinit_info(sa, sa->txq_count);
382 goto fail_tx_qinit_info;
396 fail_tx_dma_desc_boundary:
397 sfc_log_init(sa, "failed (rc = %d)", rc);
402 sfc_tx_close(struct sfc_adapter *sa)
404 sfc_tx_fini_queues(sa, 0);
406 rte_free(sa->txq_info);
411 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
413 struct rte_eth_dev_data *dev_data;
414 struct sfc_txq_info *txq_info;
418 unsigned int desc_index;
421 sfc_log_init(sa, "TxQ = %u", sw_index);
423 SFC_ASSERT(sw_index < sa->txq_count);
424 txq_info = &sa->txq_info[sw_index];
428 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
432 rc = sfc_ev_qstart(evq, sfc_evq_index_by_txq_sw_index(sa, sw_index));
437 * It seems that DPDK has no controls regarding IPv4 offloads,
438 * hence, we always enable it here
440 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
441 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP)) {
442 flags = EFX_TXQ_CKSUM_IPV4;
444 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
447 flags |= EFX_TXQ_FATSOV2;
450 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
451 txq_info->entries, 0 /* not used on EF10 */,
453 &txq->common, &desc_index);
455 if (sa->tso && (rc == ENOSPC))
456 sfc_err(sa, "ran out of TSO contexts");
458 goto fail_tx_qcreate;
461 efx_tx_qenable(txq->common);
463 txq->state |= SFC_TXQ_STARTED;
465 rc = sa->dp_tx->qstart(txq->dp, evq->read_ptr, desc_index);
470 * It seems to be used by DPDK for debug purposes only ('rte_ether')
472 dev_data = sa->eth_dev->data;
473 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
478 txq->state = SFC_TXQ_INITIALIZED;
479 efx_tx_qdestroy(txq->common);
489 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
491 struct rte_eth_dev_data *dev_data;
492 struct sfc_txq_info *txq_info;
494 unsigned int retry_count;
495 unsigned int wait_count;
498 sfc_log_init(sa, "TxQ = %u", sw_index);
500 SFC_ASSERT(sw_index < sa->txq_count);
501 txq_info = &sa->txq_info[sw_index];
505 if (txq->state == SFC_TXQ_INITIALIZED)
508 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
510 sa->dp_tx->qstop(txq->dp, &txq->evq->read_ptr);
513 * Retry TX queue flushing in case of flush failed or
514 * timeout; in the worst case it can delay for 6 seconds
516 for (retry_count = 0;
517 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
518 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
520 rc = efx_tx_qflush(txq->common);
522 txq->state |= (rc == EALREADY) ?
523 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED;
528 * Wait for TX queue flush done or flush failed event at least
529 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
530 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
531 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
535 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
536 sfc_ev_qpoll(txq->evq);
537 } while ((txq->state & SFC_TXQ_FLUSHING) &&
538 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
540 if (txq->state & SFC_TXQ_FLUSHING)
541 sfc_err(sa, "TxQ %u flush timed out", sw_index);
543 if (txq->state & SFC_TXQ_FLUSHED)
544 sfc_info(sa, "TxQ %u flushed", sw_index);
547 sa->dp_tx->qreap(txq->dp);
549 txq->state = SFC_TXQ_INITIALIZED;
551 efx_tx_qdestroy(txq->common);
553 sfc_ev_qstop(txq->evq);
556 * It seems to be used by DPDK for debug purposes only ('rte_ether')
558 dev_data = sa->eth_dev->data;
559 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
563 sfc_tx_start(struct sfc_adapter *sa)
565 unsigned int sw_index;
568 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
571 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
572 sfc_warn(sa, "TSO support was unable to be restored");
577 rc = efx_tx_init(sa->nic);
579 goto fail_efx_tx_init;
581 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
582 if (!(sa->txq_info[sw_index].deferred_start) ||
583 sa->txq_info[sw_index].deferred_started) {
584 rc = sfc_tx_qstart(sa, sw_index);
593 while (sw_index-- > 0)
594 sfc_tx_qstop(sa, sw_index);
596 efx_tx_fini(sa->nic);
599 sfc_log_init(sa, "failed (rc = %d)", rc);
604 sfc_tx_stop(struct sfc_adapter *sa)
606 unsigned int sw_index;
608 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
610 sw_index = sa->txq_count;
611 while (sw_index-- > 0) {
612 if (sa->txq_info[sw_index].txq != NULL)
613 sfc_tx_qstop(sa, sw_index);
616 efx_tx_fini(sa->nic);
620 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
622 unsigned int completed;
624 sfc_ev_qpoll(txq->evq);
626 for (completed = txq->completed;
627 completed != txq->pending; completed++) {
628 struct sfc_efx_tx_sw_desc *txd;
630 txd = &txq->sw_ring[completed & txq->ptr_mask];
632 if (txd->mbuf != NULL) {
633 rte_pktmbuf_free(txd->mbuf);
638 txq->completed = completed;
642 * The function is used to insert or update VLAN tag;
643 * the firmware has state of the firmware tag to insert per TxQ
644 * (controlled by option descriptors), hence, if the tag of the
645 * packet to be sent is different from one remembered by the firmware,
646 * the function will update it
649 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
652 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
655 if (this_tag == txq->hw_vlan_tci)
659 * The expression inside SFC_ASSERT() is not desired to be checked in
660 * a non-debug build because it might be too expensive on the data path
662 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
664 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
667 txq->hw_vlan_tci = this_tag;
673 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
675 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
676 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
677 unsigned int added = txq->added;
678 unsigned int pushed = added;
679 unsigned int pkts_sent = 0;
680 efx_desc_t *pend = &txq->pend_desc[0];
681 const unsigned int hard_max_fill = EFX_TXQ_LIMIT(txq->ptr_mask + 1);
682 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
683 unsigned int fill_level = added - txq->completed;
686 struct rte_mbuf **pktp;
688 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
692 * If insufficient space for a single packet is present,
693 * we should reap; otherwise, we shouldn't do that all the time
694 * to avoid latency increase
696 reap_done = (fill_level > soft_max_fill);
699 sfc_efx_tx_reap(txq);
701 * Recalculate fill level since 'txq->completed'
702 * might have changed on reap
704 fill_level = added - txq->completed;
707 for (pkts_sent = 0, pktp = &tx_pkts[0];
708 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
709 pkts_sent++, pktp++) {
710 struct rte_mbuf *m_seg = *pktp;
711 size_t pkt_len = m_seg->pkt_len;
712 unsigned int pkt_descs = 0;
716 * Here VLAN TCI is expected to be zero in case if no
717 * DEV_TX_VLAN_OFFLOAD capability is advertised;
718 * if the calling app ignores the absence of
719 * DEV_TX_VLAN_OFFLOAD and pushes VLAN TCI, then
720 * TX_ERROR will occur
722 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
724 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
726 * We expect correct 'pkt->l[2, 3, 4]_len' values
727 * to be set correctly by the caller
729 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
730 &pkt_descs, &pkt_len) != 0) {
731 /* We may have reached this place for
732 * one of the following reasons:
734 * 1) Packet header length is greater
735 * than SFC_TSOH_STD_LEN
736 * 2) TCP header starts at more then
737 * 208 bytes into the frame
739 * We will deceive RTE saying that we have sent
740 * the packet, but we will actually drop it.
741 * Hence, we should revert 'pend' to the
742 * previous state (in case we have added
743 * VLAN descriptor) and start processing
744 * another one packet. But the original
745 * mbuf shouldn't be orphaned
749 rte_pktmbuf_free(*pktp);
755 * We've only added 2 FATSOv2 option descriptors
756 * and 1 descriptor for the linearized packet header.
757 * The outstanding work will be done in the same manner
758 * as for the usual non-TSO path
762 for (; m_seg != NULL; m_seg = m_seg->next) {
763 efsys_dma_addr_t next_frag;
766 seg_len = m_seg->data_len;
767 next_frag = rte_mbuf_data_iova(m_seg);
770 * If we've started TSO transaction few steps earlier,
771 * we'll skip packet header using an offset in the
772 * current segment (which has been set to the
773 * first one containing payload)
780 efsys_dma_addr_t frag_addr = next_frag;
784 * It is assumed here that there is no
785 * limitation on address boundary
786 * crossing by DMA descriptor.
788 frag_len = MIN(seg_len, txq->dma_desc_size_max);
789 next_frag += frag_len;
793 efx_tx_qdesc_dma_create(txq->common,
799 } while (seg_len != 0);
804 fill_level += pkt_descs;
805 if (unlikely(fill_level > hard_max_fill)) {
807 * Our estimation for maximum number of descriptors
808 * required to send a packet seems to be wrong.
809 * Try to reap (if we haven't yet).
812 sfc_efx_tx_reap(txq);
814 fill_level = added - txq->completed;
815 if (fill_level > hard_max_fill) {
825 /* Assign mbuf to the last used desc */
826 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
829 if (likely(pkts_sent > 0)) {
830 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
831 pend - &txq->pend_desc[0],
832 txq->completed, &txq->added);
835 if (likely(pushed != txq->added))
836 efx_tx_qpush(txq->common, txq->added, pushed);
839 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
841 sfc_efx_tx_reap(txq);
849 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
851 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
852 struct rte_eth_dev *eth_dev;
853 struct sfc_adapter *sa;
856 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
857 eth_dev = &rte_eth_devices[dpq->port_id];
859 sa = eth_dev->data->dev_private;
861 SFC_ASSERT(dpq->queue_id < sa->txq_count);
862 txq = sa->txq_info[dpq->queue_id].txq;
864 SFC_ASSERT(txq != NULL);
868 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
870 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
871 const struct rte_pci_addr *pci_addr,
873 const struct sfc_dp_tx_qcreate_info *info,
874 struct sfc_dp_txq **dp_txqp)
876 struct sfc_efx_txq *txq;
877 struct sfc_txq *ctrl_txq;
881 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
882 RTE_CACHE_LINE_SIZE, socket_id);
886 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
889 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
890 EFX_TXQ_LIMIT(info->txq_entries),
891 sizeof(*txq->pend_desc), 0,
893 if (txq->pend_desc == NULL)
894 goto fail_pend_desc_alloc;
897 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
899 sizeof(*txq->sw_ring),
900 RTE_CACHE_LINE_SIZE, socket_id);
901 if (txq->sw_ring == NULL)
902 goto fail_sw_ring_alloc;
904 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
905 if (ctrl_txq->evq->sa->tso) {
906 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
907 info->txq_entries, socket_id);
909 goto fail_alloc_tsoh_objs;
912 txq->evq = ctrl_txq->evq;
913 txq->ptr_mask = info->txq_entries - 1;
914 txq->free_thresh = info->free_thresh;
915 txq->dma_desc_size_max = info->dma_desc_size_max;
920 fail_alloc_tsoh_objs:
921 rte_free(txq->sw_ring);
924 rte_free(txq->pend_desc);
926 fail_pend_desc_alloc:
933 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
935 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
937 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
939 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
940 rte_free(txq->sw_ring);
941 rte_free(txq->pend_desc);
945 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
947 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
948 __rte_unused unsigned int evq_read_ptr,
949 unsigned int txq_desc_index)
951 /* libefx-based datapath is specific to libefx-based PMD */
952 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
953 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
955 txq->common = ctrl_txq->common;
957 txq->pending = txq->completed = txq->added = txq_desc_index;
958 txq->hw_vlan_tci = 0;
960 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
965 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
967 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
968 __rte_unused unsigned int *evq_read_ptr)
970 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
972 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
975 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
977 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
979 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
982 sfc_efx_tx_reap(txq);
984 for (txds = 0; txds <= txq->ptr_mask; txds++) {
985 if (txq->sw_ring[txds].mbuf != NULL) {
986 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
987 txq->sw_ring[txds].mbuf = NULL;
991 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
994 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status;
996 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
998 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1000 if (unlikely(offset > txq->ptr_mask))
1003 if (unlikely(offset >= EFX_TXQ_LIMIT(txq->ptr_mask + 1)))
1004 return RTE_ETH_TX_DESC_UNAVAIL;
1007 * Poll EvQ to derive up-to-date 'txq->pending' figure;
1008 * it is required for the queue to be running, but the
1009 * check is omitted because API design assumes that it
1010 * is the duty of the caller to satisfy all conditions
1012 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) ==
1013 SFC_EFX_TXQ_FLAG_RUNNING);
1014 sfc_ev_qpoll(txq->evq);
1017 * Ring tail is 'txq->pending', and although descriptors
1018 * between 'txq->completed' and 'txq->pending' are still
1019 * in use by the driver, they should be reported as DONE
1021 if (unlikely(offset < (txq->added - txq->pending)))
1022 return RTE_ETH_TX_DESC_FULL;
1025 * There is no separate return value for unused descriptors;
1026 * the latter will be reported as DONE because genuine DONE
1027 * descriptors will be freed anyway in SW on the next burst
1029 return RTE_ETH_TX_DESC_DONE;
1032 struct sfc_dp_tx sfc_efx_tx = {
1034 .name = SFC_KVARG_DATAPATH_EFX,
1038 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
1039 SFC_DP_TX_FEAT_TSO |
1040 SFC_DP_TX_FEAT_MULTI_POOL |
1041 SFC_DP_TX_FEAT_REFCNT |
1042 SFC_DP_TX_FEAT_MULTI_SEG,
1043 .qcreate = sfc_efx_tx_qcreate,
1044 .qdestroy = sfc_efx_tx_qdestroy,
1045 .qstart = sfc_efx_tx_qstart,
1046 .qstop = sfc_efx_tx_qstop,
1047 .qreap = sfc_efx_tx_qreap,
1048 .qdesc_status = sfc_efx_tx_qdesc_status,
1049 .pkt_burst = sfc_efx_xmit_pkts,