4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "sfc_debug.h"
37 #include "sfc_tweak.h"
38 #include "sfc_kvargs.h"
41 * Maximum number of TX queue flush attempts in case of
42 * failure or flush timeout
44 #define SFC_TX_QFLUSH_ATTEMPTS (3)
47 * Time to wait between event queue polling attempts when waiting for TX
48 * queue flush done or flush failed events
50 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
53 * Maximum number of event queue polling attempts when waiting for TX queue
54 * flush done or flush failed events; it defines TX queue flush attempt timeout
55 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
57 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
60 sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc,
61 const struct rte_eth_txconf *tx_conf)
63 unsigned int flags = tx_conf->txq_flags;
64 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
67 if (tx_conf->tx_rs_thresh != 0) {
68 sfc_err(sa, "RS bit in transmit descriptor is not supported");
72 if (tx_conf->tx_free_thresh > EFX_TXQ_LIMIT(nb_tx_desc)) {
74 "TxQ free threshold too large: %u vs maximum %u",
75 tx_conf->tx_free_thresh, EFX_TXQ_LIMIT(nb_tx_desc));
79 if (tx_conf->tx_thresh.pthresh != 0 ||
80 tx_conf->tx_thresh.hthresh != 0 ||
81 tx_conf->tx_thresh.wthresh != 0) {
83 "prefetch/host/writeback thresholds are not supported");
87 if (!encp->enc_hw_tx_insert_vlan_enabled &&
88 (flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
89 sfc_err(sa, "VLAN offload is not supported");
93 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
94 sfc_err(sa, "SCTP offload is not supported");
98 /* We either perform both TCP and UDP offload, or no offload at all */
99 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
100 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
101 sfc_err(sa, "TCP and UDP offloads can't be set independently");
109 sfc_tx_qflush_done(struct sfc_txq *txq)
111 txq->state |= SFC_TXQ_FLUSHED;
112 txq->state &= ~SFC_TXQ_FLUSHING;
116 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
117 uint16_t nb_tx_desc, unsigned int socket_id,
118 const struct rte_eth_txconf *tx_conf)
120 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
121 struct sfc_txq_info *txq_info;
124 unsigned int evq_index = sfc_evq_index_by_txq_sw_index(sa, sw_index);
126 struct sfc_dp_tx_qcreate_info info;
128 sfc_log_init(sa, "TxQ = %u", sw_index);
130 rc = sfc_tx_qcheck_conf(sa, nb_tx_desc, tx_conf);
134 SFC_ASSERT(sw_index < sa->txq_count);
135 txq_info = &sa->txq_info[sw_index];
137 SFC_ASSERT(nb_tx_desc <= sa->txq_max_entries);
138 txq_info->entries = nb_tx_desc;
140 rc = sfc_ev_qinit(sa, evq_index, txq_info->entries, socket_id);
144 evq = sa->evq_info[evq_index].evq;
147 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
153 txq->hw_index = sw_index;
156 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
157 SFC_TX_DEFAULT_FREE_THRESH;
158 txq->flags = tx_conf->txq_flags;
160 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
161 socket_id, &txq->mem);
165 memset(&info, 0, sizeof(info));
166 info.free_thresh = txq->free_thresh;
167 info.flags = tx_conf->txq_flags;
168 info.txq_entries = txq_info->entries;
169 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
171 rc = sa->dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
172 &SFC_DEV_TO_PCI(sa->eth_dev)->addr,
173 socket_id, &info, &txq->dp);
175 goto fail_dp_tx_qinit;
177 evq->dp_txq = txq->dp;
179 txq->state = SFC_TXQ_INITIALIZED;
181 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
186 sfc_dma_free(sa, &txq->mem);
189 txq_info->txq = NULL;
193 sfc_ev_qfini(sa, evq_index);
196 txq_info->entries = 0;
199 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
204 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
206 struct sfc_txq_info *txq_info;
209 sfc_log_init(sa, "TxQ = %u", sw_index);
211 SFC_ASSERT(sw_index < sa->txq_count);
212 txq_info = &sa->txq_info[sw_index];
215 SFC_ASSERT(txq != NULL);
216 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
218 sa->dp_tx->qdestroy(txq->dp);
221 txq_info->txq = NULL;
222 txq_info->entries = 0;
224 sfc_dma_free(sa, &txq->mem);
229 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
231 sfc_log_init(sa, "TxQ = %u", sw_index);
237 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
241 switch (txmode->mq_mode) {
245 sfc_err(sa, "Tx multi-queue mode %u not supported",
251 * These features are claimed to be i40e-specific,
252 * but it does make sense to double-check their absence
254 if (txmode->hw_vlan_reject_tagged) {
255 sfc_err(sa, "Rejecting tagged packets not supported");
259 if (txmode->hw_vlan_reject_untagged) {
260 sfc_err(sa, "Rejecting untagged packets not supported");
264 if (txmode->hw_vlan_insert_pvid) {
265 sfc_err(sa, "Port-based VLAN insertion not supported");
273 sfc_tx_init(struct sfc_adapter *sa)
275 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
276 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
277 unsigned int sw_index;
281 * The datapath implementation assumes absence of boundary
282 * limits on Tx DMA descriptors. Addition of these checks on
283 * datapath would simply make the datapath slower.
285 if (encp->enc_tx_dma_desc_boundary != 0) {
287 goto fail_tx_dma_desc_boundary;
290 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
292 goto fail_check_mode;
294 sa->txq_count = sa->eth_dev->data->nb_tx_queues;
296 sa->txq_info = rte_calloc_socket("sfc-txqs", sa->txq_count,
297 sizeof(sa->txq_info[0]), 0,
299 if (sa->txq_info == NULL)
300 goto fail_txqs_alloc;
302 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
303 rc = sfc_tx_qinit_info(sa, sw_index);
305 goto fail_tx_qinit_info;
311 rte_free(sa->txq_info);
318 fail_tx_dma_desc_boundary:
319 sfc_log_init(sa, "failed (rc = %d)", rc);
324 sfc_tx_fini(struct sfc_adapter *sa)
328 sw_index = sa->txq_count;
329 while (--sw_index >= 0) {
330 if (sa->txq_info[sw_index].txq != NULL)
331 sfc_tx_qfini(sa, sw_index);
334 rte_free(sa->txq_info);
340 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
342 struct rte_eth_dev_data *dev_data;
343 struct sfc_txq_info *txq_info;
347 unsigned int desc_index;
350 sfc_log_init(sa, "TxQ = %u", sw_index);
352 SFC_ASSERT(sw_index < sa->txq_count);
353 txq_info = &sa->txq_info[sw_index];
357 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
361 rc = sfc_ev_qstart(sa, evq->evq_index);
366 * It seems that DPDK has no controls regarding IPv4 offloads,
367 * hence, we always enable it here
369 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
370 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP)) {
371 flags = EFX_TXQ_CKSUM_IPV4;
373 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
376 flags |= EFX_TXQ_FATSOV2;
379 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
380 txq_info->entries, 0 /* not used on EF10 */,
382 &txq->common, &desc_index);
384 if (sa->tso && (rc == ENOSPC))
385 sfc_err(sa, "ran out of TSO contexts");
387 goto fail_tx_qcreate;
390 efx_tx_qenable(txq->common);
392 txq->state |= SFC_TXQ_STARTED;
394 rc = sa->dp_tx->qstart(txq->dp, evq->read_ptr, desc_index);
399 * It seems to be used by DPDK for debug purposes only ('rte_ether')
401 dev_data = sa->eth_dev->data;
402 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
407 txq->state = SFC_TXQ_INITIALIZED;
408 efx_tx_qdestroy(txq->common);
411 sfc_ev_qstop(sa, evq->evq_index);
418 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
420 struct rte_eth_dev_data *dev_data;
421 struct sfc_txq_info *txq_info;
423 unsigned int retry_count;
424 unsigned int wait_count;
426 sfc_log_init(sa, "TxQ = %u", sw_index);
428 SFC_ASSERT(sw_index < sa->txq_count);
429 txq_info = &sa->txq_info[sw_index];
433 if (txq->state == SFC_TXQ_INITIALIZED)
436 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
438 sa->dp_tx->qstop(txq->dp, &txq->evq->read_ptr);
441 * Retry TX queue flushing in case of flush failed or
442 * timeout; in the worst case it can delay for 6 seconds
444 for (retry_count = 0;
445 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
446 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
448 if (efx_tx_qflush(txq->common) != 0) {
449 txq->state |= SFC_TXQ_FLUSHING;
454 * Wait for TX queue flush done or flush failed event at least
455 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
456 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
457 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
461 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
462 sfc_ev_qpoll(txq->evq);
463 } while ((txq->state & SFC_TXQ_FLUSHING) &&
464 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
466 if (txq->state & SFC_TXQ_FLUSHING)
467 sfc_err(sa, "TxQ %u flush timed out", sw_index);
469 if (txq->state & SFC_TXQ_FLUSHED)
470 sfc_info(sa, "TxQ %u flushed", sw_index);
473 sa->dp_tx->qreap(txq->dp);
475 txq->state = SFC_TXQ_INITIALIZED;
477 efx_tx_qdestroy(txq->common);
479 sfc_ev_qstop(sa, txq->evq->evq_index);
482 * It seems to be used by DPDK for debug purposes only ('rte_ether')
484 dev_data = sa->eth_dev->data;
485 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
489 sfc_tx_start(struct sfc_adapter *sa)
491 unsigned int sw_index;
494 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
497 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
498 sfc_warn(sa, "TSO support was unable to be restored");
503 rc = efx_tx_init(sa->nic);
505 goto fail_efx_tx_init;
507 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
508 if (!(sa->txq_info[sw_index].deferred_start) ||
509 sa->txq_info[sw_index].deferred_started) {
510 rc = sfc_tx_qstart(sa, sw_index);
519 while (sw_index-- > 0)
520 sfc_tx_qstop(sa, sw_index);
522 efx_tx_fini(sa->nic);
525 sfc_log_init(sa, "failed (rc = %d)", rc);
530 sfc_tx_stop(struct sfc_adapter *sa)
532 unsigned int sw_index;
534 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
536 sw_index = sa->txq_count;
537 while (sw_index-- > 0) {
538 if (sa->txq_info[sw_index].txq != NULL)
539 sfc_tx_qstop(sa, sw_index);
542 efx_tx_fini(sa->nic);
546 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
548 unsigned int completed;
550 sfc_ev_qpoll(txq->evq);
552 for (completed = txq->completed;
553 completed != txq->pending; completed++) {
554 struct sfc_efx_tx_sw_desc *txd;
556 txd = &txq->sw_ring[completed & txq->ptr_mask];
558 if (txd->mbuf != NULL) {
559 rte_pktmbuf_free(txd->mbuf);
564 txq->completed = completed;
568 * The function is used to insert or update VLAN tag;
569 * the firmware has state of the firmware tag to insert per TxQ
570 * (controlled by option descriptors), hence, if the tag of the
571 * packet to be sent is different from one remembered by the firmware,
572 * the function will update it
575 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
578 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
581 if (this_tag == txq->hw_vlan_tci)
585 * The expression inside SFC_ASSERT() is not desired to be checked in
586 * a non-debug build because it might be too expensive on the data path
588 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
590 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
593 txq->hw_vlan_tci = this_tag;
599 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
601 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
602 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
603 unsigned int added = txq->added;
604 unsigned int pushed = added;
605 unsigned int pkts_sent = 0;
606 efx_desc_t *pend = &txq->pend_desc[0];
607 const unsigned int hard_max_fill = EFX_TXQ_LIMIT(txq->ptr_mask + 1);
608 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
609 unsigned int fill_level = added - txq->completed;
612 struct rte_mbuf **pktp;
614 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
618 * If insufficient space for a single packet is present,
619 * we should reap; otherwise, we shouldn't do that all the time
620 * to avoid latency increase
622 reap_done = (fill_level > soft_max_fill);
625 sfc_efx_tx_reap(txq);
627 * Recalculate fill level since 'txq->completed'
628 * might have changed on reap
630 fill_level = added - txq->completed;
633 for (pkts_sent = 0, pktp = &tx_pkts[0];
634 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
635 pkts_sent++, pktp++) {
636 struct rte_mbuf *m_seg = *pktp;
637 size_t pkt_len = m_seg->pkt_len;
638 unsigned int pkt_descs = 0;
642 * Here VLAN TCI is expected to be zero in case if no
643 * DEV_TX_VLAN_OFFLOAD capability is advertised;
644 * if the calling app ignores the absence of
645 * DEV_TX_VLAN_OFFLOAD and pushes VLAN TCI, then
646 * TX_ERROR will occur
648 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
650 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
652 * We expect correct 'pkt->l[2, 3, 4]_len' values
653 * to be set correctly by the caller
655 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
656 &pkt_descs, &pkt_len) != 0) {
657 /* We may have reached this place for
658 * one of the following reasons:
660 * 1) Packet header length is greater
661 * than SFC_TSOH_STD_LEN
662 * 2) TCP header starts at more then
663 * 208 bytes into the frame
665 * We will deceive RTE saying that we have sent
666 * the packet, but we will actually drop it.
667 * Hence, we should revert 'pend' to the
668 * previous state (in case we have added
669 * VLAN descriptor) and start processing
670 * another one packet. But the original
671 * mbuf shouldn't be orphaned
675 rte_pktmbuf_free(*pktp);
681 * We've only added 2 FATSOv2 option descriptors
682 * and 1 descriptor for the linearized packet header.
683 * The outstanding work will be done in the same manner
684 * as for the usual non-TSO path
688 for (; m_seg != NULL; m_seg = m_seg->next) {
689 efsys_dma_addr_t next_frag;
692 seg_len = m_seg->data_len;
693 next_frag = rte_mbuf_data_dma_addr(m_seg);
696 * If we've started TSO transaction few steps earlier,
697 * we'll skip packet header using an offset in the
698 * current segment (which has been set to the
699 * first one containing payload)
706 efsys_dma_addr_t frag_addr = next_frag;
710 * It is assumed here that there is no
711 * limitation on address boundary
712 * crossing by DMA descriptor.
714 frag_len = MIN(seg_len, txq->dma_desc_size_max);
715 next_frag += frag_len;
719 efx_tx_qdesc_dma_create(txq->common,
725 } while (seg_len != 0);
730 fill_level += pkt_descs;
731 if (unlikely(fill_level > hard_max_fill)) {
733 * Our estimation for maximum number of descriptors
734 * required to send a packet seems to be wrong.
735 * Try to reap (if we haven't yet).
738 sfc_efx_tx_reap(txq);
740 fill_level = added - txq->completed;
741 if (fill_level > hard_max_fill) {
751 /* Assign mbuf to the last used desc */
752 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
755 if (likely(pkts_sent > 0)) {
756 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
757 pend - &txq->pend_desc[0],
758 txq->completed, &txq->added);
761 if (likely(pushed != txq->added))
762 efx_tx_qpush(txq->common, txq->added, pushed);
765 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
767 sfc_efx_tx_reap(txq);
775 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
777 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
778 struct rte_eth_dev *eth_dev;
779 struct sfc_adapter *sa;
782 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
783 eth_dev = &rte_eth_devices[dpq->port_id];
785 sa = eth_dev->data->dev_private;
787 SFC_ASSERT(dpq->queue_id < sa->txq_count);
788 txq = sa->txq_info[dpq->queue_id].txq;
790 SFC_ASSERT(txq != NULL);
794 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
796 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
797 const struct rte_pci_addr *pci_addr,
799 const struct sfc_dp_tx_qcreate_info *info,
800 struct sfc_dp_txq **dp_txqp)
802 struct sfc_efx_txq *txq;
803 struct sfc_txq *ctrl_txq;
807 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
808 RTE_CACHE_LINE_SIZE, socket_id);
812 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
815 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
816 EFX_TXQ_LIMIT(info->txq_entries),
817 sizeof(*txq->pend_desc), 0,
819 if (txq->pend_desc == NULL)
820 goto fail_pend_desc_alloc;
823 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
825 sizeof(*txq->sw_ring),
826 RTE_CACHE_LINE_SIZE, socket_id);
827 if (txq->sw_ring == NULL)
828 goto fail_sw_ring_alloc;
830 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
831 if (ctrl_txq->evq->sa->tso) {
832 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
833 info->txq_entries, socket_id);
835 goto fail_alloc_tsoh_objs;
838 txq->evq = ctrl_txq->evq;
839 txq->ptr_mask = info->txq_entries - 1;
840 txq->free_thresh = info->free_thresh;
841 txq->dma_desc_size_max = info->dma_desc_size_max;
846 fail_alloc_tsoh_objs:
847 rte_free(txq->sw_ring);
850 rte_free(txq->pend_desc);
852 fail_pend_desc_alloc:
859 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
861 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
863 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
865 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
866 rte_free(txq->sw_ring);
867 rte_free(txq->pend_desc);
871 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
873 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
874 __rte_unused unsigned int evq_read_ptr,
875 unsigned int txq_desc_index)
877 /* libefx-based datapath is specific to libefx-based PMD */
878 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
879 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
881 txq->common = ctrl_txq->common;
883 txq->pending = txq->completed = txq->added = txq_desc_index;
884 txq->hw_vlan_tci = 0;
886 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
891 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
893 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
894 __rte_unused unsigned int *evq_read_ptr)
896 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
898 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
901 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
903 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
905 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
908 sfc_efx_tx_reap(txq);
910 for (txds = 0; txds <= txq->ptr_mask; txds++) {
911 if (txq->sw_ring[txds].mbuf != NULL) {
912 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
913 txq->sw_ring[txds].mbuf = NULL;
917 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
920 struct sfc_dp_tx sfc_efx_tx = {
922 .name = SFC_KVARG_DATAPATH_EFX,
926 .qcreate = sfc_efx_tx_qcreate,
927 .qdestroy = sfc_efx_tx_qdestroy,
928 .qstart = sfc_efx_tx_qstart,
929 .qstop = sfc_efx_tx_qstop,
930 .qreap = sfc_efx_tx_qreap,
931 .pkt_burst = sfc_efx_xmit_pkts,