2 * Copyright (c) 2016 Solarflare Communications Inc.
5 * This software was jointly developed between OKTET Labs (under contract
6 * for Solarflare) and Solarflare Communications, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
27 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "sfc_debug.h"
35 #include "sfc_tweak.h"
38 * Maximum number of TX queue flush attempts in case of
39 * failure or flush timeout
41 #define SFC_TX_QFLUSH_ATTEMPTS (3)
44 * Time to wait between event queue polling attempts when waiting for TX
45 * queue flush done or flush failed events
47 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
50 * Maximum number of event queue polling attempts when waiting for TX queue
51 * flush done or flush failed events; it defines TX queue flush attempt timeout
52 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
54 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
57 sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc,
58 const struct rte_eth_txconf *tx_conf)
60 unsigned int flags = tx_conf->txq_flags;
63 if (tx_conf->tx_rs_thresh != 0) {
64 sfc_err(sa, "RS bit in transmit descriptor is not supported");
68 if (tx_conf->tx_free_thresh > EFX_TXQ_LIMIT(nb_tx_desc)) {
70 "TxQ free threshold too large: %u vs maximum %u",
71 tx_conf->tx_free_thresh, EFX_TXQ_LIMIT(nb_tx_desc));
75 if (tx_conf->tx_deferred_start != 0) {
76 sfc_err(sa, "TX queue deferred start is not supported (yet)");
80 if (tx_conf->tx_thresh.pthresh != 0 ||
81 tx_conf->tx_thresh.hthresh != 0 ||
82 tx_conf->tx_thresh.wthresh != 0) {
84 "prefetch/host/writeback thresholds are not supported");
88 if ((flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
89 sfc_err(sa, "VLAN offload is not supported");
93 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
94 sfc_err(sa, "SCTP offload is not supported");
98 /* We either perform both TCP and UDP offload, or no offload at all */
99 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
100 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
101 sfc_err(sa, "TCP and UDP offloads can't be set independently");
109 sfc_tx_qflush_done(struct sfc_txq *txq)
111 txq->state |= SFC_TXQ_FLUSHED;
112 txq->state &= ~SFC_TXQ_FLUSHING;
116 sfc_tx_reap(struct sfc_txq *txq)
118 unsigned int completed;
121 sfc_ev_qpoll(txq->evq);
123 for (completed = txq->completed;
124 completed != txq->pending; completed++) {
125 struct sfc_tx_sw_desc *txd;
127 txd = &txq->sw_ring[completed & txq->ptr_mask];
129 if (txd->mbuf != NULL) {
130 rte_pktmbuf_free(txd->mbuf);
135 txq->completed = completed;
139 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
140 uint16_t nb_tx_desc, unsigned int socket_id,
141 const struct rte_eth_txconf *tx_conf)
143 struct sfc_txq_info *txq_info;
146 unsigned int evq_index = sfc_evq_index_by_txq_sw_index(sa, sw_index);
149 sfc_log_init(sa, "TxQ = %u", sw_index);
151 rc = sfc_tx_qcheck_conf(sa, nb_tx_desc, tx_conf);
155 SFC_ASSERT(sw_index < sa->txq_count);
156 txq_info = &sa->txq_info[sw_index];
158 SFC_ASSERT(nb_tx_desc <= sa->txq_max_entries);
159 txq_info->entries = nb_tx_desc;
161 rc = sfc_ev_qinit(sa, evq_index, txq_info->entries, socket_id);
165 evq = sa->evq_info[evq_index].evq;
168 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
172 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
173 socket_id, &txq->mem);
178 txq->pend_desc = rte_calloc_socket("sfc-txq-pend-desc",
179 EFX_TXQ_LIMIT(txq_info->entries),
180 sizeof(efx_desc_t), 0, socket_id);
181 if (txq->pend_desc == NULL)
182 goto fail_pend_desc_alloc;
185 txq->sw_ring = rte_calloc_socket("sfc-txq-desc", txq_info->entries,
186 sizeof(*txq->sw_ring), 0, socket_id);
187 if (txq->sw_ring == NULL)
188 goto fail_desc_alloc;
190 txq->state = SFC_TXQ_INITIALIZED;
191 txq->ptr_mask = txq_info->entries - 1;
192 txq->free_thresh = (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
193 SFC_TX_DEFAULT_FREE_THRESH;
194 txq->hw_index = sw_index;
195 txq->flags = tx_conf->txq_flags;
205 rte_free(txq->pend_desc);
207 fail_pend_desc_alloc:
208 sfc_dma_free(sa, &txq->mem);
214 sfc_ev_qfini(sa, evq_index);
217 txq_info->entries = 0;
220 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
225 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
227 struct sfc_txq_info *txq_info;
230 sfc_log_init(sa, "TxQ = %u", sw_index);
232 SFC_ASSERT(sw_index < sa->txq_count);
233 txq_info = &sa->txq_info[sw_index];
236 SFC_ASSERT(txq != NULL);
237 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
239 txq_info->txq = NULL;
240 txq_info->entries = 0;
242 rte_free(txq->sw_ring);
243 rte_free(txq->pend_desc);
244 sfc_dma_free(sa, &txq->mem);
249 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
251 sfc_log_init(sa, "TxQ = %u", sw_index);
257 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
261 switch (txmode->mq_mode) {
265 sfc_err(sa, "Tx multi-queue mode %u not supported",
271 * These features are claimed to be i40e-specific,
272 * but it does make sense to double-check their absence
274 if (txmode->hw_vlan_reject_tagged) {
275 sfc_err(sa, "Rejecting tagged packets not supported");
279 if (txmode->hw_vlan_reject_untagged) {
280 sfc_err(sa, "Rejecting untagged packets not supported");
284 if (txmode->hw_vlan_insert_pvid) {
285 sfc_err(sa, "Port-based VLAN insertion not supported");
293 sfc_tx_init(struct sfc_adapter *sa)
295 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
296 unsigned int sw_index;
299 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
301 goto fail_check_mode;
303 sa->txq_count = sa->eth_dev->data->nb_tx_queues;
305 sa->txq_info = rte_calloc_socket("sfc-txqs", sa->txq_count,
306 sizeof(sa->txq_info[0]), 0,
308 if (sa->txq_info == NULL)
309 goto fail_txqs_alloc;
311 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
312 rc = sfc_tx_qinit_info(sa, sw_index);
314 goto fail_tx_qinit_info;
320 rte_free(sa->txq_info);
327 sfc_log_init(sa, "failed (rc = %d)", rc);
332 sfc_tx_fini(struct sfc_adapter *sa)
336 sw_index = sa->txq_count;
337 while (--sw_index >= 0) {
338 if (sa->txq_info[sw_index].txq != NULL)
339 sfc_tx_qfini(sa, sw_index);
342 rte_free(sa->txq_info);
348 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
350 struct rte_eth_dev_data *dev_data;
351 struct sfc_txq_info *txq_info;
355 unsigned int desc_index;
358 sfc_log_init(sa, "TxQ = %u", sw_index);
360 SFC_ASSERT(sw_index < sa->txq_count);
361 txq_info = &sa->txq_info[sw_index];
365 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
369 rc = sfc_ev_qstart(sa, evq->evq_index);
374 * It seems that DPDK has no controls regarding IPv4 offloads,
375 * hence, we always enable it here
377 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
378 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP))
379 flags = EFX_TXQ_CKSUM_IPV4;
381 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
383 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
384 txq_info->entries, 0 /* not used on EF10 */,
386 &txq->common, &desc_index);
388 goto fail_tx_qcreate;
390 txq->added = txq->pending = txq->completed = desc_index;
392 efx_tx_qenable(txq->common);
394 txq->state |= (SFC_TXQ_STARTED | SFC_TXQ_RUNNING);
397 * It seems to be used by DPDK for debug purposes only ('rte_ether')
399 dev_data = sa->eth_dev->data;
400 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
405 sfc_ev_qstop(sa, evq->evq_index);
412 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
414 struct rte_eth_dev_data *dev_data;
415 struct sfc_txq_info *txq_info;
417 unsigned int retry_count;
418 unsigned int wait_count;
421 sfc_log_init(sa, "TxQ = %u", sw_index);
423 SFC_ASSERT(sw_index < sa->txq_count);
424 txq_info = &sa->txq_info[sw_index];
428 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
430 txq->state &= ~SFC_TXQ_RUNNING;
433 * Retry TX queue flushing in case of flush failed or
434 * timeout; in the worst case it can delay for 6 seconds
436 for (retry_count = 0;
437 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
438 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
440 if (efx_tx_qflush(txq->common) != 0) {
441 txq->state |= SFC_TXQ_FLUSHING;
446 * Wait for TX queue flush done or flush failed event at least
447 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
448 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
449 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
453 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
454 sfc_ev_qpoll(txq->evq);
455 } while ((txq->state & SFC_TXQ_FLUSHING) &&
456 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
458 if (txq->state & SFC_TXQ_FLUSHING)
459 sfc_err(sa, "TxQ %u flush timed out", sw_index);
461 if (txq->state & SFC_TXQ_FLUSHED)
462 sfc_info(sa, "TxQ %u flushed", sw_index);
467 for (txds = 0; txds < txq_info->entries; txds++) {
468 if (txq->sw_ring[txds].mbuf != NULL) {
469 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
470 txq->sw_ring[txds].mbuf = NULL;
474 txq->state = SFC_TXQ_INITIALIZED;
476 efx_tx_qdestroy(txq->common);
478 sfc_ev_qstop(sa, txq->evq->evq_index);
481 * It seems to be used by DPDK for debug purposes only ('rte_ether')
483 dev_data = sa->eth_dev->data;
484 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
488 sfc_tx_start(struct sfc_adapter *sa)
490 unsigned int sw_index;
493 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
495 rc = efx_tx_init(sa->nic);
497 goto fail_efx_tx_init;
499 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
500 rc = sfc_tx_qstart(sa, sw_index);
508 while (sw_index-- > 0)
509 sfc_tx_qstop(sa, sw_index);
511 efx_tx_fini(sa->nic);
514 sfc_log_init(sa, "failed (rc = %d)", rc);
519 sfc_tx_stop(struct sfc_adapter *sa)
521 unsigned int sw_index;
523 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
525 sw_index = sa->txq_count;
526 while (sw_index-- > 0) {
527 if (sa->txq_info[sw_index].txq != NULL)
528 sfc_tx_qstop(sa, sw_index);
531 efx_tx_fini(sa->nic);
535 sfc_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
537 struct sfc_txq *txq = (struct sfc_txq *)tx_queue;
538 unsigned int added = txq->added;
539 unsigned int pushed = added;
540 unsigned int pkts_sent = 0;
541 efx_desc_t *pend = &txq->pend_desc[0];
542 const unsigned int hard_max_fill = EFX_TXQ_LIMIT(txq->ptr_mask + 1);
543 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
544 unsigned int fill_level = added - txq->completed;
547 struct rte_mbuf **pktp;
549 if (unlikely((txq->state & SFC_TXQ_RUNNING) == 0))
553 * If insufficient space for a single packet is present,
554 * we should reap; otherwise, we shouldn't do that all the time
555 * to avoid latency increase
557 reap_done = (fill_level > soft_max_fill);
562 * Recalculate fill level since 'txq->completed'
563 * might have changed on reap
565 fill_level = added - txq->completed;
568 for (pkts_sent = 0, pktp = &tx_pkts[0];
569 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
570 pkts_sent++, pktp++) {
571 struct rte_mbuf *m_seg = *pktp;
572 size_t pkt_len = m_seg->pkt_len;
573 unsigned int pkt_descs = 0;
575 for (; m_seg != NULL; m_seg = m_seg->next) {
576 efsys_dma_addr_t next_frag;
579 seg_len = m_seg->data_len;
580 next_frag = rte_mbuf_data_dma_addr(m_seg);
583 efsys_dma_addr_t frag_addr = next_frag;
586 next_frag = RTE_ALIGN(frag_addr + 1,
587 SFC_TX_SEG_BOUNDARY);
588 frag_len = MIN(next_frag - frag_addr, seg_len);
592 efx_tx_qdesc_dma_create(txq->common,
598 } while (seg_len != 0);
603 fill_level += pkt_descs;
604 if (unlikely(fill_level > hard_max_fill)) {
606 * Our estimation for maximum number of descriptors
607 * required to send a packet seems to be wrong.
608 * Try to reap (if we haven't yet).
613 fill_level = added - txq->completed;
614 if (fill_level > hard_max_fill) {
624 /* Assign mbuf to the last used desc */
625 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
628 if (likely(pkts_sent > 0)) {
629 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
630 pend - &txq->pend_desc[0],
631 txq->completed, &txq->added);
634 if (likely(pushed != txq->added))
635 efx_tx_qpush(txq->common, txq->added, pushed);
638 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE