4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "sfc_debug.h"
37 #include "sfc_tweak.h"
38 #include "sfc_kvargs.h"
41 * Maximum number of TX queue flush attempts in case of
42 * failure or flush timeout
44 #define SFC_TX_QFLUSH_ATTEMPTS (3)
47 * Time to wait between event queue polling attempts when waiting for TX
48 * queue flush done or flush failed events
50 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
53 * Maximum number of event queue polling attempts when waiting for TX queue
54 * flush done or flush failed events; it defines TX queue flush attempt timeout
55 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
57 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
60 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level,
61 const struct rte_eth_txconf *tx_conf)
63 unsigned int flags = tx_conf->txq_flags;
64 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
67 if (tx_conf->tx_rs_thresh != 0) {
68 sfc_err(sa, "RS bit in transmit descriptor is not supported");
72 if (tx_conf->tx_free_thresh > txq_max_fill_level) {
74 "TxQ free threshold too large: %u vs maximum %u",
75 tx_conf->tx_free_thresh, txq_max_fill_level);
79 if (tx_conf->tx_thresh.pthresh != 0 ||
80 tx_conf->tx_thresh.hthresh != 0 ||
81 tx_conf->tx_thresh.wthresh != 0) {
83 "prefetch/host/writeback thresholds are not supported");
86 if (((flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) &&
87 (~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG)) {
88 sfc_err(sa, "Multi-segment is not supported by %s datapath",
93 if (((flags & ETH_TXQ_FLAGS_NOMULTMEMP) == 0) &&
94 (~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_POOL)) {
95 sfc_err(sa, "multi-mempool is not supported by %s datapath",
100 if (((flags & ETH_TXQ_FLAGS_NOREFCOUNT) == 0) &&
101 (~sa->dp_tx->features & SFC_DP_TX_FEAT_REFCNT)) {
103 "mbuf reference counters are neglected by %s datapath",
108 if ((flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
109 if (!encp->enc_hw_tx_insert_vlan_enabled) {
110 sfc_err(sa, "VLAN offload is not supported");
112 } else if (~sa->dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) {
114 "VLAN offload is not supported by %s datapath",
120 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
121 sfc_err(sa, "SCTP offload is not supported");
125 /* We either perform both TCP and UDP offload, or no offload at all */
126 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
127 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
128 sfc_err(sa, "TCP and UDP offloads can't be set independently");
136 sfc_tx_qflush_done(struct sfc_txq *txq)
138 txq->state |= SFC_TXQ_FLUSHED;
139 txq->state &= ~SFC_TXQ_FLUSHING;
143 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
144 uint16_t nb_tx_desc, unsigned int socket_id,
145 const struct rte_eth_txconf *tx_conf)
147 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
148 unsigned int txq_entries;
149 unsigned int evq_entries;
150 unsigned int txq_max_fill_level;
151 struct sfc_txq_info *txq_info;
155 struct sfc_dp_tx_qcreate_info info;
157 sfc_log_init(sa, "TxQ = %u", sw_index);
159 rc = sa->dp_tx->qsize_up_rings(nb_tx_desc, &txq_entries, &evq_entries,
160 &txq_max_fill_level);
162 goto fail_size_up_rings;
164 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf);
168 SFC_ASSERT(sw_index < sa->txq_count);
169 txq_info = &sa->txq_info[sw_index];
171 SFC_ASSERT(txq_entries <= sa->txq_max_entries);
172 txq_info->entries = txq_entries;
174 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index,
175 evq_entries, socket_id, &evq);
180 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
186 txq->hw_index = sw_index;
189 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
190 SFC_TX_DEFAULT_FREE_THRESH;
191 txq->flags = tx_conf->txq_flags;
193 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
194 socket_id, &txq->mem);
198 memset(&info, 0, sizeof(info));
199 info.free_thresh = txq->free_thresh;
200 info.flags = tx_conf->txq_flags;
201 info.txq_entries = txq_info->entries;
202 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
203 info.txq_hw_ring = txq->mem.esm_base;
204 info.evq_entries = evq_entries;
205 info.evq_hw_ring = evq->mem.esm_base;
206 info.hw_index = txq->hw_index;
207 info.mem_bar = sa->mem_bar.esb_base;
209 rc = sa->dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
210 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr,
211 socket_id, &info, &txq->dp);
213 goto fail_dp_tx_qinit;
215 evq->dp_txq = txq->dp;
217 txq->state = SFC_TXQ_INITIALIZED;
219 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
224 sfc_dma_free(sa, &txq->mem);
227 txq_info->txq = NULL;
234 txq_info->entries = 0;
238 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
243 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
245 struct sfc_txq_info *txq_info;
248 sfc_log_init(sa, "TxQ = %u", sw_index);
250 SFC_ASSERT(sw_index < sa->txq_count);
251 txq_info = &sa->txq_info[sw_index];
254 SFC_ASSERT(txq != NULL);
255 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
257 sa->dp_tx->qdestroy(txq->dp);
260 txq_info->txq = NULL;
261 txq_info->entries = 0;
263 sfc_dma_free(sa, &txq->mem);
265 sfc_ev_qfini(txq->evq);
272 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
274 sfc_log_init(sa, "TxQ = %u", sw_index);
280 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
284 switch (txmode->mq_mode) {
288 sfc_err(sa, "Tx multi-queue mode %u not supported",
294 * These features are claimed to be i40e-specific,
295 * but it does make sense to double-check their absence
297 if (txmode->hw_vlan_reject_tagged) {
298 sfc_err(sa, "Rejecting tagged packets not supported");
302 if (txmode->hw_vlan_reject_untagged) {
303 sfc_err(sa, "Rejecting untagged packets not supported");
307 if (txmode->hw_vlan_insert_pvid) {
308 sfc_err(sa, "Port-based VLAN insertion not supported");
316 * Destroy excess queues that are no longer needed after reconfiguration
320 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues)
324 SFC_ASSERT(nb_tx_queues <= sa->txq_count);
326 sw_index = sa->txq_count;
327 while (--sw_index >= (int)nb_tx_queues) {
328 if (sa->txq_info[sw_index].txq != NULL)
329 sfc_tx_qfini(sa, sw_index);
332 sa->txq_count = nb_tx_queues;
336 sfc_tx_configure(struct sfc_adapter *sa)
338 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
339 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
340 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues;
343 sfc_log_init(sa, "nb_tx_queues=%u (old %u)",
344 nb_tx_queues, sa->txq_count);
347 * The datapath implementation assumes absence of boundary
348 * limits on Tx DMA descriptors. Addition of these checks on
349 * datapath would simply make the datapath slower.
351 if (encp->enc_tx_dma_desc_boundary != 0) {
353 goto fail_tx_dma_desc_boundary;
356 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
358 goto fail_check_mode;
360 if (nb_tx_queues == sa->txq_count)
363 if (sa->txq_info == NULL) {
364 sa->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues,
365 sizeof(sa->txq_info[0]), 0,
367 if (sa->txq_info == NULL)
368 goto fail_txqs_alloc;
370 struct sfc_txq_info *new_txq_info;
372 if (nb_tx_queues < sa->txq_count)
373 sfc_tx_fini_queues(sa, nb_tx_queues);
376 rte_realloc(sa->txq_info,
377 nb_tx_queues * sizeof(sa->txq_info[0]), 0);
378 if (new_txq_info == NULL && nb_tx_queues > 0)
379 goto fail_txqs_realloc;
381 sa->txq_info = new_txq_info;
382 if (nb_tx_queues > sa->txq_count)
383 memset(&sa->txq_info[sa->txq_count], 0,
384 (nb_tx_queues - sa->txq_count) *
385 sizeof(sa->txq_info[0]));
388 while (sa->txq_count < nb_tx_queues) {
389 rc = sfc_tx_qinit_info(sa, sa->txq_count);
391 goto fail_tx_qinit_info;
405 fail_tx_dma_desc_boundary:
406 sfc_log_init(sa, "failed (rc = %d)", rc);
411 sfc_tx_close(struct sfc_adapter *sa)
413 sfc_tx_fini_queues(sa, 0);
415 rte_free(sa->txq_info);
420 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
422 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
423 struct rte_eth_dev_data *dev_data;
424 struct sfc_txq_info *txq_info;
428 unsigned int desc_index;
431 sfc_log_init(sa, "TxQ = %u", sw_index);
433 SFC_ASSERT(sw_index < sa->txq_count);
434 txq_info = &sa->txq_info[sw_index];
438 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
442 rc = sfc_ev_qstart(evq, sfc_evq_index_by_txq_sw_index(sa, sw_index));
447 * It seems that DPDK has no controls regarding IPv4 offloads,
448 * hence, we always enable it here
450 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
451 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP)) {
452 flags = EFX_TXQ_CKSUM_IPV4;
454 if (encp->enc_tunnel_encapsulations_supported != 0)
455 flags |= EFX_TXQ_CKSUM_INNER_IPV4;
457 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
459 if (encp->enc_tunnel_encapsulations_supported != 0)
460 flags |= EFX_TXQ_CKSUM_INNER_IPV4 |
461 EFX_TXQ_CKSUM_INNER_TCPUDP;
464 flags |= EFX_TXQ_FATSOV2;
467 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
468 txq_info->entries, 0 /* not used on EF10 */,
470 &txq->common, &desc_index);
472 if (sa->tso && (rc == ENOSPC))
473 sfc_err(sa, "ran out of TSO contexts");
475 goto fail_tx_qcreate;
478 efx_tx_qenable(txq->common);
480 txq->state |= SFC_TXQ_STARTED;
482 rc = sa->dp_tx->qstart(txq->dp, evq->read_ptr, desc_index);
487 * It seems to be used by DPDK for debug purposes only ('rte_ether')
489 dev_data = sa->eth_dev->data;
490 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
495 txq->state = SFC_TXQ_INITIALIZED;
496 efx_tx_qdestroy(txq->common);
506 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
508 struct rte_eth_dev_data *dev_data;
509 struct sfc_txq_info *txq_info;
511 unsigned int retry_count;
512 unsigned int wait_count;
515 sfc_log_init(sa, "TxQ = %u", sw_index);
517 SFC_ASSERT(sw_index < sa->txq_count);
518 txq_info = &sa->txq_info[sw_index];
522 if (txq->state == SFC_TXQ_INITIALIZED)
525 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
527 sa->dp_tx->qstop(txq->dp, &txq->evq->read_ptr);
530 * Retry TX queue flushing in case of flush failed or
531 * timeout; in the worst case it can delay for 6 seconds
533 for (retry_count = 0;
534 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
535 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
537 rc = efx_tx_qflush(txq->common);
539 txq->state |= (rc == EALREADY) ?
540 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED;
545 * Wait for TX queue flush done or flush failed event at least
546 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
547 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
548 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
552 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
553 sfc_ev_qpoll(txq->evq);
554 } while ((txq->state & SFC_TXQ_FLUSHING) &&
555 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
557 if (txq->state & SFC_TXQ_FLUSHING)
558 sfc_err(sa, "TxQ %u flush timed out", sw_index);
560 if (txq->state & SFC_TXQ_FLUSHED)
561 sfc_info(sa, "TxQ %u flushed", sw_index);
564 sa->dp_tx->qreap(txq->dp);
566 txq->state = SFC_TXQ_INITIALIZED;
568 efx_tx_qdestroy(txq->common);
570 sfc_ev_qstop(txq->evq);
573 * It seems to be used by DPDK for debug purposes only ('rte_ether')
575 dev_data = sa->eth_dev->data;
576 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
580 sfc_tx_start(struct sfc_adapter *sa)
582 unsigned int sw_index;
585 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
588 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
589 sfc_warn(sa, "TSO support was unable to be restored");
594 rc = efx_tx_init(sa->nic);
596 goto fail_efx_tx_init;
598 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
599 if (!(sa->txq_info[sw_index].deferred_start) ||
600 sa->txq_info[sw_index].deferred_started) {
601 rc = sfc_tx_qstart(sa, sw_index);
610 while (sw_index-- > 0)
611 sfc_tx_qstop(sa, sw_index);
613 efx_tx_fini(sa->nic);
616 sfc_log_init(sa, "failed (rc = %d)", rc);
621 sfc_tx_stop(struct sfc_adapter *sa)
623 unsigned int sw_index;
625 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
627 sw_index = sa->txq_count;
628 while (sw_index-- > 0) {
629 if (sa->txq_info[sw_index].txq != NULL)
630 sfc_tx_qstop(sa, sw_index);
633 efx_tx_fini(sa->nic);
637 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
639 unsigned int completed;
641 sfc_ev_qpoll(txq->evq);
643 for (completed = txq->completed;
644 completed != txq->pending; completed++) {
645 struct sfc_efx_tx_sw_desc *txd;
647 txd = &txq->sw_ring[completed & txq->ptr_mask];
649 if (txd->mbuf != NULL) {
650 rte_pktmbuf_free(txd->mbuf);
655 txq->completed = completed;
659 * The function is used to insert or update VLAN tag;
660 * the firmware has state of the firmware tag to insert per TxQ
661 * (controlled by option descriptors), hence, if the tag of the
662 * packet to be sent is different from one remembered by the firmware,
663 * the function will update it
666 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
669 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
672 if (this_tag == txq->hw_vlan_tci)
676 * The expression inside SFC_ASSERT() is not desired to be checked in
677 * a non-debug build because it might be too expensive on the data path
679 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
681 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
684 txq->hw_vlan_tci = this_tag;
690 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
692 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
693 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
694 unsigned int added = txq->added;
695 unsigned int pushed = added;
696 unsigned int pkts_sent = 0;
697 efx_desc_t *pend = &txq->pend_desc[0];
698 const unsigned int hard_max_fill = EFX_TXQ_LIMIT(txq->ptr_mask + 1);
699 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
700 unsigned int fill_level = added - txq->completed;
703 struct rte_mbuf **pktp;
705 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
709 * If insufficient space for a single packet is present,
710 * we should reap; otherwise, we shouldn't do that all the time
711 * to avoid latency increase
713 reap_done = (fill_level > soft_max_fill);
716 sfc_efx_tx_reap(txq);
718 * Recalculate fill level since 'txq->completed'
719 * might have changed on reap
721 fill_level = added - txq->completed;
724 for (pkts_sent = 0, pktp = &tx_pkts[0];
725 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
726 pkts_sent++, pktp++) {
727 struct rte_mbuf *m_seg = *pktp;
728 size_t pkt_len = m_seg->pkt_len;
729 unsigned int pkt_descs = 0;
733 * Here VLAN TCI is expected to be zero in case if no
734 * DEV_TX_VLAN_OFFLOAD capability is advertised;
735 * if the calling app ignores the absence of
736 * DEV_TX_VLAN_OFFLOAD and pushes VLAN TCI, then
737 * TX_ERROR will occur
739 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
741 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
743 * We expect correct 'pkt->l[2, 3, 4]_len' values
744 * to be set correctly by the caller
746 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
747 &pkt_descs, &pkt_len) != 0) {
748 /* We may have reached this place for
749 * one of the following reasons:
751 * 1) Packet header length is greater
752 * than SFC_TSOH_STD_LEN
753 * 2) TCP header starts at more then
754 * 208 bytes into the frame
756 * We will deceive RTE saying that we have sent
757 * the packet, but we will actually drop it.
758 * Hence, we should revert 'pend' to the
759 * previous state (in case we have added
760 * VLAN descriptor) and start processing
761 * another one packet. But the original
762 * mbuf shouldn't be orphaned
766 rte_pktmbuf_free(*pktp);
772 * We've only added 2 FATSOv2 option descriptors
773 * and 1 descriptor for the linearized packet header.
774 * The outstanding work will be done in the same manner
775 * as for the usual non-TSO path
779 for (; m_seg != NULL; m_seg = m_seg->next) {
780 efsys_dma_addr_t next_frag;
783 seg_len = m_seg->data_len;
784 next_frag = rte_mbuf_data_iova(m_seg);
787 * If we've started TSO transaction few steps earlier,
788 * we'll skip packet header using an offset in the
789 * current segment (which has been set to the
790 * first one containing payload)
797 efsys_dma_addr_t frag_addr = next_frag;
801 * It is assumed here that there is no
802 * limitation on address boundary
803 * crossing by DMA descriptor.
805 frag_len = MIN(seg_len, txq->dma_desc_size_max);
806 next_frag += frag_len;
810 efx_tx_qdesc_dma_create(txq->common,
816 } while (seg_len != 0);
821 fill_level += pkt_descs;
822 if (unlikely(fill_level > hard_max_fill)) {
824 * Our estimation for maximum number of descriptors
825 * required to send a packet seems to be wrong.
826 * Try to reap (if we haven't yet).
829 sfc_efx_tx_reap(txq);
831 fill_level = added - txq->completed;
832 if (fill_level > hard_max_fill) {
842 /* Assign mbuf to the last used desc */
843 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
846 if (likely(pkts_sent > 0)) {
847 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
848 pend - &txq->pend_desc[0],
849 txq->completed, &txq->added);
852 if (likely(pushed != txq->added))
853 efx_tx_qpush(txq->common, txq->added, pushed);
856 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
858 sfc_efx_tx_reap(txq);
866 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
868 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
869 struct rte_eth_dev *eth_dev;
870 struct sfc_adapter *sa;
873 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
874 eth_dev = &rte_eth_devices[dpq->port_id];
876 sa = eth_dev->data->dev_private;
878 SFC_ASSERT(dpq->queue_id < sa->txq_count);
879 txq = sa->txq_info[dpq->queue_id].txq;
881 SFC_ASSERT(txq != NULL);
885 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings;
887 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc,
888 unsigned int *txq_entries,
889 unsigned int *evq_entries,
890 unsigned int *txq_max_fill_level)
892 *txq_entries = nb_tx_desc;
893 *evq_entries = nb_tx_desc;
894 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries);
898 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
900 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
901 const struct rte_pci_addr *pci_addr,
903 const struct sfc_dp_tx_qcreate_info *info,
904 struct sfc_dp_txq **dp_txqp)
906 struct sfc_efx_txq *txq;
907 struct sfc_txq *ctrl_txq;
911 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
912 RTE_CACHE_LINE_SIZE, socket_id);
916 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
919 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
920 EFX_TXQ_LIMIT(info->txq_entries),
921 sizeof(*txq->pend_desc), 0,
923 if (txq->pend_desc == NULL)
924 goto fail_pend_desc_alloc;
927 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
929 sizeof(*txq->sw_ring),
930 RTE_CACHE_LINE_SIZE, socket_id);
931 if (txq->sw_ring == NULL)
932 goto fail_sw_ring_alloc;
934 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
935 if (ctrl_txq->evq->sa->tso) {
936 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
937 info->txq_entries, socket_id);
939 goto fail_alloc_tsoh_objs;
942 txq->evq = ctrl_txq->evq;
943 txq->ptr_mask = info->txq_entries - 1;
944 txq->free_thresh = info->free_thresh;
945 txq->dma_desc_size_max = info->dma_desc_size_max;
950 fail_alloc_tsoh_objs:
951 rte_free(txq->sw_ring);
954 rte_free(txq->pend_desc);
956 fail_pend_desc_alloc:
963 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
965 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
967 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
969 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
970 rte_free(txq->sw_ring);
971 rte_free(txq->pend_desc);
975 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
977 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
978 __rte_unused unsigned int evq_read_ptr,
979 unsigned int txq_desc_index)
981 /* libefx-based datapath is specific to libefx-based PMD */
982 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
983 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
985 txq->common = ctrl_txq->common;
987 txq->pending = txq->completed = txq->added = txq_desc_index;
988 txq->hw_vlan_tci = 0;
990 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
995 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
997 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
998 __rte_unused unsigned int *evq_read_ptr)
1000 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1002 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
1005 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
1007 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
1009 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1012 sfc_efx_tx_reap(txq);
1014 for (txds = 0; txds <= txq->ptr_mask; txds++) {
1015 if (txq->sw_ring[txds].mbuf != NULL) {
1016 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
1017 txq->sw_ring[txds].mbuf = NULL;
1021 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
1024 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status;
1026 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset)
1028 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
1030 if (unlikely(offset > txq->ptr_mask))
1033 if (unlikely(offset >= EFX_TXQ_LIMIT(txq->ptr_mask + 1)))
1034 return RTE_ETH_TX_DESC_UNAVAIL;
1037 * Poll EvQ to derive up-to-date 'txq->pending' figure;
1038 * it is required for the queue to be running, but the
1039 * check is omitted because API design assumes that it
1040 * is the duty of the caller to satisfy all conditions
1042 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) ==
1043 SFC_EFX_TXQ_FLAG_RUNNING);
1044 sfc_ev_qpoll(txq->evq);
1047 * Ring tail is 'txq->pending', and although descriptors
1048 * between 'txq->completed' and 'txq->pending' are still
1049 * in use by the driver, they should be reported as DONE
1051 if (unlikely(offset < (txq->added - txq->pending)))
1052 return RTE_ETH_TX_DESC_FULL;
1055 * There is no separate return value for unused descriptors;
1056 * the latter will be reported as DONE because genuine DONE
1057 * descriptors will be freed anyway in SW on the next burst
1059 return RTE_ETH_TX_DESC_DONE;
1062 struct sfc_dp_tx sfc_efx_tx = {
1064 .name = SFC_KVARG_DATAPATH_EFX,
1068 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
1069 SFC_DP_TX_FEAT_TSO |
1070 SFC_DP_TX_FEAT_MULTI_POOL |
1071 SFC_DP_TX_FEAT_REFCNT |
1072 SFC_DP_TX_FEAT_MULTI_SEG,
1073 .qsize_up_rings = sfc_efx_tx_qsize_up_rings,
1074 .qcreate = sfc_efx_tx_qcreate,
1075 .qdestroy = sfc_efx_tx_qdestroy,
1076 .qstart = sfc_efx_tx_qstart,
1077 .qstop = sfc_efx_tx_qstop,
1078 .qreap = sfc_efx_tx_qreap,
1079 .qdesc_status = sfc_efx_tx_qdesc_status,
1080 .pkt_burst = sfc_efx_xmit_pkts,