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34 #ifndef RTE_PMD_SZEDATA2_H_
35 #define RTE_PMD_SZEDATA2_H_
39 #include <rte_byteorder.h>
43 #define PCI_VENDOR_ID_NETCOPE 0x1b26
46 #define PCI_DEVICE_ID_NETCOPE_COMBO80G 0xcb80
47 #define PCI_DEVICE_ID_NETCOPE_COMBO100G 0xc1c1
48 #define PCI_DEVICE_ID_NETCOPE_COMBO100G2 0xc2c1
50 /* number of PCI resource used by COMBO card */
51 #define PCI_RESOURCE_NUMBER 0
53 /* szedata2_packet header length == 4 bytes == 2B segment size + 2B hw size */
54 #define RTE_SZE2_PACKET_HEADER_SIZE 4
56 #define RTE_SZE2_MMIO_MAX 10
59 * Round 'what' to the nearest larger (or equal) multiple of '8'
60 * (szedata2 packet is aligned to 8 bytes)
62 #define RTE_SZE2_ALIGN8(what) (((what) + ((8) - 1)) & (~((8) - 1)))
64 /*! main handle structure */
67 struct sze2_instance_info *info;
69 void *space[RTE_SZE2_MMIO_MAX];
70 struct szedata_lock lock[2][2];
72 __u32 *rx_asize, *tx_asize;
74 /* szedata_read_next variables - to keep context (ct) */
79 /** initial sze lock ptr */
80 const struct szedata_lock *ct_rx_lck_orig;
81 /** current sze lock ptr (initial or next) */
82 const struct szedata_lock *ct_rx_lck;
83 /** remaining bytes (not read) within current lock */
84 unsigned int ct_rx_rem_bytes;
85 /** current pointer to locked memory */
86 unsigned char *ct_rx_cur_ptr;
88 * allocated buffer to store RX packet if it was split
91 unsigned char *ct_rx_buffer;
92 /** registered function to provide filtering based on hwdata */
93 int (*ct_rx_filter)(u_int16_t hwdata_len, u_char *hwdata);
99 * buffer for tx - packet is prepared here
100 * (in future for burst write)
102 unsigned char *ct_tx_buffer;
103 /** initial sze TX lock ptrs - number according to TX interfaces */
104 const struct szedata_lock **ct_tx_lck_orig;
105 /** current sze TX lock ptrs - number according to TX interfaces */
106 const struct szedata_lock **ct_tx_lck;
107 /** already written bytes in both locks */
108 unsigned int *ct_tx_written_bytes;
109 /** remaining bytes (not written) within current lock */
110 unsigned int *ct_tx_rem_bytes;
111 /** current pointers to locked memory */
112 unsigned char **ct_tx_cur_ptr;
113 /** NUMA node closest to PCIe device, or -1 */
117 static inline uint32_t
118 szedata2_read32(const volatile void *addr)
120 return rte_le_to_cpu_32(rte_read32(addr));
124 szedata2_write32(uint32_t value, volatile void *addr)
126 rte_write32(rte_cpu_to_le_32(value), addr);
129 #define SZEDATA2_PCI_RESOURCE_PTR(rsc, offset, type) \
130 ((type)(((uint8_t *)(rsc)->addr) + (offset)))
132 enum szedata2_link_speed {
133 SZEDATA2_LINK_SPEED_DEFAULT = 0,
134 SZEDATA2_LINK_SPEED_10G,
135 SZEDATA2_LINK_SPEED_40G,
136 SZEDATA2_LINK_SPEED_100G,
139 enum szedata2_mac_check_mode {
140 SZEDATA2_MAC_CHMODE_PROMISC = 0x0,
141 SZEDATA2_MAC_CHMODE_ONLY_VALID = 0x1,
142 SZEDATA2_MAC_CHMODE_ALL_BROADCAST = 0x2,
143 SZEDATA2_MAC_CHMODE_ALL_MULTICAST = 0x3,
147 * Maximum possible number of MAC addresses (limited by IBUF status
148 * register value MAC_COUNT which has 5 bits).
150 #define SZEDATA2_IBUF_MAX_MAC_COUNT 32
153 * Structure describes IBUF address space
155 struct szedata2_ibuf {
156 /** Total Received Frames Counter low part */
157 uint32_t trfcl; /**< 0x00 */
158 /** Correct Frames Counter low part */
159 uint32_t cfcl; /**< 0x04 */
160 /** Discarded Frames Counter low part */
161 uint32_t dfcl; /**< 0x08 */
162 /** Counter of frames discarded due to buffer overflow low part */
163 uint32_t bodfcl; /**< 0x0C */
164 /** Total Received Frames Counter high part */
165 uint32_t trfch; /**< 0x10 */
166 /** Correct Frames Counter high part */
167 uint32_t cfch; /**< 0x14 */
168 /** Discarded Frames Counter high part */
169 uint32_t dfch; /**< 0x18 */
170 /** Counter of frames discarded due to buffer overflow high part */
171 uint32_t bodfch; /**< 0x1C */
172 /** IBUF enable register */
173 uint32_t ibuf_en; /**< 0x20 */
174 /** Error mask register */
175 uint32_t err_mask; /**< 0x24 */
176 /** IBUF status register */
177 uint32_t ibuf_st; /**< 0x28 */
178 /** IBUF command register */
179 uint32_t ibuf_cmd; /**< 0x2C */
180 /** Minimum frame length allowed */
181 uint32_t mfla; /**< 0x30 */
183 uint32_t mtu; /**< 0x34 */
184 /** MAC address check mode */
185 uint32_t mac_chmode; /**< 0x38 */
186 /** Octets Received OK Counter low part */
187 uint32_t orocl; /**< 0x3C */
188 /** Octets Received OK Counter high part */
189 uint32_t oroch; /**< 0x40 */
191 uint8_t reserved[60]; /**< 0x4C */
192 /** IBUF memory for MAC addresses */
193 uint32_t mac_mem[2 * SZEDATA2_IBUF_MAX_MAC_COUNT]; /**< 0x80 */
198 * true if IBUF is enabled
199 * false if IBUF is disabled
202 ibuf_is_enabled(const volatile struct szedata2_ibuf *ibuf)
204 return ((szedata2_read32(&ibuf->ibuf_en) & 0x1) != 0) ? true : false;
211 ibuf_enable(volatile struct szedata2_ibuf *ibuf)
213 szedata2_write32(szedata2_read32(&ibuf->ibuf_en) | 0x1, &ibuf->ibuf_en);
220 ibuf_disable(volatile struct szedata2_ibuf *ibuf)
222 szedata2_write32(szedata2_read32(&ibuf->ibuf_en) & ~0x1,
228 * true if ibuf link is up
229 * false if ibuf link is down
232 ibuf_is_link_up(const volatile struct szedata2_ibuf *ibuf)
234 return ((szedata2_read32(&ibuf->ibuf_st) & 0x80) != 0) ? true : false;
239 * MAC address check mode
241 static inline enum szedata2_mac_check_mode
242 ibuf_mac_mode_read(const volatile struct szedata2_ibuf *ibuf)
244 switch (szedata2_read32(&ibuf->mac_chmode) & 0x3) {
246 return SZEDATA2_MAC_CHMODE_PROMISC;
248 return SZEDATA2_MAC_CHMODE_ONLY_VALID;
250 return SZEDATA2_MAC_CHMODE_ALL_BROADCAST;
252 return SZEDATA2_MAC_CHMODE_ALL_MULTICAST;
254 return SZEDATA2_MAC_CHMODE_PROMISC;
259 * Writes "mode" in MAC address check mode register.
262 ibuf_mac_mode_write(volatile struct szedata2_ibuf *ibuf,
263 enum szedata2_mac_check_mode mode)
265 szedata2_write32((szedata2_read32(&ibuf->mac_chmode) & ~0x3) | mode,
270 * Structure describes OBUF address space
272 struct szedata2_obuf {
273 /** Total Sent Frames Counter low part */
274 uint32_t tsfcl; /**< 0x00 */
275 /** Octets Sent Counter low part */
276 uint32_t oscl; /**< 0x04 */
277 /** Total Discarded Frames Counter low part */
278 uint32_t tdfcl; /**< 0x08 */
280 uint32_t reserved1; /**< 0x0C */
281 /** Total Sent Frames Counter high part */
282 uint32_t tsfch; /**< 0x10 */
283 /** Octets Sent Counter high part */
284 uint32_t osch; /**< 0x14 */
285 /** Total Discarded Frames Counter high part */
286 uint32_t tdfch; /**< 0x18 */
288 uint32_t reserved2; /**< 0x1C */
289 /** OBUF enable register */
290 uint32_t obuf_en; /**< 0x20 */
292 uint64_t reserved3; /**< 0x24 */
293 /** OBUF control register */
294 uint32_t ctrl; /**< 0x2C */
295 /** OBUF status register */
296 uint32_t obuf_st; /**< 0x30 */
301 * true if OBUF is enabled
302 * false if OBUF is disabled
305 obuf_is_enabled(const volatile struct szedata2_obuf *obuf)
307 return ((szedata2_read32(&obuf->obuf_en) & 0x1) != 0) ? true : false;
314 obuf_enable(volatile struct szedata2_obuf *obuf)
316 szedata2_write32(szedata2_read32(&obuf->obuf_en) | 0x1, &obuf->obuf_en);
323 obuf_disable(volatile struct szedata2_obuf *obuf)
325 szedata2_write32(szedata2_read32(&obuf->obuf_en) & ~0x1,
330 * Function takes value from IBUF status register. Values in IBUF and OBUF
333 * @return Link speed constant.
335 static inline enum szedata2_link_speed
336 get_link_speed(const volatile struct szedata2_ibuf *ibuf)
338 uint32_t speed = (szedata2_read32(&ibuf->ibuf_st) & 0x70) >> 4;
341 return SZEDATA2_LINK_SPEED_10G;
343 return SZEDATA2_LINK_SPEED_40G;
345 return SZEDATA2_LINK_SPEED_100G;
347 return SZEDATA2_LINK_SPEED_DEFAULT;
352 * IBUFs and OBUFs can generally be located at different offsets in different
354 * This part defines base offsets of IBUFs and OBUFs through various firmwares.
355 * Currently one firmware type is supported.
356 * Type of firmware is set through configuration option
357 * CONFIG_RTE_LIBRTE_PMD_SZEDATA_AS.
358 * Possible values are:
364 #if !defined(RTE_LIBRTE_PMD_SZEDATA2_AS)
365 #error "RTE_LIBRTE_PMD_SZEDATA2_AS has to be defined"
366 #elif RTE_LIBRTE_PMD_SZEDATA2_AS == 0
369 * IBUF offset from the beginning of PCI resource address space.
371 #define SZEDATA2_IBUF_BASE_OFF 0x8000
375 #define SZEDATA2_IBUF_SIZE 0x200
378 * OBUF offset from the beginning of PCI resource address space.
380 #define SZEDATA2_OBUF_BASE_OFF 0x9000
384 #define SZEDATA2_OBUF_SIZE 0x100
387 #error "RTE_LIBRTE_PMD_SZEDATA2_AS has wrong value, see comments in config file"