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34 #ifndef RTE_PMD_SZEDATA2_H_
35 #define RTE_PMD_SZEDATA2_H_
39 #include <rte_byteorder.h>
42 #define PCI_VENDOR_ID_NETCOPE 0x1b26
45 #define PCI_DEVICE_ID_NETCOPE_COMBO80G 0xcb80
46 #define PCI_DEVICE_ID_NETCOPE_COMBO100G 0xc1c1
47 #define PCI_DEVICE_ID_NETCOPE_COMBO100G2 0xc2c1
49 /* number of PCI resource used by COMBO card */
50 #define PCI_RESOURCE_NUMBER 0
52 /* szedata2_packet header length == 4 bytes == 2B segment size + 2B hw size */
53 #define RTE_SZE2_PACKET_HEADER_SIZE 4
55 #define RTE_SZE2_MMIO_MAX 10
58 * Round 'what' to the nearest larger (or equal) multiple of '8'
59 * (szedata2 packet is aligned to 8 bytes)
61 #define RTE_SZE2_ALIGN8(what) (((what) + ((8) - 1)) & (~((8) - 1)))
63 /*! main handle structure */
66 struct sze2_instance_info *info;
68 void *space[RTE_SZE2_MMIO_MAX];
69 struct szedata_lock lock[2][2];
71 __u32 *rx_asize, *tx_asize;
73 /* szedata_read_next variables - to keep context (ct) */
78 /** initial sze lock ptr */
79 const struct szedata_lock *ct_rx_lck_orig;
80 /** current sze lock ptr (initial or next) */
81 const struct szedata_lock *ct_rx_lck;
82 /** remaining bytes (not read) within current lock */
83 unsigned int ct_rx_rem_bytes;
84 /** current pointer to locked memory */
85 unsigned char *ct_rx_cur_ptr;
87 * allocated buffer to store RX packet if it was split
90 unsigned char *ct_rx_buffer;
91 /** registered function to provide filtering based on hwdata */
92 int (*ct_rx_filter)(u_int16_t hwdata_len, u_char *hwdata);
98 * buffer for tx - packet is prepared here
99 * (in future for burst write)
101 unsigned char *ct_tx_buffer;
102 /** initial sze TX lock ptrs - number according to TX interfaces */
103 const struct szedata_lock **ct_tx_lck_orig;
104 /** current sze TX lock ptrs - number according to TX interfaces */
105 const struct szedata_lock **ct_tx_lck;
106 /** already written bytes in both locks */
107 unsigned int *ct_tx_written_bytes;
108 /** remaining bytes (not written) within current lock */
109 unsigned int *ct_tx_rem_bytes;
110 /** current pointers to locked memory */
111 unsigned char **ct_tx_cur_ptr;
112 /** NUMA node closest to PCIe device, or -1 */
117 * @return Byte from PCI resource at offset "offset".
119 static inline uint8_t
120 pci_resource_read8(struct rte_eth_dev *dev, uint32_t offset)
122 return *((uint8_t *)((uint8_t *)
123 dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
128 * @return Two bytes from PCI resource starting at offset "offset".
130 static inline uint16_t
131 pci_resource_read16(struct rte_eth_dev *dev, uint32_t offset)
133 return rte_le_to_cpu_16(*((uint16_t *)((uint8_t *)
134 dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
139 * @return Four bytes from PCI resource starting at offset "offset".
141 static inline uint32_t
142 pci_resource_read32(struct rte_eth_dev *dev, uint32_t offset)
144 return rte_le_to_cpu_32(*((uint32_t *)((uint8_t *)
145 dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
150 * @return Eight bytes from PCI resource starting at offset "offset".
152 static inline uint64_t
153 pci_resource_read64(struct rte_eth_dev *dev, uint32_t offset)
155 return rte_le_to_cpu_64(*((uint64_t *)((uint8_t *)
156 dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
161 * Write one byte to PCI resource address space at offset "offset".
164 pci_resource_write8(struct rte_eth_dev *dev, uint32_t offset, uint8_t val)
166 *((uint8_t *)((uint8_t *)
167 dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
172 * Write two bytes to PCI resource address space at offset "offset".
175 pci_resource_write16(struct rte_eth_dev *dev, uint32_t offset, uint16_t val)
177 *((uint16_t *)((uint8_t *)
178 dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
179 offset)) = rte_cpu_to_le_16(val);
183 * Write four bytes to PCI resource address space at offset "offset".
186 pci_resource_write32(struct rte_eth_dev *dev, uint32_t offset, uint32_t val)
188 *((uint32_t *)((uint8_t *)
189 dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
190 offset)) = rte_cpu_to_le_32(val);
194 * Write eight bytes to PCI resource address space at offset "offset".
197 pci_resource_write64(struct rte_eth_dev *dev, uint32_t offset, uint64_t val)
199 *((uint64_t *)((uint8_t *)
200 dev->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr +
201 offset)) = rte_cpu_to_le_64(val);
204 #define SZEDATA2_PCI_RESOURCE_PTR(dev, offset, type) \
205 ((type)((uint8_t *) \
206 ((dev)->pci_dev->mem_resource[PCI_RESOURCE_NUMBER].addr) \
209 enum szedata2_link_speed {
210 SZEDATA2_LINK_SPEED_DEFAULT = 0,
211 SZEDATA2_LINK_SPEED_10G,
212 SZEDATA2_LINK_SPEED_40G,
213 SZEDATA2_LINK_SPEED_100G,
217 * Structure describes CGMII IBUF address space
219 struct szedata2_cgmii_ibuf {
220 /** Total Received Frames Counter low part */
222 /** Correct Frames Counter low part */
224 /** Discarded Frames Counter low part */
226 /** Counter of frames discarded due to buffer overflow low part */
228 /** Total Received Frames Counter high part */
230 /** Correct Frames Counter high part */
232 /** Discarded Frames Counter high part */
234 /** Counter of frames discarded due to buffer overflow high part */
236 /** IBUF enable register */
238 /** Error mask register */
240 /** IBUF status register */
242 /** IBUF command register */
244 /** Minimum frame length allowed */
248 /** MAC address check mode */
250 /** Octets Received OK Counter low part */
252 /** Octets Received OK Counter high part */
256 /* Offset of CGMII IBUF memory for MAC addresses */
257 #define SZEDATA2_CGMII_IBUF_MAC_MEM_OFF 0x80
261 * true if IBUF is enabled
262 * false if IBUF is disabled
265 cgmii_ibuf_is_enabled(volatile struct szedata2_cgmii_ibuf *ibuf)
267 return ((rte_le_to_cpu_32(ibuf->ibuf_en) & 0x1) != 0) ? true : false;
274 cgmii_ibuf_enable(volatile struct szedata2_cgmii_ibuf *ibuf)
277 rte_cpu_to_le_32(rte_le_to_cpu_32(ibuf->ibuf_en) | 0x1);
284 cgmii_ibuf_disable(volatile struct szedata2_cgmii_ibuf *ibuf)
287 rte_cpu_to_le_32(rte_le_to_cpu_32(ibuf->ibuf_en) & ~0x1);
292 * true if ibuf link is up
293 * false if ibuf link is down
296 cgmii_ibuf_is_link_up(volatile struct szedata2_cgmii_ibuf *ibuf)
298 return ((rte_le_to_cpu_32(ibuf->ibuf_st) & 0x80) != 0) ? true : false;
302 * Structure describes CGMII OBUF address space
304 struct szedata2_cgmii_obuf {
305 /** Total Sent Frames Counter low part */
307 /** Octets Sent Counter low part */
309 /** Total Discarded Frames Counter low part */
313 /** Total Sent Frames Counter high part */
315 /** Octets Sent Counter high part */
317 /** Total Discarded Frames Counter high part */
321 /** OBUF enable register */
325 /** OBUF control register */
327 /** OBUF status register */
333 * true if OBUF is enabled
334 * false if OBUF is disabled
337 cgmii_obuf_is_enabled(volatile struct szedata2_cgmii_obuf *obuf)
339 return ((rte_le_to_cpu_32(obuf->obuf_en) & 0x1) != 0) ? true : false;
346 cgmii_obuf_enable(volatile struct szedata2_cgmii_obuf *obuf)
349 rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) | 0x1);
356 cgmii_obuf_disable(volatile struct szedata2_cgmii_obuf *obuf)
359 rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) & ~0x1);
363 * Function takes value from IBUF status register. Values in IBUF and OBUF
366 * @return Link speed constant.
368 static inline enum szedata2_link_speed
369 cgmii_link_speed(volatile struct szedata2_cgmii_ibuf *ibuf)
371 uint32_t speed = (rte_le_to_cpu_32(ibuf->ibuf_st) & 0x70) >> 4;
374 return SZEDATA2_LINK_SPEED_10G;
376 return SZEDATA2_LINK_SPEED_40G;
378 return SZEDATA2_LINK_SPEED_100G;
380 return SZEDATA2_LINK_SPEED_DEFAULT;
385 * IBUFs and OBUFs can generally be located at different offsets in different
387 * This part defines base offsets of IBUFs and OBUFs through various firmwares.
388 * Currently one firmware type is supported.
389 * Type of firmware is set through configuration option
390 * CONFIG_RTE_LIBRTE_PMD_SZEDATA_AS.
391 * Possible values are:
397 #if !defined(RTE_LIBRTE_PMD_SZEDATA2_AS)
398 #error "RTE_LIBRTE_PMD_SZEDATA2_AS has to be defined"
399 #elif RTE_LIBRTE_PMD_SZEDATA2_AS == 0
402 * CGMII IBUF offset from the beginning of PCI resource address space.
404 #define SZEDATA2_CGMII_IBUF_BASE_OFF 0x8000
406 * Size of CGMII IBUF.
408 #define SZEDATA2_CGMII_IBUF_SIZE 0x200
411 * GCMII OBUF offset from the beginning of PCI resource address space.
413 #define SZEDATA2_CGMII_OBUF_BASE_OFF 0x9000
415 * Size of CGMII OBUF.
417 #define SZEDATA2_CGMII_OBUF_SIZE 0x100
420 #error "RTE_LIBRTE_PMD_SZEDATA2_AS has wrong value, see comments in config file"