4 * Copyright (c) 2015 - 2016 CESNET
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of CESNET nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef RTE_PMD_SZEDATA2_H_
35 #define RTE_PMD_SZEDATA2_H_
39 #include <rte_byteorder.h>
42 #define PCI_VENDOR_ID_NETCOPE 0x1b26
45 #define PCI_DEVICE_ID_NETCOPE_COMBO80G 0xcb80
46 #define PCI_DEVICE_ID_NETCOPE_COMBO100G 0xc1c1
47 #define PCI_DEVICE_ID_NETCOPE_COMBO100G2 0xc2c1
49 /* number of PCI resource used by COMBO card */
50 #define PCI_RESOURCE_NUMBER 0
52 /* szedata2_packet header length == 4 bytes == 2B segment size + 2B hw size */
53 #define RTE_SZE2_PACKET_HEADER_SIZE 4
55 #define RTE_SZE2_MMIO_MAX 10
58 * Round 'what' to the nearest larger (or equal) multiple of '8'
59 * (szedata2 packet is aligned to 8 bytes)
61 #define RTE_SZE2_ALIGN8(what) (((what) + ((8) - 1)) & (~((8) - 1)))
63 /*! main handle structure */
66 struct sze2_instance_info *info;
68 void *space[RTE_SZE2_MMIO_MAX];
69 struct szedata_lock lock[2][2];
71 __u32 *rx_asize, *tx_asize;
73 /* szedata_read_next variables - to keep context (ct) */
78 /** initial sze lock ptr */
79 const struct szedata_lock *ct_rx_lck_orig;
80 /** current sze lock ptr (initial or next) */
81 const struct szedata_lock *ct_rx_lck;
82 /** remaining bytes (not read) within current lock */
83 unsigned int ct_rx_rem_bytes;
84 /** current pointer to locked memory */
85 unsigned char *ct_rx_cur_ptr;
87 * allocated buffer to store RX packet if it was split
90 unsigned char *ct_rx_buffer;
91 /** registered function to provide filtering based on hwdata */
92 int (*ct_rx_filter)(u_int16_t hwdata_len, u_char *hwdata);
98 * buffer for tx - packet is prepared here
99 * (in future for burst write)
101 unsigned char *ct_tx_buffer;
102 /** initial sze TX lock ptrs - number according to TX interfaces */
103 const struct szedata_lock **ct_tx_lck_orig;
104 /** current sze TX lock ptrs - number according to TX interfaces */
105 const struct szedata_lock **ct_tx_lck;
106 /** already written bytes in both locks */
107 unsigned int *ct_tx_written_bytes;
108 /** remaining bytes (not written) within current lock */
109 unsigned int *ct_tx_rem_bytes;
110 /** current pointers to locked memory */
111 unsigned char **ct_tx_cur_ptr;
112 /** NUMA node closest to PCIe device, or -1 */
117 * @return Byte from PCI resource at offset "offset".
119 static inline uint8_t
120 pci_resource_read8(struct rte_mem_resource *rsc, uint32_t offset)
122 return *((uint8_t *)((uint8_t *)rsc->addr + offset));
126 * @return Two bytes from PCI resource starting at offset "offset".
128 static inline uint16_t
129 pci_resource_read16(struct rte_mem_resource *rsc, uint32_t offset)
131 return rte_le_to_cpu_16(*((uint16_t *)((uint8_t *)rsc->addr +
136 * @return Four bytes from PCI resource starting at offset "offset".
138 static inline uint32_t
139 pci_resource_read32(struct rte_mem_resource *rsc, uint32_t offset)
141 return rte_le_to_cpu_32(*((uint32_t *)((uint8_t *)rsc->addr +
146 * @return Eight bytes from PCI resource starting at offset "offset".
148 static inline uint64_t
149 pci_resource_read64(struct rte_mem_resource *rsc, uint32_t offset)
151 return rte_le_to_cpu_64(*((uint64_t *)((uint8_t *)rsc->addr +
156 * Write one byte to PCI resource address space at offset "offset".
159 pci_resource_write8(struct rte_mem_resource *rsc, uint32_t offset, uint8_t val)
161 *((uint8_t *)((uint8_t *)rsc->addr + offset)) = val;
165 * Write two bytes to PCI resource address space at offset "offset".
168 pci_resource_write16(struct rte_mem_resource *rsc, uint32_t offset,
171 *((uint16_t *)((uint8_t *)rsc->addr + offset)) = rte_cpu_to_le_16(val);
175 * Write four bytes to PCI resource address space at offset "offset".
178 pci_resource_write32(struct rte_mem_resource *rsc, uint32_t offset,
181 *((uint32_t *)((uint8_t *)rsc->addr + offset)) = rte_cpu_to_le_32(val);
185 * Write eight bytes to PCI resource address space at offset "offset".
188 pci_resource_write64(struct rte_mem_resource *rsc, uint32_t offset,
191 *((uint64_t *)((uint8_t *)rsc->addr + offset)) = rte_cpu_to_le_64(val);
194 #define SZEDATA2_PCI_RESOURCE_PTR(rsc, offset, type) \
195 ((type)(((uint8_t *)(rsc)->addr) + (offset)))
197 enum szedata2_link_speed {
198 SZEDATA2_LINK_SPEED_DEFAULT = 0,
199 SZEDATA2_LINK_SPEED_10G,
200 SZEDATA2_LINK_SPEED_40G,
201 SZEDATA2_LINK_SPEED_100G,
204 enum szedata2_mac_check_mode {
205 SZEDATA2_MAC_CHMODE_PROMISC = 0x0,
206 SZEDATA2_MAC_CHMODE_ONLY_VALID = 0x1,
207 SZEDATA2_MAC_CHMODE_ALL_BROADCAST = 0x2,
208 SZEDATA2_MAC_CHMODE_ALL_MULTICAST = 0x3,
212 * Structure describes CGMII IBUF address space
214 struct szedata2_cgmii_ibuf {
215 /** Total Received Frames Counter low part */
217 /** Correct Frames Counter low part */
219 /** Discarded Frames Counter low part */
221 /** Counter of frames discarded due to buffer overflow low part */
223 /** Total Received Frames Counter high part */
225 /** Correct Frames Counter high part */
227 /** Discarded Frames Counter high part */
229 /** Counter of frames discarded due to buffer overflow high part */
231 /** IBUF enable register */
233 /** Error mask register */
235 /** IBUF status register */
237 /** IBUF command register */
239 /** Minimum frame length allowed */
243 /** MAC address check mode */
245 /** Octets Received OK Counter low part */
247 /** Octets Received OK Counter high part */
251 /* Offset of CGMII IBUF memory for MAC addresses */
252 #define SZEDATA2_CGMII_IBUF_MAC_MEM_OFF 0x80
256 * true if IBUF is enabled
257 * false if IBUF is disabled
260 cgmii_ibuf_is_enabled(volatile struct szedata2_cgmii_ibuf *ibuf)
262 return ((rte_le_to_cpu_32(ibuf->ibuf_en) & 0x1) != 0) ? true : false;
269 cgmii_ibuf_enable(volatile struct szedata2_cgmii_ibuf *ibuf)
272 rte_cpu_to_le_32(rte_le_to_cpu_32(ibuf->ibuf_en) | 0x1);
279 cgmii_ibuf_disable(volatile struct szedata2_cgmii_ibuf *ibuf)
282 rte_cpu_to_le_32(rte_le_to_cpu_32(ibuf->ibuf_en) & ~0x1);
287 * true if ibuf link is up
288 * false if ibuf link is down
291 cgmii_ibuf_is_link_up(volatile struct szedata2_cgmii_ibuf *ibuf)
293 return ((rte_le_to_cpu_32(ibuf->ibuf_st) & 0x80) != 0) ? true : false;
298 * MAC address check mode
300 static inline enum szedata2_mac_check_mode
301 cgmii_ibuf_mac_mode_read(volatile struct szedata2_cgmii_ibuf *ibuf)
303 switch (rte_le_to_cpu_32(ibuf->mac_chmode) & 0x3) {
305 return SZEDATA2_MAC_CHMODE_PROMISC;
307 return SZEDATA2_MAC_CHMODE_ONLY_VALID;
309 return SZEDATA2_MAC_CHMODE_ALL_BROADCAST;
311 return SZEDATA2_MAC_CHMODE_ALL_MULTICAST;
313 return SZEDATA2_MAC_CHMODE_PROMISC;
318 * Writes "mode" in MAC address check mode register.
321 cgmii_ibuf_mac_mode_write(volatile struct szedata2_cgmii_ibuf *ibuf,
322 enum szedata2_mac_check_mode mode)
324 ibuf->mac_chmode = rte_cpu_to_le_32(
325 (rte_le_to_cpu_32(ibuf->mac_chmode) & ~0x3) | mode);
329 * Structure describes CGMII OBUF address space
331 struct szedata2_cgmii_obuf {
332 /** Total Sent Frames Counter low part */
334 /** Octets Sent Counter low part */
336 /** Total Discarded Frames Counter low part */
340 /** Total Sent Frames Counter high part */
342 /** Octets Sent Counter high part */
344 /** Total Discarded Frames Counter high part */
348 /** OBUF enable register */
352 /** OBUF control register */
354 /** OBUF status register */
360 * true if OBUF is enabled
361 * false if OBUF is disabled
364 cgmii_obuf_is_enabled(volatile struct szedata2_cgmii_obuf *obuf)
366 return ((rte_le_to_cpu_32(obuf->obuf_en) & 0x1) != 0) ? true : false;
373 cgmii_obuf_enable(volatile struct szedata2_cgmii_obuf *obuf)
376 rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) | 0x1);
383 cgmii_obuf_disable(volatile struct szedata2_cgmii_obuf *obuf)
386 rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) & ~0x1);
390 * Function takes value from IBUF status register. Values in IBUF and OBUF
393 * @return Link speed constant.
395 static inline enum szedata2_link_speed
396 cgmii_link_speed(volatile struct szedata2_cgmii_ibuf *ibuf)
398 uint32_t speed = (rte_le_to_cpu_32(ibuf->ibuf_st) & 0x70) >> 4;
401 return SZEDATA2_LINK_SPEED_10G;
403 return SZEDATA2_LINK_SPEED_40G;
405 return SZEDATA2_LINK_SPEED_100G;
407 return SZEDATA2_LINK_SPEED_DEFAULT;
412 * IBUFs and OBUFs can generally be located at different offsets in different
414 * This part defines base offsets of IBUFs and OBUFs through various firmwares.
415 * Currently one firmware type is supported.
416 * Type of firmware is set through configuration option
417 * CONFIG_RTE_LIBRTE_PMD_SZEDATA_AS.
418 * Possible values are:
424 #if !defined(RTE_LIBRTE_PMD_SZEDATA2_AS)
425 #error "RTE_LIBRTE_PMD_SZEDATA2_AS has to be defined"
426 #elif RTE_LIBRTE_PMD_SZEDATA2_AS == 0
429 * CGMII IBUF offset from the beginning of PCI resource address space.
431 #define SZEDATA2_CGMII_IBUF_BASE_OFF 0x8000
433 * Size of CGMII IBUF.
435 #define SZEDATA2_CGMII_IBUF_SIZE 0x200
438 * GCMII OBUF offset from the beginning of PCI resource address space.
440 #define SZEDATA2_CGMII_OBUF_BASE_OFF 0x9000
442 * Size of CGMII OBUF.
444 #define SZEDATA2_CGMII_OBUF_SIZE 0x100
447 #error "RTE_LIBRTE_PMD_SZEDATA2_AS has wrong value, see comments in config file"