4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #ifndef _THUNDERX_NICVF_HW_H
34 #define _THUNDERX_NICVF_HW_H
38 #include "nicvf_hw_defs.h"
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
41 #define PCI_DEVICE_ID_THUNDERX_PASS1_NICVF 0x0011
42 #define PCI_DEVICE_ID_THUNDERX_PASS2_NICVF 0xA034
43 #define PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF 0xA11E
44 #define PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF 0xA134
46 #define NICVF_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
48 #define NICVF_GET_RX_STATS(reg) \
49 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
50 #define NICVF_GET_TX_STATS(reg) \
51 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
53 #define NICVF_PASS1 (PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF)
54 #define NICVF_PASS2 (PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF)
56 #define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
65 NICVF_ERR_SET_QS = -8191,/* -8191 */
66 NICVF_ERR_RESET_QS, /* -8190 */
67 NICVF_ERR_REG_POLL, /* -8189 */
68 NICVF_ERR_RBDR_RESET, /* -8188 */
69 NICVF_ERR_RBDR_DISABLE, /* -8187 */
70 NICVF_ERR_RBDR_PREFETCH, /* -8186 */
71 NICVF_ERR_RBDR_RESET1, /* -8185 */
72 NICVF_ERR_RBDR_RESET2, /* -8184 */
73 NICVF_ERR_RQ_CLAIM, /* -8183 */
74 NICVF_ERR_RQ_PF_CFG, /* -8182 */
75 NICVF_ERR_RQ_BP_CFG, /* -8181 */
76 NICVF_ERR_RQ_DROP_CFG, /* -8180 */
77 NICVF_ERR_CQ_DISABLE, /* -8179 */
78 NICVF_ERR_CQ_RESET, /* -8178 */
79 NICVF_ERR_SQ_DISABLE, /* -8177 */
80 NICVF_ERR_SQ_RESET, /* -8176 */
81 NICVF_ERR_SQ_PF_CFG, /* -8175 */
82 NICVF_ERR_LOOPBACK_CFG, /* -8174 */
83 NICVF_ERR_BASE_INIT, /* -8173 */
84 NICVF_ERR_RSS_TBL_UPDATE,/* -8172 */
85 NICVF_ERR_RSS_GET_SZ, /* -8171 */
88 typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *opaque);
90 struct nicvf_hw_rx_qstats {
92 uint64_t q_rx_packets;
95 struct nicvf_hw_tx_qstats {
97 uint64_t q_tx_packets;
100 struct nicvf_hw_stats {
102 uint64_t rx_ucast_frames;
103 uint64_t rx_bcast_frames;
104 uint64_t rx_mcast_frames;
105 uint64_t rx_fcs_errors;
106 uint64_t rx_l2_errors;
107 uint64_t rx_drop_red;
108 uint64_t rx_drop_red_bytes;
109 uint64_t rx_drop_overrun;
110 uint64_t rx_drop_overrun_bytes;
111 uint64_t rx_drop_bcast;
112 uint64_t rx_drop_mcast;
113 uint64_t rx_drop_l3_bcast;
114 uint64_t rx_drop_l3_mcast;
116 uint64_t tx_bytes_ok;
117 uint64_t tx_ucast_frames_ok;
118 uint64_t tx_bcast_frames_ok;
119 uint64_t tx_mcast_frames_ok;
123 struct nicvf_rss_reta_info {
126 uint8_t ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
129 /* Common structs used in DPDK and base layer are defined in DPDK layer */
130 #include "../nicvf_struct.h"
132 NICVF_STATIC_ASSERT(sizeof(struct nicvf_rbdr) <= 128);
133 NICVF_STATIC_ASSERT(sizeof(struct nicvf_txq) <= 128);
134 NICVF_STATIC_ASSERT(sizeof(struct nicvf_rxq) <= 128);
137 nicvf_reg_write(struct nicvf *nic, uint32_t offset, uint64_t val)
139 nicvf_addr_write(nic->reg_base + offset, val);
142 static inline uint64_t
143 nicvf_reg_read(struct nicvf *nic, uint32_t offset)
145 return nicvf_addr_read(nic->reg_base + offset);
148 static inline uintptr_t
149 nicvf_qset_base(struct nicvf *nic, uint32_t qidx)
151 return nic->reg_base + (qidx << NIC_Q_NUM_SHIFT);
155 nicvf_queue_reg_write(struct nicvf *nic, uint32_t offset, uint32_t qidx,
158 nicvf_addr_write(nicvf_qset_base(nic, qidx) + offset, val);
161 static inline uint64_t
162 nicvf_queue_reg_read(struct nicvf *nic, uint32_t offset, uint32_t qidx)
164 return nicvf_addr_read(nicvf_qset_base(nic, qidx) + offset);
168 nicvf_disable_all_interrupts(struct nicvf *nic)
170 nicvf_reg_write(nic, NIC_VF_ENA_W1C, NICVF_INTR_ALL_MASK);
171 nicvf_reg_write(nic, NIC_VF_INT, NICVF_INTR_ALL_MASK);
174 static inline uint32_t
175 nicvf_hw_version(struct nicvf *nic)
177 return nic->subsystem_device_id;
180 static inline uint64_t
181 nicvf_hw_cap(struct nicvf *nic)
186 int nicvf_base_init(struct nicvf *nic);
188 int nicvf_reg_get_count(void);
189 int nicvf_reg_poll_interrupts(struct nicvf *nic);
190 int nicvf_reg_dump(struct nicvf *nic, uint64_t *data);
192 int nicvf_qset_config(struct nicvf *nic);
193 int nicvf_qset_reclaim(struct nicvf *nic);
195 int nicvf_qset_rbdr_config(struct nicvf *nic, uint16_t qidx);
196 int nicvf_qset_rbdr_reclaim(struct nicvf *nic, uint16_t qidx);
197 int nicvf_qset_rbdr_precharge(struct nicvf *nic, uint16_t ridx,
198 rbdr_pool_get_handler handler, void *opaque,
200 int nicvf_qset_rbdr_active(struct nicvf *nic, uint16_t qidx);
202 int nicvf_qset_rq_config(struct nicvf *nic, uint16_t qidx,
203 struct nicvf_rxq *rxq);
204 int nicvf_qset_rq_reclaim(struct nicvf *nic, uint16_t qidx);
206 int nicvf_qset_cq_config(struct nicvf *nic, uint16_t qidx,
207 struct nicvf_rxq *rxq);
208 int nicvf_qset_cq_reclaim(struct nicvf *nic, uint16_t qidx);
210 int nicvf_qset_sq_config(struct nicvf *nic, uint16_t qidx,
211 struct nicvf_txq *txq);
212 int nicvf_qset_sq_reclaim(struct nicvf *nic, uint16_t qidx);
214 uint32_t nicvf_qsize_rbdr_roundup(uint32_t val);
215 uint32_t nicvf_qsize_cq_roundup(uint32_t val);
216 uint32_t nicvf_qsize_sq_roundup(uint32_t val);
218 void nicvf_vlan_hw_strip(struct nicvf *nic, bool enable);
220 int nicvf_rss_config(struct nicvf *nic, uint32_t qcnt, uint64_t cfg);
221 int nicvf_rss_term(struct nicvf *nic);
223 int nicvf_rss_reta_update(struct nicvf *nic, uint8_t *tbl, uint32_t max_count);
224 int nicvf_rss_reta_query(struct nicvf *nic, uint8_t *tbl, uint32_t max_count);
226 void nicvf_rss_set_key(struct nicvf *nic, uint8_t *key);
227 void nicvf_rss_get_key(struct nicvf *nic, uint8_t *key);
229 void nicvf_rss_set_cfg(struct nicvf *nic, uint64_t val);
230 uint64_t nicvf_rss_get_cfg(struct nicvf *nic);
232 int nicvf_loopback_config(struct nicvf *nic, bool enable);
234 void nicvf_hw_get_stats(struct nicvf *nic, struct nicvf_hw_stats *stats);
235 void nicvf_hw_get_rx_qstats(struct nicvf *nic,
236 struct nicvf_hw_rx_qstats *qstats, uint16_t qidx);
237 void nicvf_hw_get_tx_qstats(struct nicvf *nic,
238 struct nicvf_hw_tx_qstats *qstats, uint16_t qidx);
240 #endif /* _THUNDERX_NICVF_HW_H */