4 * Copyright (C) Cavium networks Ltd. 2016.
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7 * modification, are permitted provided that the following conditions
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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 #ifndef _THUNDERX_NICVF_HW_H
34 #define _THUNDERX_NICVF_HW_H
38 #include "nicvf_hw_defs.h"
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
41 #define PCI_DEVICE_ID_THUNDERX_PASS1_NICVF 0x0011
42 #define PCI_DEVICE_ID_THUNDERX_PASS2_NICVF 0xA034
43 #define PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF 0xA11E
44 #define PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF 0xA134
46 #define NICVF_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
48 #define NICVF_PASS1 (PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF)
49 #define NICVF_PASS2 (PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF)
51 #define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
60 NICVF_ERR_SET_QS = -8191,/* -8191 */
61 NICVF_ERR_RESET_QS, /* -8190 */
62 NICVF_ERR_REG_POLL, /* -8189 */
63 NICVF_ERR_RBDR_RESET, /* -8188 */
64 NICVF_ERR_RBDR_DISABLE, /* -8187 */
65 NICVF_ERR_RBDR_PREFETCH, /* -8186 */
66 NICVF_ERR_RBDR_RESET1, /* -8185 */
67 NICVF_ERR_RBDR_RESET2, /* -8184 */
68 NICVF_ERR_RQ_CLAIM, /* -8183 */
69 NICVF_ERR_RQ_PF_CFG, /* -8182 */
70 NICVF_ERR_RQ_BP_CFG, /* -8181 */
71 NICVF_ERR_RQ_DROP_CFG, /* -8180 */
72 NICVF_ERR_CQ_DISABLE, /* -8179 */
73 NICVF_ERR_CQ_RESET, /* -8178 */
74 NICVF_ERR_SQ_DISABLE, /* -8177 */
75 NICVF_ERR_SQ_RESET, /* -8176 */
76 NICVF_ERR_SQ_PF_CFG, /* -8175 */
77 NICVF_ERR_LOOPBACK_CFG, /* -8174 */
78 NICVF_ERR_BASE_INIT, /* -8173 */
79 NICVF_ERR_RSS_TBL_UPDATE,/* -8172 */
80 NICVF_ERR_RSS_GET_SZ, /* -8171 */
83 typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *opaque);
85 struct nicvf_rss_reta_info {
88 uint8_t ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
91 /* Common structs used in DPDK and base layer are defined in DPDK layer */
92 #include "../nicvf_struct.h"
94 NICVF_STATIC_ASSERT(sizeof(struct nicvf_rbdr) <= 128);
95 NICVF_STATIC_ASSERT(sizeof(struct nicvf_txq) <= 128);
96 NICVF_STATIC_ASSERT(sizeof(struct nicvf_rxq) <= 128);
99 nicvf_reg_write(struct nicvf *nic, uint32_t offset, uint64_t val)
101 nicvf_addr_write(nic->reg_base + offset, val);
104 static inline uint64_t
105 nicvf_reg_read(struct nicvf *nic, uint32_t offset)
107 return nicvf_addr_read(nic->reg_base + offset);
110 static inline uintptr_t
111 nicvf_qset_base(struct nicvf *nic, uint32_t qidx)
113 return nic->reg_base + (qidx << NIC_Q_NUM_SHIFT);
117 nicvf_queue_reg_write(struct nicvf *nic, uint32_t offset, uint32_t qidx,
120 nicvf_addr_write(nicvf_qset_base(nic, qidx) + offset, val);
123 static inline uint64_t
124 nicvf_queue_reg_read(struct nicvf *nic, uint32_t offset, uint32_t qidx)
126 return nicvf_addr_read(nicvf_qset_base(nic, qidx) + offset);
130 nicvf_disable_all_interrupts(struct nicvf *nic)
132 nicvf_reg_write(nic, NIC_VF_ENA_W1C, NICVF_INTR_ALL_MASK);
133 nicvf_reg_write(nic, NIC_VF_INT, NICVF_INTR_ALL_MASK);
136 static inline uint32_t
137 nicvf_hw_version(struct nicvf *nic)
139 return nic->subsystem_device_id;
142 static inline uint64_t
143 nicvf_hw_cap(struct nicvf *nic)
148 int nicvf_base_init(struct nicvf *nic);
150 int nicvf_reg_get_count(void);
151 int nicvf_reg_poll_interrupts(struct nicvf *nic);
152 int nicvf_reg_dump(struct nicvf *nic, uint64_t *data);
154 int nicvf_qset_config(struct nicvf *nic);
155 int nicvf_qset_reclaim(struct nicvf *nic);
157 int nicvf_qset_rbdr_config(struct nicvf *nic, uint16_t qidx);
158 int nicvf_qset_rbdr_reclaim(struct nicvf *nic, uint16_t qidx);
159 int nicvf_qset_rbdr_precharge(struct nicvf *nic, uint16_t ridx,
160 rbdr_pool_get_handler handler, void *opaque,
162 int nicvf_qset_rbdr_active(struct nicvf *nic, uint16_t qidx);
164 int nicvf_qset_rq_config(struct nicvf *nic, uint16_t qidx,
165 struct nicvf_rxq *rxq);
166 int nicvf_qset_rq_reclaim(struct nicvf *nic, uint16_t qidx);
168 int nicvf_qset_cq_config(struct nicvf *nic, uint16_t qidx,
169 struct nicvf_rxq *rxq);
170 int nicvf_qset_cq_reclaim(struct nicvf *nic, uint16_t qidx);
172 int nicvf_qset_sq_config(struct nicvf *nic, uint16_t qidx,
173 struct nicvf_txq *txq);
174 int nicvf_qset_sq_reclaim(struct nicvf *nic, uint16_t qidx);
176 uint32_t nicvf_qsize_rbdr_roundup(uint32_t val);
177 uint32_t nicvf_qsize_cq_roundup(uint32_t val);
178 uint32_t nicvf_qsize_sq_roundup(uint32_t val);
180 void nicvf_vlan_hw_strip(struct nicvf *nic, bool enable);
182 int nicvf_rss_config(struct nicvf *nic, uint32_t qcnt, uint64_t cfg);
183 int nicvf_rss_term(struct nicvf *nic);
185 int nicvf_rss_reta_update(struct nicvf *nic, uint8_t *tbl, uint32_t max_count);
186 int nicvf_rss_reta_query(struct nicvf *nic, uint8_t *tbl, uint32_t max_count);
188 void nicvf_rss_set_key(struct nicvf *nic, uint8_t *key);
189 void nicvf_rss_get_key(struct nicvf *nic, uint8_t *key);
191 void nicvf_rss_set_cfg(struct nicvf *nic, uint64_t val);
192 uint64_t nicvf_rss_get_cfg(struct nicvf *nic);
194 int nicvf_loopback_config(struct nicvf *nic, bool enable);
196 #endif /* _THUNDERX_NICVF_HW_H */