4 * Copyright (C) Cavium networks Ltd. 2016.
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33 #ifndef _THUNDERX_NICVF_HW_DEFS_H
34 #define _THUNDERX_NICVF_HW_DEFS_H
39 /* Virtual function register offsets */
41 #define NIC_VF_CFG (0x000020)
42 #define NIC_VF_PF_MAILBOX_0_1 (0x000130)
43 #define NIC_VF_INT (0x000200)
44 #define NIC_VF_INT_W1S (0x000220)
45 #define NIC_VF_ENA_W1C (0x000240)
46 #define NIC_VF_ENA_W1S (0x000260)
48 #define NIC_VNIC_RSS_CFG (0x0020E0)
49 #define NIC_VNIC_RSS_KEY_0_4 (0x002200)
50 #define NIC_VNIC_TX_STAT_0_4 (0x004000)
51 #define NIC_VNIC_RX_STAT_0_13 (0x004100)
52 #define NIC_VNIC_RQ_GEN_CFG (0x010010)
54 #define NIC_QSET_CQ_0_7_CFG (0x010400)
55 #define NIC_QSET_CQ_0_7_CFG2 (0x010408)
56 #define NIC_QSET_CQ_0_7_THRESH (0x010410)
57 #define NIC_QSET_CQ_0_7_BASE (0x010420)
58 #define NIC_QSET_CQ_0_7_HEAD (0x010428)
59 #define NIC_QSET_CQ_0_7_TAIL (0x010430)
60 #define NIC_QSET_CQ_0_7_DOOR (0x010438)
61 #define NIC_QSET_CQ_0_7_STATUS (0x010440)
62 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448)
63 #define NIC_QSET_CQ_0_7_DEBUG (0x010450)
65 #define NIC_QSET_RQ_0_7_CFG (0x010600)
66 #define NIC_QSET_RQ_0_7_STATUS0 (0x010700)
67 #define NIC_QSET_RQ_0_7_STATUS1 (0x010708)
69 #define NIC_QSET_SQ_0_7_CFG (0x010800)
70 #define NIC_QSET_SQ_0_7_THRESH (0x010810)
71 #define NIC_QSET_SQ_0_7_BASE (0x010820)
72 #define NIC_QSET_SQ_0_7_HEAD (0x010828)
73 #define NIC_QSET_SQ_0_7_TAIL (0x010830)
74 #define NIC_QSET_SQ_0_7_DOOR (0x010838)
75 #define NIC_QSET_SQ_0_7_STATUS (0x010840)
76 #define NIC_QSET_SQ_0_7_DEBUG (0x010848)
77 #define NIC_QSET_SQ_0_7_STATUS0 (0x010900)
78 #define NIC_QSET_SQ_0_7_STATUS1 (0x010908)
80 #define NIC_QSET_RBDR_0_1_CFG (0x010C00)
81 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10)
82 #define NIC_QSET_RBDR_0_1_BASE (0x010C20)
83 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28)
84 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30)
85 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38)
86 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40)
87 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48)
88 #define NIC_QSET_RBDR_0_1_PRFCH_STATUS (0x010C50)
90 /* vNIC HW Constants */
92 #define NIC_Q_NUM_SHIFT 18
94 #define MAX_QUEUE_SET 128
95 #define MAX_RCV_QUEUES_PER_QS 8
96 #define MAX_RCV_BUF_DESC_RINGS_PER_QS 2
97 #define MAX_SND_QUEUES_PER_QS 8
98 #define MAX_CMP_QUEUES_PER_QS 8
100 #define NICVF_INTR_CQ_SHIFT 0
101 #define NICVF_INTR_SQ_SHIFT 8
102 #define NICVF_INTR_RBDR_SHIFT 16
103 #define NICVF_INTR_PKT_DROP_SHIFT 20
104 #define NICVF_INTR_TCP_TIMER_SHIFT 21
105 #define NICVF_INTR_MBOX_SHIFT 22
106 #define NICVF_INTR_QS_ERR_SHIFT 23
108 #define NICVF_QS_RQ_DIS_APAD_SHIFT 22
110 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
111 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
112 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
113 #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT)
114 #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT)
115 #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT)
116 #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT)
117 #define NICVF_INTR_ALL_MASK (0x7FFFFF)
119 #define NICVF_CQ_WR_FULL (1ULL << 26)
120 #define NICVF_CQ_WR_DISABLE (1ULL << 25)
121 #define NICVF_CQ_WR_FAULT (1ULL << 24)
122 #define NICVF_CQ_ERR_MASK (NICVF_CQ_WR_FULL |\
123 NICVF_CQ_WR_DISABLE |\
125 #define NICVF_CQ_CQE_COUNT_MASK (0xFFFF)
127 #define NICVF_SQ_ERR_STOPPED (1ULL << 21)
128 #define NICVF_SQ_ERR_SEND (1ULL << 20)
129 #define NICVF_SQ_ERR_DPE (1ULL << 19)
130 #define NICVF_SQ_ERR_MASK (NICVF_SQ_ERR_STOPPED |\
133 #define NICVF_SQ_STATUS_STOPPED_BIT (21)
135 #define NICVF_RBDR_FIFO_STATE_SHIFT (62)
136 #define NICVF_RBDR_FIFO_STATE_MASK (3ULL << NICVF_RBDR_FIFO_STATE_SHIFT)
137 #define NICVF_RBDR_COUNT_MASK (0x7FFFF)
140 #define NICVF_CQ_RESET (1ULL << 41)
141 #define NICVF_SQ_RESET (1ULL << 17)
142 #define NICVF_RBDR_RESET (1ULL << 43)
145 #define NIC_MAX_RSS_HASH_BITS (8)
146 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
147 #define RSS_HASH_KEY_SIZE (5) /* 320 bit key */
148 #define RSS_HASH_KEY_BYTE_SIZE (40) /* 320 bit key */
150 #define RSS_L2_EXTENDED_HASH_ENA (1 << 0)
151 #define RSS_IP_ENA (1 << 1)
152 #define RSS_TCP_ENA (1 << 2)
153 #define RSS_TCP_SYN_ENA (1 << 3)
154 #define RSS_UDP_ENA (1 << 4)
155 #define RSS_L4_EXTENDED_ENA (1 << 5)
156 #define RSS_L3_BI_DIRECTION_ENA (1 << 7)
157 #define RSS_L4_BI_DIRECTION_ENA (1 << 8)
158 #define RSS_TUN_VXLAN_ENA (1 << 9)
159 #define RSS_TUN_GENEVE_ENA (1 << 10)
160 #define RSS_TUN_NVGRE_ENA (1 << 11)
162 #define RBDR_QUEUE_SZ_8K (8 * 1024)
163 #define RBDR_QUEUE_SZ_16K (16 * 1024)
164 #define RBDR_QUEUE_SZ_32K (32 * 1024)
165 #define RBDR_QUEUE_SZ_64K (64 * 1024)
166 #define RBDR_QUEUE_SZ_128K (128 * 1024)
167 #define RBDR_QUEUE_SZ_256K (256 * 1024)
168 #define RBDR_QUEUE_SZ_512K (512 * 1024)
169 #define RBDR_QUEUE_SZ_MAX RBDR_QUEUE_SZ_512K
171 #define RBDR_SIZE_SHIFT (13) /* 8k */
173 #define SND_QUEUE_SZ_1K (1 * 1024)
174 #define SND_QUEUE_SZ_2K (2 * 1024)
175 #define SND_QUEUE_SZ_4K (4 * 1024)
176 #define SND_QUEUE_SZ_8K (8 * 1024)
177 #define SND_QUEUE_SZ_16K (16 * 1024)
178 #define SND_QUEUE_SZ_32K (32 * 1024)
179 #define SND_QUEUE_SZ_64K (64 * 1024)
180 #define SND_QUEUE_SZ_MAX SND_QUEUE_SZ_64K
182 #define SND_QSIZE_SHIFT (10) /* 1k */
184 #define CMP_QUEUE_SZ_1K (1 * 1024)
185 #define CMP_QUEUE_SZ_2K (2 * 1024)
186 #define CMP_QUEUE_SZ_4K (4 * 1024)
187 #define CMP_QUEUE_SZ_8K (8 * 1024)
188 #define CMP_QUEUE_SZ_16K (16 * 1024)
189 #define CMP_QUEUE_SZ_32K (32 * 1024)
190 #define CMP_QUEUE_SZ_64K (64 * 1024)
191 #define CMP_QUEUE_SZ_MAX CMP_QUEUE_SZ_64K
193 #define CMP_QSIZE_SHIFT (10) /* 1k */
195 #define NICVF_QSIZE_MIN_VAL (0)
196 #define NICVF_QSIZE_MAX_VAL (6)
198 /* Min/Max packet size */
199 #define NIC_HW_MIN_FRS (64)
200 #define NIC_HW_MAX_FRS (9200) /* 9216 max pkt including FCS */
201 #define NIC_HW_MAX_SEGS (12)
203 /* Descriptor alignments */
204 #define NICVF_RBDR_BASE_ALIGN_BYTES (128) /* 7 bits */
205 #define NICVF_CQ_BASE_ALIGN_BYTES (512) /* 9 bits */
206 #define NICVF_SQ_BASE_ALIGN_BYTES (128) /* 7 bits */
208 #define NICVF_CQE_RBPTR_WORD (6)
209 #define NICVF_CQE_RX2_RBPTR_WORD (7)
211 #define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s)
212 #define assert_primary(nic) assert((nic)->sqs_mode == 0)
214 typedef uint64_t nicvf_phys_addr_t;
216 #ifndef __BYTE_ORDER__
217 #error __BYTE_ORDER__ not defined
220 /* vNIC HW Enumerations */
222 enum nic_send_ld_type_e {
223 NIC_SEND_LD_TYPE_E_LDD,
224 NIC_SEND_LD_TYPE_E_LDT,
225 NIC_SEND_LD_TYPE_E_LDWB,
226 NIC_SEND_LD_TYPE_E_ENUM_LAST,
229 enum ether_type_algorithm {
234 ETYPE_ALG_VLAN_STRIP,
241 L3TYPE_IPV4_OPTIONS = 0x5,
243 L3TYPE_IPV6_OPTIONS = 0x7,
244 L3TYPE_ET_STOP = 0xD,
248 #define NICVF_L3TYPE_OPTIONS_MASK ((uint8_t)1)
249 #define NICVF_L3TYPE_IPVX_MASK ((uint8_t)0x06)
264 /* CPI and RSSI configuration */
265 enum cpi_algorithm_type {
272 enum rss_algorithm_type {
287 RSS_HASH_TCP_SYN_DIS,
295 /* Completion queue entry types */
299 CQE_TYPE_RX_SPLIT = 0x3,
300 CQE_TYPE_RX_TCP = 0x4,
302 CQE_TYPE_SEND_PTP = 0x9,
305 enum cqe_rx_tcp_status {
306 CQE_RX_STATUS_VALID_TCP_CNXT,
307 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
310 enum cqe_send_status {
311 CQE_SEND_STATUS_GOOD,
312 CQE_SEND_STATUS_DESC_FAULT = 0x01,
313 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
314 CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
315 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
316 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
317 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
318 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
319 CQE_SEND_STATUS_LOCK_VIOL = 0x84,
320 CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
321 CQE_SEND_STATUS_DATA_FAULT = 0x86,
322 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
323 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
324 CQE_SEND_STATUS_MEM_FAULT = 0x89,
325 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
326 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
329 enum cqe_rx_tcp_end_reason {
330 CQE_RX_TCP_END_FIN_FLAG_DET,
331 CQE_RX_TCP_END_INVALID_FLAG,
332 CQE_RX_TCP_END_TIMEOUT,
333 CQE_RX_TCP_END_OUT_OF_SEQ,
334 CQE_RX_TCP_END_PKT_ERR,
335 CQE_RX_TCP_END_QS_DISABLED = 0x0F,
338 /* Packet protocol level error enumeration */
339 enum cqe_rx_err_level {
346 /* Packet protocol level error type enumeration */
347 enum cqe_rx_err_opcode {
349 CQE_RX_ERR_RE_PARTIAL,
350 CQE_RX_ERR_RE_JABBER,
351 CQE_RX_ERR_RE_FCS = 0x7,
352 CQE_RX_ERR_RE_TERMINATE = 0x9,
353 CQE_RX_ERR_RE_RX_CTL = 0xb,
354 CQE_RX_ERR_PREL2_ERR = 0x1f,
355 CQE_RX_ERR_L2_FRAGMENT = 0x20,
356 CQE_RX_ERR_L2_OVERRUN = 0x21,
357 CQE_RX_ERR_L2_PFCS = 0x22,
358 CQE_RX_ERR_L2_PUNY = 0x23,
359 CQE_RX_ERR_L2_MAL = 0x24,
360 CQE_RX_ERR_L2_OVERSIZE = 0x25,
361 CQE_RX_ERR_L2_UNDERSIZE = 0x26,
362 CQE_RX_ERR_L2_LENMISM = 0x27,
363 CQE_RX_ERR_L2_PCLP = 0x28,
364 CQE_RX_ERR_IP_NOT = 0x41,
365 CQE_RX_ERR_IP_CHK = 0x42,
366 CQE_RX_ERR_IP_MAL = 0x43,
367 CQE_RX_ERR_IP_MALD = 0x44,
368 CQE_RX_ERR_IP_HOP = 0x45,
369 CQE_RX_ERR_L3_ICRC = 0x46,
370 CQE_RX_ERR_L3_PCLP = 0x47,
371 CQE_RX_ERR_L4_MAL = 0x61,
372 CQE_RX_ERR_L4_CHK = 0x62,
373 CQE_RX_ERR_UDP_LEN = 0x63,
374 CQE_RX_ERR_L4_PORT = 0x64,
375 CQE_RX_ERR_TCP_FLAG = 0x65,
376 CQE_RX_ERR_TCP_OFFSET = 0x66,
377 CQE_RX_ERR_L4_PCLP = 0x67,
378 CQE_RX_ERR_RBDR_TRUNC = 0x70,
381 enum send_l4_csum_type {
382 SEND_L4_CSUM_DISABLE,
393 enum send_load_type {
399 enum send_mem_alg_type {
401 SEND_MEMALG_ADD = 0x08,
402 SEND_MEMALG_SUB = 0x09,
403 SEND_MEMALG_ADDLEN = 0x0A,
404 SEND_MEMALG_SUBLEN = 0x0B,
407 enum send_mem_dsz_type {
410 SEND_MEMDSZ_B8 = 0x03,
413 enum sq_subdesc_type {
414 SQ_DESC_TYPE_INVALID,
417 SQ_DESC_TYPE_IMMEDIATE,
441 L4_UDP_GENEVE = 0x09,
455 RBDR_FIFO_STATE_INACTIVE,
456 RBDR_FIFO_STATE_ACTIVE,
457 RBDR_FIFO_STATE_RESET,
458 RBDR_FIFO_STATE_FAIL,
461 enum rq_cache_allocation {
464 RQ_CACHE_ALLOC_FIRST,
468 enum cq_rx_errlvl_e {
477 CQ_RX_ERROP_RE_PARTIAL = 0x1,
478 CQ_RX_ERROP_RE_JABBER = 0x2,
479 CQ_RX_ERROP_RE_FCS = 0x7,
480 CQ_RX_ERROP_RE_TERMINATE = 0x9,
481 CQ_RX_ERROP_RE_RX_CTL = 0xb,
482 CQ_RX_ERROP_PREL2_ERR = 0x1f,
483 CQ_RX_ERROP_L2_FRAGMENT = 0x20,
484 CQ_RX_ERROP_L2_OVERRUN = 0x21,
485 CQ_RX_ERROP_L2_PFCS = 0x22,
486 CQ_RX_ERROP_L2_PUNY = 0x23,
487 CQ_RX_ERROP_L2_MAL = 0x24,
488 CQ_RX_ERROP_L2_OVERSIZE = 0x25,
489 CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
490 CQ_RX_ERROP_L2_LENMISM = 0x27,
491 CQ_RX_ERROP_L2_PCLP = 0x28,
492 CQ_RX_ERROP_IP_NOT = 0x41,
493 CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
494 CQ_RX_ERROP_IP_MAL = 0x43,
495 CQ_RX_ERROP_IP_MALD = 0x44,
496 CQ_RX_ERROP_IP_HOP = 0x45,
497 CQ_RX_ERROP_L3_ICRC = 0x46,
498 CQ_RX_ERROP_L3_PCLP = 0x47,
499 CQ_RX_ERROP_L4_MAL = 0x61,
500 CQ_RX_ERROP_L4_CHK = 0x62,
501 CQ_RX_ERROP_UDP_LEN = 0x63,
502 CQ_RX_ERROP_L4_PORT = 0x64,
503 CQ_RX_ERROP_TCP_FLAG = 0x65,
504 CQ_RX_ERROP_TCP_OFFSET = 0x66,
505 CQ_RX_ERROP_L4_PCLP = 0x67,
506 CQ_RX_ERROP_RBDR_TRUNC = 0x70,
511 CQ_TX_ERROP_DESC_FAULT = 0x10,
512 CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
513 CQ_TX_ERROP_SUBDC_ERR = 0x12,
514 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
515 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
516 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
517 CQ_TX_ERROP_LOCK_VIOL = 0x83,
518 CQ_TX_ERROP_DATA_FAULT = 0x84,
519 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
520 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
521 CQ_TX_ERROP_MEM_FAULT = 0x87,
522 CQ_TX_ERROP_CK_OVERLAP = 0x88,
523 CQ_TX_ERROP_CK_OFLOW = 0x89,
524 CQ_TX_ERROP_ENUM_LAST = 0x8a,
527 enum rq_sq_stats_reg_offset {
532 enum nic_stat_vnic_rx_e {
549 enum nic_stat_vnic_tx_e {
557 /* vNIC HW Register structures */
562 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
564 uint64_t stdn_fault:1;
572 uint64_t vlan_found:1;
573 uint64_t vlan_stripped:1;
574 uint64_t vlan2_found:1;
575 uint64_t vlan2_stripped:1;
578 uint64_t l2_present:1;
579 uint64_t err_level:3;
580 uint64_t err_opcode:8;
582 uint64_t err_opcode:8;
583 uint64_t err_level:3;
584 uint64_t l2_present:1;
587 uint64_t vlan2_stripped:1;
588 uint64_t vlan2_found:1;
589 uint64_t vlan_stripped:1;
590 uint64_t vlan_found:1;
598 uint64_t stdn_fault:1;
607 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
612 uint64_t cq_pkt_len:8;
613 uint64_t align_pad:3;
619 uint64_t align_pad:3;
620 uint64_t cq_pkt_len:8;
632 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
634 uint64_t vlan_tci:16;
636 uint64_t vlan2_ptr:8;
638 uint64_t vlan2_ptr:8;
640 uint64_t vlan_tci:16;
649 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
666 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
683 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
700 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
701 uint64_t vlan_found:1;
702 uint64_t vlan_stripped:1;
703 uint64_t vlan2_found:1;
704 uint64_t vlan2_stripped:1;
707 uint64_t inner_l4type:4;
708 uint64_t inner_l3type:4;
710 uint64_t vlan2_ptr:8;
713 uint64_t inner_l3ptr:8;
714 uint64_t inner_l4ptr:8;
716 uint64_t inner_l4ptr:8;
717 uint64_t inner_l3ptr:8;
720 uint64_t vlan2_ptr:8;
722 uint64_t inner_l3type:4;
723 uint64_t inner_l4type:4;
726 uint64_t vlan2_stripped:1;
727 uint64_t vlan2_found:1;
728 uint64_t vlan_stripped:1;
729 uint64_t vlan_found:1;
735 cqe_rx_word0_t word0;
736 cqe_rx_word1_t word1;
737 cqe_rx_word2_t word2;
738 cqe_rx_word3_t word3;
739 cqe_rx_word4_t word4;
740 cqe_rx_word5_t word5;
741 cqe_rx2_word6_t word6; /* if NIC_PF_RX_CFG[CQE_RX2_ENA] set */
744 struct cqe_rx_tcp_err_t {
745 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
746 uint64_t cqe_type:4; /* W0 */
749 uint64_t rsvd1:4; /* W1 */
750 uint64_t partial_first:1;
752 uint64_t rbdr_bytes:8;
759 uint64_t rbdr_bytes:8;
761 uint64_t partial_first:1;
766 struct cqe_rx_tcp_t {
767 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
768 uint64_t cqe_type:4; /* W0 */
770 uint64_t cq_tcp_status:8;
772 uint64_t rsvd1:32; /* W1 */
773 uint64_t tcp_cntx_bytes:8;
775 uint64_t tcp_err_bytes:16;
777 uint64_t cq_tcp_status:8;
779 uint64_t cqe_type:4; /* W0 */
781 uint64_t tcp_err_bytes:16;
783 uint64_t tcp_cntx_bytes:8;
784 uint64_t rsvd1:32; /* W1 */
789 #if defined(__BIG_ENDIAN_BITFIELD)
790 uint64_t cqe_type:4; /* W0 */
798 uint64_t send_status:8;
800 uint64_t ptp_timestamp:64; /* W1 */
801 #elif defined(__LITTLE_ENDIAN_BITFIELD)
802 uint64_t send_status:8;
810 uint64_t cqe_type:4; /* W0 */
812 uint64_t ptp_timestamp:64;
816 struct cq_entry_type_t {
817 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
828 struct cq_entry_type_t type;
829 struct cqe_rx_t rx_hdr;
830 struct cqe_rx_tcp_t rx_tcp_hdr;
831 struct cqe_rx_tcp_err_t rx_tcp_err_hdr;
832 struct cqe_send_t cqe_send;
835 NICVF_STATIC_ASSERT(sizeof(union cq_entry_t) == 512);
837 struct rbdr_entry_t {
838 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
842 uint64_t buf_addr:42;
843 uint64_t cache_align:7;
845 nicvf_phys_addr_t full_addr;
850 uint64_t cache_align:7;
851 uint64_t buf_addr:42;
854 nicvf_phys_addr_t full_addr;
859 NICVF_STATIC_ASSERT(sizeof(struct rbdr_entry_t) == sizeof(uint64_t));
861 /* TCP reassembly context */
862 struct rbe_tcp_cnxt_t {
863 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
864 uint64_t tcp_pkt_cnt:12;
866 uint64_t align_hdr_bytes:4;
867 uint64_t align_ptr_bytes:4;
868 uint64_t ptr_bytes:16;
872 uint64_t tcp_end_reason:2;
873 uint64_t tcp_status:4;
875 uint64_t tcp_status:4;
876 uint64_t tcp_end_reason:2;
880 uint64_t ptr_bytes:16;
881 uint64_t align_ptr_bytes:4;
882 uint64_t align_hdr_bytes:4;
884 uint64_t tcp_pkt_cnt:12;
888 /* Always Big endian */
892 uint64_t skip_length:6;
893 uint64_t disable_rss:1;
894 uint64_t disable_tcp_reassembly:1;
901 struct sq_crc_subdesc {
902 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
904 uint64_t crc_ival:32;
905 uint64_t subdesc_type:4;
908 uint64_t crc_insert_pos:16;
909 uint64_t hdr_start:16;
913 uint64_t hdr_start:16;
914 uint64_t crc_insert_pos:16;
917 uint64_t subdesc_type:4;
918 uint64_t crc_ival:32;
923 struct sq_gather_subdesc {
924 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
925 uint64_t subdesc_type:4; /* W0 */
930 uint64_t rsvd1:15; /* W1 */
936 uint64_t subdesc_type:4; /* W0 */
939 uint64_t rsvd1:15; /* W1 */
943 /* SQ immediate subdescriptor */
944 struct sq_imm_subdesc {
945 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
946 uint64_t subdesc_type:4; /* W0 */
950 uint64_t data:64; /* W1 */
954 uint64_t subdesc_type:4; /* W0 */
956 uint64_t data:64; /* W1 */
960 struct sq_mem_subdesc {
961 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
962 uint64_t subdesc_type:4; /* W0 */
969 uint64_t rsvd1:15; /* W1 */
977 uint64_t subdesc_type:4; /* W0 */
980 uint64_t rsvd1:15; /* W1 */
984 struct sq_hdr_subdesc {
985 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
986 uint64_t subdesc_type:4;
988 uint64_t post_cqe:1; /* Post CQE on no error also */
989 uint64_t dont_send:1;
991 uint64_t subdesc_cnt:8;
994 uint64_t csum_inner_l4:2;
995 uint64_t csum_inner_l3:1;
997 uint64_t l4_offset:8;
998 uint64_t l3_offset:8;
1000 uint64_t tot_len:20; /* W0 */
1003 uint64_t inner_l4_offset:8;
1004 uint64_t inner_l3_offset:8;
1005 uint64_t tso_start:8;
1007 uint64_t tso_max_paysize:14; /* W1 */
1009 uint64_t tot_len:20;
1011 uint64_t l3_offset:8;
1012 uint64_t l4_offset:8;
1014 uint64_t csum_inner_l3:1;
1015 uint64_t csum_inner_l4:2;
1018 uint64_t subdesc_cnt:8;
1020 uint64_t dont_send:1;
1021 uint64_t post_cqe:1; /* Post CQE on no error also */
1023 uint64_t subdesc_type:4; /* W0 */
1025 uint64_t tso_max_paysize:14;
1027 uint64_t tso_start:8;
1028 uint64_t inner_l3_offset:8;
1029 uint64_t inner_l4_offset:8;
1030 uint64_t rsvd2:24; /* W1 */
1034 /* Each sq entry is 128 bits wide */
1037 struct sq_hdr_subdesc hdr;
1038 struct sq_imm_subdesc imm;
1039 struct sq_gather_subdesc gather;
1040 struct sq_crc_subdesc crc;
1041 struct sq_mem_subdesc mem;
1044 NICVF_STATIC_ASSERT(sizeof(union sq_entry_t) == 16);
1046 /* Queue config register formats */
1047 struct rq_cfg { union { struct {
1048 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1049 uint64_t reserved_2_63:62;
1051 uint64_t reserved_0:1;
1053 uint64_t reserved_0:1;
1055 uint64_t reserved_2_63:62;
1061 struct cq_cfg { union { struct {
1062 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1063 uint64_t reserved_43_63:21;
1067 uint64_t reserved_35_39:5;
1069 uint64_t reserved_25_31:7;
1071 uint64_t reserved_0_15:16;
1073 uint64_t reserved_0_15:16;
1075 uint64_t reserved_25_31:7;
1077 uint64_t reserved_35_39:5;
1081 uint64_t reserved_43_63:21;
1087 struct sq_cfg { union { struct {
1088 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1089 uint64_t reserved_20_63:44;
1091 uint64_t reserved_18_18:1;
1094 uint64_t reserved_11_15:5;
1096 uint64_t reserved_3_7:5;
1097 uint64_t tstmp_bgx_intf:3;
1099 uint64_t tstmp_bgx_intf:3;
1100 uint64_t reserved_3_7:5;
1102 uint64_t reserved_11_15:5;
1105 uint64_t reserved_18_18:1;
1107 uint64_t reserved_20_63:44;
1113 struct rbdr_cfg { union { struct {
1114 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1115 uint64_t reserved_45_63:19;
1119 uint64_t reserved_36_41:6;
1121 uint64_t reserved_25_31:7;
1123 uint64_t reserved_12_15:4;
1127 uint64_t reserved_12_15:4;
1129 uint64_t reserved_25_31:7;
1131 uint64_t reserved_36_41:6;
1135 uint64_t reserved_45_63:19;
1141 struct pf_qs_cfg { union { struct {
1142 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1143 uint64_t reserved_32_63:32;
1145 uint64_t reserved_27_30:4;
1146 uint64_t sq_ins_ena:1;
1147 uint64_t sq_ins_pos:6;
1148 uint64_t lock_ena:1;
1149 uint64_t lock_viol_cqe_ena:1;
1150 uint64_t send_tstmp_ena:1;
1152 uint64_t reserved_7_15:9;
1156 uint64_t reserved_7_15:9;
1158 uint64_t send_tstmp_ena:1;
1159 uint64_t lock_viol_cqe_ena:1;
1160 uint64_t lock_ena:1;
1161 uint64_t sq_ins_pos:6;
1162 uint64_t sq_ins_ena:1;
1163 uint64_t reserved_27_30:4;
1165 uint64_t reserved_32_63:32;
1171 struct pf_rq_cfg { union { struct {
1172 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1173 uint64_t reserved1:1;
1174 uint64_t reserved0:34;
1175 uint64_t strip_pre_l2:1;
1179 uint64_t rbdr_cont_qs:7;
1180 uint64_t rbdr_cont_idx:1;
1181 uint64_t rbdr_strt_qs:7;
1182 uint64_t rbdr_strt_idx:1;
1184 uint64_t rbdr_strt_idx:1;
1185 uint64_t rbdr_strt_qs:7;
1186 uint64_t rbdr_cont_idx:1;
1187 uint64_t rbdr_cont_qs:7;
1191 uint64_t strip_pre_l2:1;
1192 uint64_t reserved0:34;
1193 uint64_t reserved1:1;
1199 struct pf_rq_drop_cfg { union { struct {
1200 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1201 uint64_t rbdr_red:1;
1203 uint64_t reserved3:14;
1204 uint64_t rbdr_pass:8;
1205 uint64_t rbdr_drop:8;
1206 uint64_t reserved2:8;
1209 uint64_t reserved1:8;
1211 uint64_t reserved1:8;
1214 uint64_t reserved2:8;
1215 uint64_t rbdr_drop:8;
1216 uint64_t rbdr_pass:8;
1217 uint64_t reserved3:14;
1219 uint64_t rbdr_red:1;
1225 #endif /* _THUNDERX_NICVF_HW_DEFS_H */