4 * Copyright (C) Cavium networks Ltd. 2016.
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33 #ifndef _THUNDERX_NICVF_HW_DEFS_H
34 #define _THUNDERX_NICVF_HW_DEFS_H
39 /* Virtual function register offsets */
41 #define NIC_VF_CFG (0x000020)
42 #define NIC_VF_PF_MAILBOX_0_1 (0x000130)
43 #define NIC_VF_INT (0x000200)
44 #define NIC_VF_INT_W1S (0x000220)
45 #define NIC_VF_ENA_W1C (0x000240)
46 #define NIC_VF_ENA_W1S (0x000260)
48 #define NIC_VNIC_RSS_CFG (0x0020E0)
49 #define NIC_VNIC_RSS_KEY_0_4 (0x002200)
50 #define NIC_VNIC_TX_STAT_0_4 (0x004000)
51 #define NIC_VNIC_RX_STAT_0_13 (0x004100)
52 #define NIC_VNIC_RQ_GEN_CFG (0x010010)
54 #define NIC_QSET_CQ_0_7_CFG (0x010400)
55 #define NIC_QSET_CQ_0_7_CFG2 (0x010408)
56 #define NIC_QSET_CQ_0_7_THRESH (0x010410)
57 #define NIC_QSET_CQ_0_7_BASE (0x010420)
58 #define NIC_QSET_CQ_0_7_HEAD (0x010428)
59 #define NIC_QSET_CQ_0_7_TAIL (0x010430)
60 #define NIC_QSET_CQ_0_7_DOOR (0x010438)
61 #define NIC_QSET_CQ_0_7_STATUS (0x010440)
62 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448)
63 #define NIC_QSET_CQ_0_7_DEBUG (0x010450)
65 #define NIC_QSET_RQ_0_7_CFG (0x010600)
66 #define NIC_QSET_RQ_0_7_STATUS0 (0x010700)
67 #define NIC_QSET_RQ_0_7_STATUS1 (0x010708)
69 #define NIC_QSET_SQ_0_7_CFG (0x010800)
70 #define NIC_QSET_SQ_0_7_THRESH (0x010810)
71 #define NIC_QSET_SQ_0_7_BASE (0x010820)
72 #define NIC_QSET_SQ_0_7_HEAD (0x010828)
73 #define NIC_QSET_SQ_0_7_TAIL (0x010830)
74 #define NIC_QSET_SQ_0_7_DOOR (0x010838)
75 #define NIC_QSET_SQ_0_7_STATUS (0x010840)
76 #define NIC_QSET_SQ_0_7_DEBUG (0x010848)
77 #define NIC_QSET_SQ_0_7_STATUS0 (0x010900)
78 #define NIC_QSET_SQ_0_7_STATUS1 (0x010908)
80 #define NIC_QSET_RBDR_0_1_CFG (0x010C00)
81 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10)
82 #define NIC_QSET_RBDR_0_1_BASE (0x010C20)
83 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28)
84 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30)
85 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38)
86 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40)
87 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48)
88 #define NIC_QSET_RBDR_0_1_PRFCH_STATUS (0x010C50)
90 /* vNIC HW Constants */
92 #define NIC_Q_NUM_SHIFT 18
94 #define MAX_QUEUE_SET 128
95 #define MAX_RCV_QUEUES_PER_QS 8
96 #define MAX_RCV_BUF_DESC_RINGS_PER_QS 2
97 #define MAX_SND_QUEUES_PER_QS 8
98 #define MAX_CMP_QUEUES_PER_QS 8
100 #define NICVF_INTR_CQ_SHIFT 0
101 #define NICVF_INTR_SQ_SHIFT 8
102 #define NICVF_INTR_RBDR_SHIFT 16
103 #define NICVF_INTR_PKT_DROP_SHIFT 20
104 #define NICVF_INTR_TCP_TIMER_SHIFT 21
105 #define NICVF_INTR_MBOX_SHIFT 22
106 #define NICVF_INTR_QS_ERR_SHIFT 23
108 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
109 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
110 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
111 #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT)
112 #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT)
113 #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT)
114 #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT)
115 #define NICVF_INTR_ALL_MASK (0x7FFFFF)
117 #define NICVF_CQ_WR_FULL (1ULL << 26)
118 #define NICVF_CQ_WR_DISABLE (1ULL << 25)
119 #define NICVF_CQ_WR_FAULT (1ULL << 24)
120 #define NICVF_CQ_ERR_MASK (NICVF_CQ_WR_FULL |\
121 NICVF_CQ_WR_DISABLE |\
123 #define NICVF_CQ_CQE_COUNT_MASK (0xFFFF)
125 #define NICVF_SQ_ERR_STOPPED (1ULL << 21)
126 #define NICVF_SQ_ERR_SEND (1ULL << 20)
127 #define NICVF_SQ_ERR_DPE (1ULL << 19)
128 #define NICVF_SQ_ERR_MASK (NICVF_SQ_ERR_STOPPED |\
131 #define NICVF_SQ_STATUS_STOPPED_BIT (21)
133 #define NICVF_RBDR_FIFO_STATE_SHIFT (62)
134 #define NICVF_RBDR_FIFO_STATE_MASK (3ULL << NICVF_RBDR_FIFO_STATE_SHIFT)
135 #define NICVF_RBDR_COUNT_MASK (0x7FFFF)
138 #define NICVF_CQ_RESET (1ULL << 41)
139 #define NICVF_SQ_RESET (1ULL << 17)
140 #define NICVF_RBDR_RESET (1ULL << 43)
143 #define NIC_MAX_RSS_HASH_BITS (8)
144 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
145 #define RSS_HASH_KEY_SIZE (5) /* 320 bit key */
146 #define RSS_HASH_KEY_BYTE_SIZE (40) /* 320 bit key */
148 #define RSS_L2_EXTENDED_HASH_ENA (1 << 0)
149 #define RSS_IP_ENA (1 << 1)
150 #define RSS_TCP_ENA (1 << 2)
151 #define RSS_TCP_SYN_ENA (1 << 3)
152 #define RSS_UDP_ENA (1 << 4)
153 #define RSS_L4_EXTENDED_ENA (1 << 5)
154 #define RSS_L3_BI_DIRECTION_ENA (1 << 7)
155 #define RSS_L4_BI_DIRECTION_ENA (1 << 8)
156 #define RSS_TUN_VXLAN_ENA (1 << 9)
157 #define RSS_TUN_GENEVE_ENA (1 << 10)
158 #define RSS_TUN_NVGRE_ENA (1 << 11)
160 #define RBDR_QUEUE_SZ_8K (8 * 1024)
161 #define RBDR_QUEUE_SZ_16K (16 * 1024)
162 #define RBDR_QUEUE_SZ_32K (32 * 1024)
163 #define RBDR_QUEUE_SZ_64K (64 * 1024)
164 #define RBDR_QUEUE_SZ_128K (128 * 1024)
165 #define RBDR_QUEUE_SZ_256K (256 * 1024)
166 #define RBDR_QUEUE_SZ_512K (512 * 1024)
168 #define RBDR_SIZE_SHIFT (13) /* 8k */
170 #define SND_QUEUE_SZ_1K (1 * 1024)
171 #define SND_QUEUE_SZ_2K (2 * 1024)
172 #define SND_QUEUE_SZ_4K (4 * 1024)
173 #define SND_QUEUE_SZ_8K (8 * 1024)
174 #define SND_QUEUE_SZ_16K (16 * 1024)
175 #define SND_QUEUE_SZ_32K (32 * 1024)
176 #define SND_QUEUE_SZ_64K (64 * 1024)
178 #define SND_QSIZE_SHIFT (10) /* 1k */
180 #define CMP_QUEUE_SZ_1K (1 * 1024)
181 #define CMP_QUEUE_SZ_2K (2 * 1024)
182 #define CMP_QUEUE_SZ_4K (4 * 1024)
183 #define CMP_QUEUE_SZ_8K (8 * 1024)
184 #define CMP_QUEUE_SZ_16K (16 * 1024)
185 #define CMP_QUEUE_SZ_32K (32 * 1024)
186 #define CMP_QUEUE_SZ_64K (64 * 1024)
188 #define CMP_QSIZE_SHIFT (10) /* 1k */
190 #define NICVF_QSIZE_MIN_VAL (0)
191 #define NICVF_QSIZE_MAX_VAL (6)
193 /* Min/Max packet size */
194 #define NIC_HW_MIN_FRS (64)
195 #define NIC_HW_MAX_FRS (9200) /* 9216 max pkt including FCS */
196 #define NIC_HW_MAX_SEGS (12)
198 /* Descriptor alignments */
199 #define NICVF_RBDR_BASE_ALIGN_BYTES (128) /* 7 bits */
200 #define NICVF_CQ_BASE_ALIGN_BYTES (512) /* 9 bits */
201 #define NICVF_SQ_BASE_ALIGN_BYTES (128) /* 7 bits */
203 #define NICVF_CQE_RBPTR_WORD (6)
204 #define NICVF_CQE_RX2_RBPTR_WORD (7)
206 #define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s)
208 typedef uint64_t nicvf_phys_addr_t;
210 #ifndef __BYTE_ORDER__
211 #error __BYTE_ORDER__ not defined
214 /* vNIC HW Enumerations */
216 enum nic_send_ld_type_e {
217 NIC_SEND_LD_TYPE_E_LDD,
218 NIC_SEND_LD_TYPE_E_LDT,
219 NIC_SEND_LD_TYPE_E_LDWB,
220 NIC_SEND_LD_TYPE_E_ENUM_LAST,
223 enum ether_type_algorithm {
228 ETYPE_ALG_VLAN_STRIP,
235 L3TYPE_IPV4_OPTIONS = 0x5,
237 L3TYPE_IPV6_OPTIONS = 0x7,
238 L3TYPE_ET_STOP = 0xD,
242 #define NICVF_L3TYPE_OPTIONS_MASK ((uint8_t)1)
243 #define NICVF_L3TYPE_IPVX_MASK ((uint8_t)0x06)
258 /* CPI and RSSI configuration */
259 enum cpi_algorithm_type {
266 enum rss_algorithm_type {
281 RSS_HASH_TCP_SYN_DIS,
289 /* Completion queue entry types */
293 CQE_TYPE_RX_SPLIT = 0x3,
294 CQE_TYPE_RX_TCP = 0x4,
296 CQE_TYPE_SEND_PTP = 0x9,
299 enum cqe_rx_tcp_status {
300 CQE_RX_STATUS_VALID_TCP_CNXT,
301 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
304 enum cqe_send_status {
305 CQE_SEND_STATUS_GOOD,
306 CQE_SEND_STATUS_DESC_FAULT = 0x01,
307 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
308 CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
309 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
310 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
311 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
312 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
313 CQE_SEND_STATUS_LOCK_VIOL = 0x84,
314 CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
315 CQE_SEND_STATUS_DATA_FAULT = 0x86,
316 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
317 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
318 CQE_SEND_STATUS_MEM_FAULT = 0x89,
319 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
320 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
323 enum cqe_rx_tcp_end_reason {
324 CQE_RX_TCP_END_FIN_FLAG_DET,
325 CQE_RX_TCP_END_INVALID_FLAG,
326 CQE_RX_TCP_END_TIMEOUT,
327 CQE_RX_TCP_END_OUT_OF_SEQ,
328 CQE_RX_TCP_END_PKT_ERR,
329 CQE_RX_TCP_END_QS_DISABLED = 0x0F,
332 /* Packet protocol level error enumeration */
333 enum cqe_rx_err_level {
340 /* Packet protocol level error type enumeration */
341 enum cqe_rx_err_opcode {
343 CQE_RX_ERR_RE_PARTIAL,
344 CQE_RX_ERR_RE_JABBER,
345 CQE_RX_ERR_RE_FCS = 0x7,
346 CQE_RX_ERR_RE_TERMINATE = 0x9,
347 CQE_RX_ERR_RE_RX_CTL = 0xb,
348 CQE_RX_ERR_PREL2_ERR = 0x1f,
349 CQE_RX_ERR_L2_FRAGMENT = 0x20,
350 CQE_RX_ERR_L2_OVERRUN = 0x21,
351 CQE_RX_ERR_L2_PFCS = 0x22,
352 CQE_RX_ERR_L2_PUNY = 0x23,
353 CQE_RX_ERR_L2_MAL = 0x24,
354 CQE_RX_ERR_L2_OVERSIZE = 0x25,
355 CQE_RX_ERR_L2_UNDERSIZE = 0x26,
356 CQE_RX_ERR_L2_LENMISM = 0x27,
357 CQE_RX_ERR_L2_PCLP = 0x28,
358 CQE_RX_ERR_IP_NOT = 0x41,
359 CQE_RX_ERR_IP_CHK = 0x42,
360 CQE_RX_ERR_IP_MAL = 0x43,
361 CQE_RX_ERR_IP_MALD = 0x44,
362 CQE_RX_ERR_IP_HOP = 0x45,
363 CQE_RX_ERR_L3_ICRC = 0x46,
364 CQE_RX_ERR_L3_PCLP = 0x47,
365 CQE_RX_ERR_L4_MAL = 0x61,
366 CQE_RX_ERR_L4_CHK = 0x62,
367 CQE_RX_ERR_UDP_LEN = 0x63,
368 CQE_RX_ERR_L4_PORT = 0x64,
369 CQE_RX_ERR_TCP_FLAG = 0x65,
370 CQE_RX_ERR_TCP_OFFSET = 0x66,
371 CQE_RX_ERR_L4_PCLP = 0x67,
372 CQE_RX_ERR_RBDR_TRUNC = 0x70,
375 enum send_l4_csum_type {
376 SEND_L4_CSUM_DISABLE,
387 enum send_load_type {
393 enum send_mem_alg_type {
395 SEND_MEMALG_ADD = 0x08,
396 SEND_MEMALG_SUB = 0x09,
397 SEND_MEMALG_ADDLEN = 0x0A,
398 SEND_MEMALG_SUBLEN = 0x0B,
401 enum send_mem_dsz_type {
404 SEND_MEMDSZ_B8 = 0x03,
407 enum sq_subdesc_type {
408 SQ_DESC_TYPE_INVALID,
411 SQ_DESC_TYPE_IMMEDIATE,
435 L4_UDP_GENEVE = 0x09,
449 RBDR_FIFO_STATE_INACTIVE,
450 RBDR_FIFO_STATE_ACTIVE,
451 RBDR_FIFO_STATE_RESET,
452 RBDR_FIFO_STATE_FAIL,
455 enum rq_cache_allocation {
458 RQ_CACHE_ALLOC_FIRST,
462 enum cq_rx_errlvl_e {
471 CQ_RX_ERROP_RE_PARTIAL = 0x1,
472 CQ_RX_ERROP_RE_JABBER = 0x2,
473 CQ_RX_ERROP_RE_FCS = 0x7,
474 CQ_RX_ERROP_RE_TERMINATE = 0x9,
475 CQ_RX_ERROP_RE_RX_CTL = 0xb,
476 CQ_RX_ERROP_PREL2_ERR = 0x1f,
477 CQ_RX_ERROP_L2_FRAGMENT = 0x20,
478 CQ_RX_ERROP_L2_OVERRUN = 0x21,
479 CQ_RX_ERROP_L2_PFCS = 0x22,
480 CQ_RX_ERROP_L2_PUNY = 0x23,
481 CQ_RX_ERROP_L2_MAL = 0x24,
482 CQ_RX_ERROP_L2_OVERSIZE = 0x25,
483 CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
484 CQ_RX_ERROP_L2_LENMISM = 0x27,
485 CQ_RX_ERROP_L2_PCLP = 0x28,
486 CQ_RX_ERROP_IP_NOT = 0x41,
487 CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
488 CQ_RX_ERROP_IP_MAL = 0x43,
489 CQ_RX_ERROP_IP_MALD = 0x44,
490 CQ_RX_ERROP_IP_HOP = 0x45,
491 CQ_RX_ERROP_L3_ICRC = 0x46,
492 CQ_RX_ERROP_L3_PCLP = 0x47,
493 CQ_RX_ERROP_L4_MAL = 0x61,
494 CQ_RX_ERROP_L4_CHK = 0x62,
495 CQ_RX_ERROP_UDP_LEN = 0x63,
496 CQ_RX_ERROP_L4_PORT = 0x64,
497 CQ_RX_ERROP_TCP_FLAG = 0x65,
498 CQ_RX_ERROP_TCP_OFFSET = 0x66,
499 CQ_RX_ERROP_L4_PCLP = 0x67,
500 CQ_RX_ERROP_RBDR_TRUNC = 0x70,
505 CQ_TX_ERROP_DESC_FAULT = 0x10,
506 CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
507 CQ_TX_ERROP_SUBDC_ERR = 0x12,
508 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
509 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
510 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
511 CQ_TX_ERROP_LOCK_VIOL = 0x83,
512 CQ_TX_ERROP_DATA_FAULT = 0x84,
513 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
514 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
515 CQ_TX_ERROP_MEM_FAULT = 0x87,
516 CQ_TX_ERROP_CK_OVERLAP = 0x88,
517 CQ_TX_ERROP_CK_OFLOW = 0x89,
518 CQ_TX_ERROP_ENUM_LAST = 0x8a,
521 enum rq_sq_stats_reg_offset {
526 enum nic_stat_vnic_rx_e {
543 enum nic_stat_vnic_tx_e {
551 #endif /* _THUNDERX_NICVF_HW_DEFS_H */