drivers/net/thunderx/base/nicvf_hw_defs.h

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _THUNDERX_NICVF_HW_DEFS_H
  34 #define _THUNDERX_NICVF_HW_DEFS_H
  35
  36 #include <stdint.h>
  37 #include <stdbool.h>
  38
  39 /* Virtual function register offsets */
  40
  41 #define NIC_VF_CFG                      (0x000020)
  42 #define NIC_VF_PF_MAILBOX_0_1           (0x000130)
  43 #define NIC_VF_INT                      (0x000200)
  44 #define NIC_VF_INT_W1S                  (0x000220)
  45 #define NIC_VF_ENA_W1C                  (0x000240)
  46 #define NIC_VF_ENA_W1S                  (0x000260)
  47
  48 #define NIC_VNIC_RSS_CFG                (0x0020E0)
  49 #define NIC_VNIC_RSS_KEY_0_4            (0x002200)
  50 #define NIC_VNIC_TX_STAT_0_4            (0x004000)
  51 #define NIC_VNIC_RX_STAT_0_13           (0x004100)
  52 #define NIC_VNIC_RQ_GEN_CFG             (0x010010)
  53
  54 #define NIC_QSET_CQ_0_7_CFG             (0x010400)
  55 #define NIC_QSET_CQ_0_7_CFG2            (0x010408)
  56 #define NIC_QSET_CQ_0_7_THRESH          (0x010410)
  57 #define NIC_QSET_CQ_0_7_BASE            (0x010420)
  58 #define NIC_QSET_CQ_0_7_HEAD            (0x010428)
  59 #define NIC_QSET_CQ_0_7_TAIL            (0x010430)
  60 #define NIC_QSET_CQ_0_7_DOOR            (0x010438)
  61 #define NIC_QSET_CQ_0_7_STATUS          (0x010440)
  62 #define NIC_QSET_CQ_0_7_STATUS2         (0x010448)
  63 #define NIC_QSET_CQ_0_7_DEBUG           (0x010450)
  64
  65 #define NIC_QSET_RQ_0_7_CFG             (0x010600)
  66 #define NIC_QSET_RQ_0_7_STATUS0         (0x010700)
  67 #define NIC_QSET_RQ_0_7_STATUS1         (0x010708)
  68
  69 #define NIC_QSET_SQ_0_7_CFG             (0x010800)
  70 #define NIC_QSET_SQ_0_7_THRESH          (0x010810)
  71 #define NIC_QSET_SQ_0_7_BASE            (0x010820)
  72 #define NIC_QSET_SQ_0_7_HEAD            (0x010828)
  73 #define NIC_QSET_SQ_0_7_TAIL            (0x010830)
  74 #define NIC_QSET_SQ_0_7_DOOR            (0x010838)
  75 #define NIC_QSET_SQ_0_7_STATUS          (0x010840)
  76 #define NIC_QSET_SQ_0_7_DEBUG           (0x010848)
  77 #define NIC_QSET_SQ_0_7_STATUS0         (0x010900)
  78 #define NIC_QSET_SQ_0_7_STATUS1         (0x010908)
  79
  80 #define NIC_QSET_RBDR_0_1_CFG           (0x010C00)
  81 #define NIC_QSET_RBDR_0_1_THRESH        (0x010C10)
  82 #define NIC_QSET_RBDR_0_1_BASE          (0x010C20)
  83 #define NIC_QSET_RBDR_0_1_HEAD          (0x010C28)
  84 #define NIC_QSET_RBDR_0_1_TAIL          (0x010C30)
  85 #define NIC_QSET_RBDR_0_1_DOOR          (0x010C38)
  86 #define NIC_QSET_RBDR_0_1_STATUS0       (0x010C40)
  87 #define NIC_QSET_RBDR_0_1_STATUS1       (0x010C48)
  88 #define NIC_QSET_RBDR_0_1_PRFCH_STATUS  (0x010C50)
  89
  90 /* vNIC HW Constants */
  91
  92 #define NIC_Q_NUM_SHIFT                 18
  93
  94 #define MAX_QUEUE_SET                   128
  95 #define MAX_RCV_QUEUES_PER_QS           8
  96 #define MAX_RCV_BUF_DESC_RINGS_PER_QS   2
  97 #define MAX_SND_QUEUES_PER_QS           8
  98 #define MAX_CMP_QUEUES_PER_QS           8
  99
 100 #define NICVF_INTR_CQ_SHIFT             0
 101 #define NICVF_INTR_SQ_SHIFT             8
 102 #define NICVF_INTR_RBDR_SHIFT           16
 103 #define NICVF_INTR_PKT_DROP_SHIFT       20
 104 #define NICVF_INTR_TCP_TIMER_SHIFT      21
 105 #define NICVF_INTR_MBOX_SHIFT           22
 106 #define NICVF_INTR_QS_ERR_SHIFT         23
 107
 108 #define NICVF_INTR_CQ_MASK              (0xFF << NICVF_INTR_CQ_SHIFT)
 109 #define NICVF_INTR_SQ_MASK              (0xFF << NICVF_INTR_SQ_SHIFT)
 110 #define NICVF_INTR_RBDR_MASK            (0x03 << NICVF_INTR_RBDR_SHIFT)
 111 #define NICVF_INTR_PKT_DROP_MASK        (1 << NICVF_INTR_PKT_DROP_SHIFT)
 112 #define NICVF_INTR_TCP_TIMER_MASK       (1 << NICVF_INTR_TCP_TIMER_SHIFT)
 113 #define NICVF_INTR_MBOX_MASK            (1 << NICVF_INTR_MBOX_SHIFT)
 114 #define NICVF_INTR_QS_ERR_MASK          (1 << NICVF_INTR_QS_ERR_SHIFT)
 115 #define NICVF_INTR_ALL_MASK             (0x7FFFFF)
 116
 117 #define NICVF_CQ_WR_FULL                (1ULL << 26)
 118 #define NICVF_CQ_WR_DISABLE             (1ULL << 25)
 119 #define NICVF_CQ_WR_FAULT               (1ULL << 24)
 120 #define NICVF_CQ_ERR_MASK               (NICVF_CQ_WR_FULL |\
 121                                          NICVF_CQ_WR_DISABLE |\
 122                                          NICVF_CQ_WR_FAULT)
 123 #define NICVF_CQ_CQE_COUNT_MASK         (0xFFFF)
 124
 125 #define NICVF_SQ_ERR_STOPPED            (1ULL << 21)
 126 #define NICVF_SQ_ERR_SEND               (1ULL << 20)
 127 #define NICVF_SQ_ERR_DPE                (1ULL << 19)
 128 #define NICVF_SQ_ERR_MASK               (NICVF_SQ_ERR_STOPPED |\
 129                                          NICVF_SQ_ERR_SEND |\
 130                                          NICVF_SQ_ERR_DPE)
 131 #define NICVF_SQ_STATUS_STOPPED_BIT     (21)
 132
 133 #define NICVF_RBDR_FIFO_STATE_SHIFT     (62)
 134 #define NICVF_RBDR_FIFO_STATE_MASK      (3ULL << NICVF_RBDR_FIFO_STATE_SHIFT)
 135 #define NICVF_RBDR_COUNT_MASK           (0x7FFFF)
 136
 137 /* Queue reset */
 138 #define NICVF_CQ_RESET                  (1ULL << 41)
 139 #define NICVF_SQ_RESET                  (1ULL << 17)
 140 #define NICVF_RBDR_RESET                (1ULL << 43)
 141
 142 /* RSS constants */
 143 #define NIC_MAX_RSS_HASH_BITS           (8)
 144 #define NIC_MAX_RSS_IDR_TBL_SIZE        (1 << NIC_MAX_RSS_HASH_BITS)
 145 #define RSS_HASH_KEY_SIZE               (5) /* 320 bit key */
 146 #define RSS_HASH_KEY_BYTE_SIZE          (40) /* 320 bit key */
 147
 148 #define RSS_L2_EXTENDED_HASH_ENA        (1 << 0)
 149 #define RSS_IP_ENA                      (1 << 1)
 150 #define RSS_TCP_ENA                     (1 << 2)
 151 #define RSS_TCP_SYN_ENA                 (1 << 3)
 152 #define RSS_UDP_ENA                     (1 << 4)
 153 #define RSS_L4_EXTENDED_ENA             (1 << 5)
 154 #define RSS_L3_BI_DIRECTION_ENA         (1 << 7)
 155 #define RSS_L4_BI_DIRECTION_ENA         (1 << 8)
 156 #define RSS_TUN_VXLAN_ENA               (1 << 9)
 157 #define RSS_TUN_GENEVE_ENA              (1 << 10)
 158 #define RSS_TUN_NVGRE_ENA               (1 << 11)
 159
 160 #define RBDR_QUEUE_SZ_8K                (8 * 1024)
 161 #define RBDR_QUEUE_SZ_16K               (16 * 1024)
 162 #define RBDR_QUEUE_SZ_32K               (32 * 1024)
 163 #define RBDR_QUEUE_SZ_64K               (64 * 1024)
 164 #define RBDR_QUEUE_SZ_128K              (128 * 1024)
 165 #define RBDR_QUEUE_SZ_256K              (256 * 1024)
 166 #define RBDR_QUEUE_SZ_512K              (512 * 1024)
 167
 168 #define RBDR_SIZE_SHIFT                 (13) /* 8k */
 169
 170 #define SND_QUEUE_SZ_1K                 (1 * 1024)
 171 #define SND_QUEUE_SZ_2K                 (2 * 1024)
 172 #define SND_QUEUE_SZ_4K                 (4 * 1024)
 173 #define SND_QUEUE_SZ_8K                 (8 * 1024)
 174 #define SND_QUEUE_SZ_16K                (16 * 1024)
 175 #define SND_QUEUE_SZ_32K                (32 * 1024)
 176 #define SND_QUEUE_SZ_64K                (64 * 1024)
 177
 178 #define SND_QSIZE_SHIFT                 (10) /* 1k */
 179
 180 #define CMP_QUEUE_SZ_1K                 (1 * 1024)
 181 #define CMP_QUEUE_SZ_2K                 (2 * 1024)
 182 #define CMP_QUEUE_SZ_4K                 (4 * 1024)
 183 #define CMP_QUEUE_SZ_8K                 (8 * 1024)
 184 #define CMP_QUEUE_SZ_16K                (16 * 1024)
 185 #define CMP_QUEUE_SZ_32K                (32 * 1024)
 186 #define CMP_QUEUE_SZ_64K                (64 * 1024)
 187
 188 #define CMP_QSIZE_SHIFT                 (10) /* 1k */
 189
 190 #define NICVF_QSIZE_MIN_VAL             (0)
 191 #define NICVF_QSIZE_MAX_VAL             (6)
 192
 193 /* Min/Max packet size */
 194 #define NIC_HW_MIN_FRS                  (64)
 195 #define NIC_HW_MAX_FRS                  (9200) /* 9216 max pkt including FCS */
 196 #define NIC_HW_MAX_SEGS                 (12)
 197
 198 /* Descriptor alignments */
 199 #define NICVF_RBDR_BASE_ALIGN_BYTES     (128) /* 7 bits */
 200 #define NICVF_CQ_BASE_ALIGN_BYTES       (512) /* 9 bits */
 201 #define NICVF_SQ_BASE_ALIGN_BYTES       (128) /* 7 bits */
 202
 203 #define NICVF_CQE_RBPTR_WORD            (6)
 204 #define NICVF_CQE_RX2_RBPTR_WORD        (7)
 205
 206 #define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s)
 207
 208 typedef uint64_t nicvf_phys_addr_t;
 209
 210 #ifndef __BYTE_ORDER__
 211 #error __BYTE_ORDER__ not defined
 212 #endif
 213
 214 /* vNIC HW Enumerations */
 215
 216 enum nic_send_ld_type_e {
 217         NIC_SEND_LD_TYPE_E_LDD,
 218         NIC_SEND_LD_TYPE_E_LDT,
 219         NIC_SEND_LD_TYPE_E_LDWB,
 220         NIC_SEND_LD_TYPE_E_ENUM_LAST,
 221 };
 222
 223 enum ether_type_algorithm {
 224         ETYPE_ALG_NONE,
 225         ETYPE_ALG_SKIP,
 226         ETYPE_ALG_ENDPARSE,
 227         ETYPE_ALG_VLAN,
 228         ETYPE_ALG_VLAN_STRIP,
 229 };
 230
 231 enum layer3_type {
 232         L3TYPE_NONE,
 233         L3TYPE_GRH,
 234         L3TYPE_IPV4 = 0x4,
 235         L3TYPE_IPV4_OPTIONS = 0x5,
 236         L3TYPE_IPV6 = 0x6,
 237         L3TYPE_IPV6_OPTIONS = 0x7,
 238         L3TYPE_ET_STOP = 0xD,
 239         L3TYPE_OTHER = 0xE,
 240 };
 241
 242 #define NICVF_L3TYPE_OPTIONS_MASK       ((uint8_t)1)
 243 #define NICVF_L3TYPE_IPVX_MASK          ((uint8_t)0x06)
 244
 245 enum layer4_type {
 246         L4TYPE_NONE,
 247         L4TYPE_IPSEC_ESP,
 248         L4TYPE_IPFRAG,
 249         L4TYPE_IPCOMP,
 250         L4TYPE_TCP,
 251         L4TYPE_UDP,
 252         L4TYPE_SCTP,
 253         L4TYPE_GRE,
 254         L4TYPE_ROCE_BTH,
 255         L4TYPE_OTHER = 0xE,
 256 };
 257
 258 /* CPI and RSSI configuration */
 259 enum cpi_algorithm_type {
 260         CPI_ALG_NONE,
 261         CPI_ALG_VLAN,
 262         CPI_ALG_VLAN16,
 263         CPI_ALG_DIFF,
 264 };
 265
 266 enum rss_algorithm_type {
 267         RSS_ALG_NONE,
 268         RSS_ALG_PORT,
 269         RSS_ALG_IP,
 270         RSS_ALG_TCP_IP,
 271         RSS_ALG_UDP_IP,
 272         RSS_ALG_SCTP_IP,
 273         RSS_ALG_GRE_IP,
 274         RSS_ALG_ROCE,
 275 };
 276
 277 enum rss_hash_cfg {
 278         RSS_HASH_L2ETC,
 279         RSS_HASH_IP,
 280         RSS_HASH_TCP,
 281         RSS_HASH_TCP_SYN_DIS,
 282         RSS_HASH_UDP,
 283         RSS_HASH_L4ETC,
 284         RSS_HASH_ROCE,
 285         RSS_L3_BIDI,
 286         RSS_L4_BIDI,
 287 };
 288
 289 /* Completion queue entry types */
 290 enum cqe_type {
 291         CQE_TYPE_INVALID,
 292         CQE_TYPE_RX = 0x2,
 293         CQE_TYPE_RX_SPLIT = 0x3,
 294         CQE_TYPE_RX_TCP = 0x4,
 295         CQE_TYPE_SEND = 0x8,
 296         CQE_TYPE_SEND_PTP = 0x9,
 297 };
 298
 299 enum cqe_rx_tcp_status {
 300         CQE_RX_STATUS_VALID_TCP_CNXT,
 301         CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
 302 };
 303
 304 enum cqe_send_status {
 305         CQE_SEND_STATUS_GOOD,
 306         CQE_SEND_STATUS_DESC_FAULT = 0x01,
 307         CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
 308         CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
 309         CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
 310         CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
 311         CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
 312         CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
 313         CQE_SEND_STATUS_LOCK_VIOL = 0x84,
 314         CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
 315         CQE_SEND_STATUS_DATA_FAULT = 0x86,
 316         CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
 317         CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
 318         CQE_SEND_STATUS_MEM_FAULT = 0x89,
 319         CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
 320         CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
 321 };
 322
 323 enum cqe_rx_tcp_end_reason {
 324         CQE_RX_TCP_END_FIN_FLAG_DET,
 325         CQE_RX_TCP_END_INVALID_FLAG,
 326         CQE_RX_TCP_END_TIMEOUT,
 327         CQE_RX_TCP_END_OUT_OF_SEQ,
 328         CQE_RX_TCP_END_PKT_ERR,
 329         CQE_RX_TCP_END_QS_DISABLED = 0x0F,
 330 };
 331
 332 /* Packet protocol level error enumeration */
 333 enum cqe_rx_err_level {
 334         CQE_RX_ERRLVL_RE,
 335         CQE_RX_ERRLVL_L2,
 336         CQE_RX_ERRLVL_L3,
 337         CQE_RX_ERRLVL_L4,
 338 };
 339
 340 /* Packet protocol level error type enumeration */
 341 enum cqe_rx_err_opcode {
 342         CQE_RX_ERR_RE_NONE,
 343         CQE_RX_ERR_RE_PARTIAL,
 344         CQE_RX_ERR_RE_JABBER,
 345         CQE_RX_ERR_RE_FCS = 0x7,
 346         CQE_RX_ERR_RE_TERMINATE = 0x9,
 347         CQE_RX_ERR_RE_RX_CTL = 0xb,
 348         CQE_RX_ERR_PREL2_ERR = 0x1f,
 349         CQE_RX_ERR_L2_FRAGMENT = 0x20,
 350         CQE_RX_ERR_L2_OVERRUN = 0x21,
 351         CQE_RX_ERR_L2_PFCS = 0x22,
 352         CQE_RX_ERR_L2_PUNY = 0x23,
 353         CQE_RX_ERR_L2_MAL = 0x24,
 354         CQE_RX_ERR_L2_OVERSIZE = 0x25,
 355         CQE_RX_ERR_L2_UNDERSIZE = 0x26,
 356         CQE_RX_ERR_L2_LENMISM = 0x27,
 357         CQE_RX_ERR_L2_PCLP = 0x28,
 358         CQE_RX_ERR_IP_NOT = 0x41,
 359         CQE_RX_ERR_IP_CHK = 0x42,
 360         CQE_RX_ERR_IP_MAL = 0x43,
 361         CQE_RX_ERR_IP_MALD = 0x44,
 362         CQE_RX_ERR_IP_HOP = 0x45,
 363         CQE_RX_ERR_L3_ICRC = 0x46,
 364         CQE_RX_ERR_L3_PCLP = 0x47,
 365         CQE_RX_ERR_L4_MAL = 0x61,
 366         CQE_RX_ERR_L4_CHK = 0x62,
 367         CQE_RX_ERR_UDP_LEN = 0x63,
 368         CQE_RX_ERR_L4_PORT = 0x64,
 369         CQE_RX_ERR_TCP_FLAG = 0x65,
 370         CQE_RX_ERR_TCP_OFFSET = 0x66,
 371         CQE_RX_ERR_L4_PCLP = 0x67,
 372         CQE_RX_ERR_RBDR_TRUNC = 0x70,
 373 };
 374
 375 enum send_l4_csum_type {
 376         SEND_L4_CSUM_DISABLE,
 377         SEND_L4_CSUM_UDP,
 378         SEND_L4_CSUM_TCP,
 379 };
 380
 381 enum send_crc_alg {
 382         SEND_CRCALG_CRC32,
 383         SEND_CRCALG_CRC32C,
 384         SEND_CRCALG_ICRC,
 385 };
 386
 387 enum send_load_type {
 388         SEND_LD_TYPE_LDD,
 389         SEND_LD_TYPE_LDT,
 390         SEND_LD_TYPE_LDWB,
 391 };
 392
 393 enum send_mem_alg_type {
 394         SEND_MEMALG_SET,
 395         SEND_MEMALG_ADD = 0x08,
 396         SEND_MEMALG_SUB = 0x09,
 397         SEND_MEMALG_ADDLEN = 0x0A,
 398         SEND_MEMALG_SUBLEN = 0x0B,
 399 };
 400
 401 enum send_mem_dsz_type {
 402         SEND_MEMDSZ_B64,
 403         SEND_MEMDSZ_B32,
 404         SEND_MEMDSZ_B8 = 0x03,
 405 };
 406
 407 enum sq_subdesc_type {
 408         SQ_DESC_TYPE_INVALID,
 409         SQ_DESC_TYPE_HEADER,
 410         SQ_DESC_TYPE_CRC,
 411         SQ_DESC_TYPE_IMMEDIATE,
 412         SQ_DESC_TYPE_GATHER,
 413         SQ_DESC_TYPE_MEMORY,
 414 };
 415
 416 enum l3_type_t {
 417         L3_NONE,
 418         L3_IPV4         = 0x04,
 419         L3_IPV4_OPT     = 0x05,
 420         L3_IPV6         = 0x06,
 421         L3_IPV6_OPT     = 0x07,
 422         L3_ET_STOP      = 0x0D,
 423         L3_OTHER        = 0x0E
 424 };
 425
 426 enum l4_type_t {
 427         L4_NONE,
 428         L4_IPSEC_ESP    = 0x01,
 429         L4_IPFRAG       = 0x02,
 430         L4_IPCOMP       = 0x03,
 431         L4_TCP          = 0x04,
 432         L4_UDP_PASS1    = 0x05,
 433         L4_GRE          = 0x07,
 434         L4_UDP_PASS2    = 0x08,
 435         L4_UDP_GENEVE   = 0x09,
 436         L4_UDP_VXLAN    = 0x0A,
 437         L4_NVGRE        = 0x0C,
 438         L4_OTHER        = 0x0E
 439 };
 440
 441 enum vlan_strip {
 442         NO_STRIP,
 443         STRIP_FIRST_VLAN,
 444         STRIP_SECOND_VLAN,
 445         STRIP_RESERV,
 446 };
 447
 448 enum rbdr_state {
 449         RBDR_FIFO_STATE_INACTIVE,
 450         RBDR_FIFO_STATE_ACTIVE,
 451         RBDR_FIFO_STATE_RESET,
 452         RBDR_FIFO_STATE_FAIL,
 453 };
 454
 455 enum rq_cache_allocation {
 456         RQ_CACHE_ALLOC_OFF,
 457         RQ_CACHE_ALLOC_ALL,
 458         RQ_CACHE_ALLOC_FIRST,
 459         RQ_CACHE_ALLOC_TWO,
 460 };
 461
 462 enum cq_rx_errlvl_e {
 463         CQ_ERRLVL_MAC,
 464         CQ_ERRLVL_L2,
 465         CQ_ERRLVL_L3,
 466         CQ_ERRLVL_L4,
 467 };
 468
 469 enum cq_rx_errop_e {
 470         CQ_RX_ERROP_RE_NONE,
 471         CQ_RX_ERROP_RE_PARTIAL = 0x1,
 472         CQ_RX_ERROP_RE_JABBER = 0x2,
 473         CQ_RX_ERROP_RE_FCS = 0x7,
 474         CQ_RX_ERROP_RE_TERMINATE = 0x9,
 475         CQ_RX_ERROP_RE_RX_CTL = 0xb,
 476         CQ_RX_ERROP_PREL2_ERR = 0x1f,
 477         CQ_RX_ERROP_L2_FRAGMENT = 0x20,
 478         CQ_RX_ERROP_L2_OVERRUN = 0x21,
 479         CQ_RX_ERROP_L2_PFCS = 0x22,
 480         CQ_RX_ERROP_L2_PUNY = 0x23,
 481         CQ_RX_ERROP_L2_MAL = 0x24,
 482         CQ_RX_ERROP_L2_OVERSIZE = 0x25,
 483         CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
 484         CQ_RX_ERROP_L2_LENMISM = 0x27,
 485         CQ_RX_ERROP_L2_PCLP = 0x28,
 486         CQ_RX_ERROP_IP_NOT = 0x41,
 487         CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
 488         CQ_RX_ERROP_IP_MAL = 0x43,
 489         CQ_RX_ERROP_IP_MALD = 0x44,
 490         CQ_RX_ERROP_IP_HOP = 0x45,
 491         CQ_RX_ERROP_L3_ICRC = 0x46,
 492         CQ_RX_ERROP_L3_PCLP = 0x47,
 493         CQ_RX_ERROP_L4_MAL = 0x61,
 494         CQ_RX_ERROP_L4_CHK = 0x62,
 495         CQ_RX_ERROP_UDP_LEN = 0x63,
 496         CQ_RX_ERROP_L4_PORT = 0x64,
 497         CQ_RX_ERROP_TCP_FLAG = 0x65,
 498         CQ_RX_ERROP_TCP_OFFSET = 0x66,
 499         CQ_RX_ERROP_L4_PCLP = 0x67,
 500         CQ_RX_ERROP_RBDR_TRUNC = 0x70,
 501 };
 502
 503 enum cq_tx_errop_e {
 504         CQ_TX_ERROP_GOOD,
 505         CQ_TX_ERROP_DESC_FAULT = 0x10,
 506         CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
 507         CQ_TX_ERROP_SUBDC_ERR = 0x12,
 508         CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
 509         CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
 510         CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
 511         CQ_TX_ERROP_LOCK_VIOL = 0x83,
 512         CQ_TX_ERROP_DATA_FAULT = 0x84,
 513         CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
 514         CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
 515         CQ_TX_ERROP_MEM_FAULT = 0x87,
 516         CQ_TX_ERROP_CK_OVERLAP = 0x88,
 517         CQ_TX_ERROP_CK_OFLOW = 0x89,
 518         CQ_TX_ERROP_ENUM_LAST = 0x8a,
 519 };
 520
 521 enum rq_sq_stats_reg_offset {
 522         RQ_SQ_STATS_OCTS,
 523         RQ_SQ_STATS_PKTS,
 524 };
 525
 526 enum nic_stat_vnic_rx_e {
 527         RX_OCTS,
 528         RX_UCAST,
 529         RX_BCAST,
 530         RX_MCAST,
 531         RX_RED,
 532         RX_RED_OCTS,
 533         RX_ORUN,
 534         RX_ORUN_OCTS,
 535         RX_FCS,
 536         RX_L2ERR,
 537         RX_DRP_BCAST,
 538         RX_DRP_MCAST,
 539         RX_DRP_L3BCAST,
 540         RX_DRP_L3MCAST,
 541 };
 542
 543 enum nic_stat_vnic_tx_e {
 544         TX_OCTS,
 545         TX_UCAST,
 546         TX_BCAST,
 547         TX_MCAST,
 548         TX_DROP,
 549 };
 550
 551 #endif /* _THUNDERX_NICVF_HW_DEFS_H */