1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016 Cavium, Inc
5 #ifndef _THUNDERX_NICVF_HW_DEFS_H
6 #define _THUNDERX_NICVF_HW_DEFS_H
11 #include "nicvf_plat.h"
13 /* Virtual function register offsets */
15 #define NIC_VF_CFG (0x000020)
16 #define NIC_VF_PF_MAILBOX_0_1 (0x000130)
17 #define NIC_VF_INT (0x000200)
18 #define NIC_VF_INT_W1S (0x000220)
19 #define NIC_VF_ENA_W1C (0x000240)
20 #define NIC_VF_ENA_W1S (0x000260)
22 #define NIC_VNIC_RSS_CFG (0x0020E0)
23 #define NIC_VNIC_RSS_KEY_0_4 (0x002200)
24 #define NIC_VNIC_TX_STAT_0_4 (0x004000)
25 #define NIC_VNIC_RX_STAT_0_13 (0x004100)
26 #define NIC_VNIC_RQ_GEN_CFG (0x010010)
28 #define NIC_QSET_CQ_0_7_CFG (0x010400)
29 #define NIC_QSET_CQ_0_7_CFG2 (0x010408)
30 #define NIC_QSET_CQ_0_7_THRESH (0x010410)
31 #define NIC_QSET_CQ_0_7_BASE (0x010420)
32 #define NIC_QSET_CQ_0_7_HEAD (0x010428)
33 #define NIC_QSET_CQ_0_7_TAIL (0x010430)
34 #define NIC_QSET_CQ_0_7_DOOR (0x010438)
35 #define NIC_QSET_CQ_0_7_STATUS (0x010440)
36 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448)
37 #define NIC_QSET_CQ_0_7_DEBUG (0x010450)
39 #define NIC_QSET_RQ_0_7_CFG (0x010600)
40 #define NIC_QSET_RQ_0_7_STATUS0 (0x010700)
41 #define NIC_QSET_RQ_0_7_STATUS1 (0x010708)
43 #define NIC_QSET_SQ_0_7_CFG (0x010800)
44 #define NIC_QSET_SQ_0_7_THRESH (0x010810)
45 #define NIC_QSET_SQ_0_7_BASE (0x010820)
46 #define NIC_QSET_SQ_0_7_HEAD (0x010828)
47 #define NIC_QSET_SQ_0_7_TAIL (0x010830)
48 #define NIC_QSET_SQ_0_7_DOOR (0x010838)
49 #define NIC_QSET_SQ_0_7_STATUS (0x010840)
50 #define NIC_QSET_SQ_0_7_DEBUG (0x010848)
51 #define NIC_QSET_SQ_0_7_STATUS0 (0x010900)
52 #define NIC_QSET_SQ_0_7_STATUS1 (0x010908)
54 #define NIC_QSET_RBDR_0_1_CFG (0x010C00)
55 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10)
56 #define NIC_QSET_RBDR_0_1_BASE (0x010C20)
57 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28)
58 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30)
59 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38)
60 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40)
61 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48)
62 #define NIC_QSET_RBDR_0_1_PRFCH_STATUS (0x010C50)
64 /* vNIC HW Constants */
66 #define NIC_Q_NUM_SHIFT 18
68 #define MAX_QUEUE_SET 128
69 #define MAX_RCV_QUEUES_PER_QS 8
70 #define MAX_RCV_BUF_DESC_RINGS_PER_QS 2
71 #define MAX_SND_QUEUES_PER_QS 8
72 #define MAX_CMP_QUEUES_PER_QS 8
74 #define NICVF_INTR_CQ_SHIFT 0
75 #define NICVF_INTR_SQ_SHIFT 8
76 #define NICVF_INTR_RBDR_SHIFT 16
77 #define NICVF_INTR_PKT_DROP_SHIFT 20
78 #define NICVF_INTR_TCP_TIMER_SHIFT 21
79 #define NICVF_INTR_MBOX_SHIFT 22
80 #define NICVF_INTR_QS_ERR_SHIFT 23
82 #define NICVF_QS_RQ_DIS_APAD_SHIFT 22
84 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
85 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
86 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
87 #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT)
88 #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT)
89 #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT)
90 #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT)
91 #define NICVF_INTR_ALL_MASK (0x7FFFFF)
93 #define NICVF_CQ_WR_FULL (1ULL << 26)
94 #define NICVF_CQ_WR_DISABLE (1ULL << 25)
95 #define NICVF_CQ_WR_FAULT (1ULL << 24)
96 #define NICVF_CQ_ERR_MASK (NICVF_CQ_WR_FULL |\
97 NICVF_CQ_WR_DISABLE |\
99 #define NICVF_CQ_CQE_COUNT_MASK (0xFFFF)
101 #define NICVF_SQ_ERR_STOPPED (1ULL << 21)
102 #define NICVF_SQ_ERR_SEND (1ULL << 20)
103 #define NICVF_SQ_ERR_DPE (1ULL << 19)
104 #define NICVF_SQ_ERR_MASK (NICVF_SQ_ERR_STOPPED |\
107 #define NICVF_SQ_STATUS_STOPPED_BIT (21)
109 #define NICVF_RBDR_FIFO_STATE_SHIFT (62)
110 #define NICVF_RBDR_FIFO_STATE_MASK (3ULL << NICVF_RBDR_FIFO_STATE_SHIFT)
111 #define NICVF_RBDR_COUNT_MASK (0x7FFFF)
114 #define NICVF_CQ_RESET (1ULL << 41)
115 #define NICVF_SQ_RESET (1ULL << 17)
116 #define NICVF_RBDR_RESET (1ULL << 43)
119 #define NIC_MAX_RSS_HASH_BITS (8)
120 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
121 #define RSS_HASH_KEY_SIZE (5) /* 320 bit key */
122 #define RSS_HASH_KEY_BYTE_SIZE (40) /* 320 bit key */
124 #define RSS_L2_EXTENDED_HASH_ENA (1 << 0)
125 #define RSS_IP_ENA (1 << 1)
126 #define RSS_TCP_ENA (1 << 2)
127 #define RSS_TCP_SYN_ENA (1 << 3)
128 #define RSS_UDP_ENA (1 << 4)
129 #define RSS_L4_EXTENDED_ENA (1 << 5)
130 #define RSS_L3_BI_DIRECTION_ENA (1 << 7)
131 #define RSS_L4_BI_DIRECTION_ENA (1 << 8)
132 #define RSS_TUN_VXLAN_ENA (1 << 9)
133 #define RSS_TUN_GENEVE_ENA (1 << 10)
134 #define RSS_TUN_NVGRE_ENA (1 << 11)
136 #define RBDR_QUEUE_SZ_8K (8 * 1024)
137 #define RBDR_QUEUE_SZ_16K (16 * 1024)
138 #define RBDR_QUEUE_SZ_32K (32 * 1024)
139 #define RBDR_QUEUE_SZ_64K (64 * 1024)
140 #define RBDR_QUEUE_SZ_128K (128 * 1024)
141 #define RBDR_QUEUE_SZ_256K (256 * 1024)
142 #define RBDR_QUEUE_SZ_512K (512 * 1024)
143 #define RBDR_QUEUE_SZ_MAX RBDR_QUEUE_SZ_512K
145 #define RBDR_SIZE_SHIFT (13) /* 8k */
147 #define SND_QUEUE_SZ_1K (1 * 1024)
148 #define SND_QUEUE_SZ_2K (2 * 1024)
149 #define SND_QUEUE_SZ_4K (4 * 1024)
150 #define SND_QUEUE_SZ_8K (8 * 1024)
151 #define SND_QUEUE_SZ_16K (16 * 1024)
152 #define SND_QUEUE_SZ_32K (32 * 1024)
153 #define SND_QUEUE_SZ_64K (64 * 1024)
154 #define SND_QUEUE_SZ_MAX SND_QUEUE_SZ_64K
156 #define SND_QSIZE_SHIFT (10) /* 1k */
158 #define CMP_QUEUE_SZ_1K (1 * 1024)
159 #define CMP_QUEUE_SZ_2K (2 * 1024)
160 #define CMP_QUEUE_SZ_4K (4 * 1024)
161 #define CMP_QUEUE_SZ_8K (8 * 1024)
162 #define CMP_QUEUE_SZ_16K (16 * 1024)
163 #define CMP_QUEUE_SZ_32K (32 * 1024)
164 #define CMP_QUEUE_SZ_64K (64 * 1024)
165 #define CMP_QUEUE_SZ_MAX CMP_QUEUE_SZ_64K
167 #define CMP_QSIZE_SHIFT (10) /* 1k */
169 #define NICVF_QSIZE_MIN_VAL (0)
170 #define NICVF_QSIZE_MAX_VAL (6)
172 /* Min/Max packet size */
173 #define NIC_HW_MIN_FRS (64)
174 #define NIC_HW_MAX_FRS (9200) /* 9216 max pkt including FCS */
175 #define NIC_HW_MAX_SEGS (12)
177 /* Descriptor alignments */
178 #define NICVF_RBDR_BASE_ALIGN_BYTES (128) /* 7 bits */
179 #define NICVF_CQ_BASE_ALIGN_BYTES (512) /* 9 bits */
180 #define NICVF_SQ_BASE_ALIGN_BYTES (128) /* 7 bits */
182 #define NICVF_CQE_RBPTR_WORD (6)
183 #define NICVF_CQE_RX2_RBPTR_WORD (7)
185 #define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s)
186 #define assert_primary(nic) assert((nic)->sqs_mode == 0)
188 typedef uint64_t nicvf_iova_addr_t;
190 /* vNIC HW Enumerations */
192 enum nic_send_ld_type_e {
193 NIC_SEND_LD_TYPE_E_LDD,
194 NIC_SEND_LD_TYPE_E_LDT,
195 NIC_SEND_LD_TYPE_E_LDWB,
196 NIC_SEND_LD_TYPE_E_ENUM_LAST,
199 enum ether_type_algorithm {
204 ETYPE_ALG_VLAN_STRIP,
211 L3TYPE_IPV4_OPTIONS = 0x5,
213 L3TYPE_IPV6_OPTIONS = 0x7,
214 L3TYPE_ET_STOP = 0xD,
218 #define NICVF_L3TYPE_OPTIONS_MASK ((uint8_t)1)
219 #define NICVF_L3TYPE_IPVX_MASK ((uint8_t)0x06)
234 /* CPI and RSSI configuration */
235 enum cpi_algorithm_type {
242 enum rss_algorithm_type {
257 RSS_HASH_TCP_SYN_DIS,
265 /* Completion queue entry types */
269 CQE_TYPE_RX_SPLIT = 0x3,
270 CQE_TYPE_RX_TCP = 0x4,
272 CQE_TYPE_SEND_PTP = 0x9,
275 enum cqe_rx_tcp_status {
276 CQE_RX_STATUS_VALID_TCP_CNXT,
277 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
280 enum cqe_send_status {
281 CQE_SEND_STATUS_GOOD,
282 CQE_SEND_STATUS_DESC_FAULT = 0x01,
283 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
284 CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
285 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
286 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
287 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
288 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
289 CQE_SEND_STATUS_LOCK_VIOL = 0x84,
290 CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
291 CQE_SEND_STATUS_DATA_FAULT = 0x86,
292 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
293 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
294 CQE_SEND_STATUS_MEM_FAULT = 0x89,
295 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
296 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
299 enum cqe_rx_tcp_end_reason {
300 CQE_RX_TCP_END_FIN_FLAG_DET,
301 CQE_RX_TCP_END_INVALID_FLAG,
302 CQE_RX_TCP_END_TIMEOUT,
303 CQE_RX_TCP_END_OUT_OF_SEQ,
304 CQE_RX_TCP_END_PKT_ERR,
305 CQE_RX_TCP_END_QS_DISABLED = 0x0F,
308 /* Packet protocol level error enumeration */
309 enum cqe_rx_err_level {
316 /* Packet protocol level error type enumeration */
317 enum cqe_rx_err_opcode {
319 CQE_RX_ERR_RE_PARTIAL,
320 CQE_RX_ERR_RE_JABBER,
321 CQE_RX_ERR_RE_FCS = 0x7,
322 CQE_RX_ERR_RE_TERMINATE = 0x9,
323 CQE_RX_ERR_RE_RX_CTL = 0xb,
324 CQE_RX_ERR_PREL2_ERR = 0x1f,
325 CQE_RX_ERR_L2_FRAGMENT = 0x20,
326 CQE_RX_ERR_L2_OVERRUN = 0x21,
327 CQE_RX_ERR_L2_PFCS = 0x22,
328 CQE_RX_ERR_L2_PUNY = 0x23,
329 CQE_RX_ERR_L2_MAL = 0x24,
330 CQE_RX_ERR_L2_OVERSIZE = 0x25,
331 CQE_RX_ERR_L2_UNDERSIZE = 0x26,
332 CQE_RX_ERR_L2_LENMISM = 0x27,
333 CQE_RX_ERR_L2_PCLP = 0x28,
334 CQE_RX_ERR_IP_NOT = 0x41,
335 CQE_RX_ERR_IP_CHK = 0x42,
336 CQE_RX_ERR_IP_MAL = 0x43,
337 CQE_RX_ERR_IP_MALD = 0x44,
338 CQE_RX_ERR_IP_HOP = 0x45,
339 CQE_RX_ERR_L3_ICRC = 0x46,
340 CQE_RX_ERR_L3_PCLP = 0x47,
341 CQE_RX_ERR_L4_MAL = 0x61,
342 CQE_RX_ERR_L4_CHK = 0x62,
343 CQE_RX_ERR_UDP_LEN = 0x63,
344 CQE_RX_ERR_L4_PORT = 0x64,
345 CQE_RX_ERR_TCP_FLAG = 0x65,
346 CQE_RX_ERR_TCP_OFFSET = 0x66,
347 CQE_RX_ERR_L4_PCLP = 0x67,
348 CQE_RX_ERR_RBDR_TRUNC = 0x70,
351 enum send_l4_csum_type {
352 SEND_L4_CSUM_DISABLE,
363 enum send_load_type {
369 enum send_mem_alg_type {
371 SEND_MEMALG_ADD = 0x08,
372 SEND_MEMALG_SUB = 0x09,
373 SEND_MEMALG_ADDLEN = 0x0A,
374 SEND_MEMALG_SUBLEN = 0x0B,
377 enum send_mem_dsz_type {
380 SEND_MEMDSZ_B8 = 0x03,
383 enum sq_subdesc_type {
384 SQ_DESC_TYPE_INVALID,
387 SQ_DESC_TYPE_IMMEDIATE,
411 L4_UDP_GENEVE = 0x09,
425 RBDR_FIFO_STATE_INACTIVE,
426 RBDR_FIFO_STATE_ACTIVE,
427 RBDR_FIFO_STATE_RESET,
428 RBDR_FIFO_STATE_FAIL,
431 enum rq_cache_allocation {
434 RQ_CACHE_ALLOC_FIRST,
438 enum cq_rx_errlvl_e {
447 CQ_RX_ERROP_RE_PARTIAL = 0x1,
448 CQ_RX_ERROP_RE_JABBER = 0x2,
449 CQ_RX_ERROP_RE_FCS = 0x7,
450 CQ_RX_ERROP_RE_TERMINATE = 0x9,
451 CQ_RX_ERROP_RE_RX_CTL = 0xb,
452 CQ_RX_ERROP_PREL2_ERR = 0x1f,
453 CQ_RX_ERROP_L2_FRAGMENT = 0x20,
454 CQ_RX_ERROP_L2_OVERRUN = 0x21,
455 CQ_RX_ERROP_L2_PFCS = 0x22,
456 CQ_RX_ERROP_L2_PUNY = 0x23,
457 CQ_RX_ERROP_L2_MAL = 0x24,
458 CQ_RX_ERROP_L2_OVERSIZE = 0x25,
459 CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
460 CQ_RX_ERROP_L2_LENMISM = 0x27,
461 CQ_RX_ERROP_L2_PCLP = 0x28,
462 CQ_RX_ERROP_IP_NOT = 0x41,
463 CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
464 CQ_RX_ERROP_IP_MAL = 0x43,
465 CQ_RX_ERROP_IP_MALD = 0x44,
466 CQ_RX_ERROP_IP_HOP = 0x45,
467 CQ_RX_ERROP_L3_ICRC = 0x46,
468 CQ_RX_ERROP_L3_PCLP = 0x47,
469 CQ_RX_ERROP_L4_MAL = 0x61,
470 CQ_RX_ERROP_L4_CHK = 0x62,
471 CQ_RX_ERROP_UDP_LEN = 0x63,
472 CQ_RX_ERROP_L4_PORT = 0x64,
473 CQ_RX_ERROP_TCP_FLAG = 0x65,
474 CQ_RX_ERROP_TCP_OFFSET = 0x66,
475 CQ_RX_ERROP_L4_PCLP = 0x67,
476 CQ_RX_ERROP_RBDR_TRUNC = 0x70,
481 CQ_TX_ERROP_DESC_FAULT = 0x10,
482 CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
483 CQ_TX_ERROP_SUBDC_ERR = 0x12,
484 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
485 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
486 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
487 CQ_TX_ERROP_LOCK_VIOL = 0x83,
488 CQ_TX_ERROP_DATA_FAULT = 0x84,
489 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
490 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
491 CQ_TX_ERROP_MEM_FAULT = 0x87,
492 CQ_TX_ERROP_CK_OVERLAP = 0x88,
493 CQ_TX_ERROP_CK_OFLOW = 0x89,
494 CQ_TX_ERROP_ENUM_LAST = 0x8a,
497 enum rq_sq_stats_reg_offset {
502 enum nic_stat_vnic_rx_e {
519 enum nic_stat_vnic_tx_e {
527 /* vNIC HW Register structures */
532 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
534 uint64_t stdn_fault:1;
542 uint64_t vlan_found:1;
543 uint64_t vlan_stripped:1;
544 uint64_t vlan2_found:1;
545 uint64_t vlan2_stripped:1;
548 uint64_t l2_present:1;
549 uint64_t err_level:3;
550 uint64_t err_opcode:8;
552 uint64_t err_opcode:8;
553 uint64_t err_level:3;
554 uint64_t l2_present:1;
557 uint64_t vlan2_stripped:1;
558 uint64_t vlan2_found:1;
559 uint64_t vlan_stripped:1;
560 uint64_t vlan_found:1;
568 uint64_t stdn_fault:1;
577 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
582 uint64_t cq_pkt_len:8;
583 uint64_t align_pad:3;
589 uint64_t align_pad:3;
590 uint64_t cq_pkt_len:8;
602 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
604 uint64_t vlan_tci:16;
606 uint64_t vlan2_ptr:8;
608 uint64_t vlan2_ptr:8;
610 uint64_t vlan_tci:16;
619 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
636 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
653 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
670 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
671 uint64_t vlan_found:1;
672 uint64_t vlan_stripped:1;
673 uint64_t vlan2_found:1;
674 uint64_t vlan2_stripped:1;
677 uint64_t inner_l4type:4;
678 uint64_t inner_l3type:4;
680 uint64_t vlan2_ptr:8;
683 uint64_t inner_l3ptr:8;
684 uint64_t inner_l4ptr:8;
686 uint64_t inner_l4ptr:8;
687 uint64_t inner_l3ptr:8;
690 uint64_t vlan2_ptr:8;
692 uint64_t inner_l3type:4;
693 uint64_t inner_l4type:4;
696 uint64_t vlan2_stripped:1;
697 uint64_t vlan2_found:1;
698 uint64_t vlan_stripped:1;
699 uint64_t vlan_found:1;
705 cqe_rx_word0_t word0;
706 cqe_rx_word1_t word1;
707 cqe_rx_word2_t word2;
708 cqe_rx_word3_t word3;
709 cqe_rx_word4_t word4;
710 cqe_rx_word5_t word5;
711 cqe_rx2_word6_t word6; /* if NIC_PF_RX_CFG[CQE_RX2_ENA] set */
714 struct cqe_rx_tcp_err_t {
715 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
716 uint64_t cqe_type:4; /* W0 */
719 uint64_t rsvd1:4; /* W1 */
720 uint64_t partial_first:1;
722 uint64_t rbdr_bytes:8;
729 uint64_t rbdr_bytes:8;
731 uint64_t partial_first:1;
736 struct cqe_rx_tcp_t {
737 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
738 uint64_t cqe_type:4; /* W0 */
740 uint64_t cq_tcp_status:8;
742 uint64_t rsvd1:32; /* W1 */
743 uint64_t tcp_cntx_bytes:8;
745 uint64_t tcp_err_bytes:16;
747 uint64_t cq_tcp_status:8;
749 uint64_t cqe_type:4; /* W0 */
751 uint64_t tcp_err_bytes:16;
753 uint64_t tcp_cntx_bytes:8;
754 uint64_t rsvd1:32; /* W1 */
759 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
760 uint64_t cqe_type:4; /* W0 */
768 uint64_t send_status:8;
770 uint64_t ptp_timestamp:64; /* W1 */
771 #elif NICVF_BYTE_ORDER == NICVF_LITTLE_ENDIAN
772 uint64_t send_status:8;
780 uint64_t cqe_type:4; /* W0 */
782 uint64_t ptp_timestamp:64;
786 struct cq_entry_type_t {
787 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
798 struct cq_entry_type_t type;
799 struct cqe_rx_t rx_hdr;
800 struct cqe_rx_tcp_t rx_tcp_hdr;
801 struct cqe_rx_tcp_err_t rx_tcp_err_hdr;
802 struct cqe_send_t cqe_send;
805 NICVF_STATIC_ASSERT(sizeof(union cq_entry_t) == 512);
807 struct rbdr_entry_t {
808 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
812 uint64_t buf_addr:42;
813 uint64_t cache_align:7;
815 nicvf_iova_addr_t full_addr;
820 uint64_t cache_align:7;
821 uint64_t buf_addr:42;
824 nicvf_iova_addr_t full_addr;
829 NICVF_STATIC_ASSERT(sizeof(struct rbdr_entry_t) == sizeof(uint64_t));
831 /* TCP reassembly context */
832 struct rbe_tcp_cnxt_t {
833 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
834 uint64_t tcp_pkt_cnt:12;
836 uint64_t align_hdr_bytes:4;
837 uint64_t align_ptr_bytes:4;
838 uint64_t ptr_bytes:16;
842 uint64_t tcp_end_reason:2;
843 uint64_t tcp_status:4;
845 uint64_t tcp_status:4;
846 uint64_t tcp_end_reason:2;
850 uint64_t ptr_bytes:16;
851 uint64_t align_ptr_bytes:4;
852 uint64_t align_hdr_bytes:4;
854 uint64_t tcp_pkt_cnt:12;
858 /* Always Big endian */
862 uint64_t skip_length:6;
863 uint64_t disable_rss:1;
864 uint64_t disable_tcp_reassembly:1;
871 struct sq_crc_subdesc {
872 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
874 uint64_t crc_ival:32;
875 uint64_t subdesc_type:4;
878 uint64_t crc_insert_pos:16;
879 uint64_t hdr_start:16;
883 uint64_t hdr_start:16;
884 uint64_t crc_insert_pos:16;
887 uint64_t subdesc_type:4;
888 uint64_t crc_ival:32;
893 struct sq_gather_subdesc {
894 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
895 uint64_t subdesc_type:4; /* W0 */
900 uint64_t rsvd1:15; /* W1 */
906 uint64_t subdesc_type:4; /* W0 */
909 uint64_t rsvd1:15; /* W1 */
913 /* SQ immediate subdescriptor */
914 struct sq_imm_subdesc {
915 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
916 uint64_t subdesc_type:4; /* W0 */
920 uint64_t data:64; /* W1 */
924 uint64_t subdesc_type:4; /* W0 */
926 uint64_t data:64; /* W1 */
930 struct sq_mem_subdesc {
931 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
932 uint64_t subdesc_type:4; /* W0 */
939 uint64_t rsvd1:15; /* W1 */
947 uint64_t subdesc_type:4; /* W0 */
950 uint64_t rsvd1:15; /* W1 */
954 struct sq_hdr_subdesc {
955 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
956 uint64_t subdesc_type:4;
958 uint64_t post_cqe:1; /* Post CQE on no error also */
959 uint64_t dont_send:1;
961 uint64_t subdesc_cnt:8;
964 uint64_t csum_inner_l4:2;
965 uint64_t csum_inner_l3:1;
967 uint64_t l4_offset:8;
968 uint64_t l3_offset:8;
970 uint64_t tot_len:20; /* W0 */
973 uint64_t inner_l4_offset:8;
974 uint64_t inner_l3_offset:8;
975 uint64_t tso_start:8;
977 uint64_t tso_max_paysize:14; /* W1 */
981 uint64_t l3_offset:8;
982 uint64_t l4_offset:8;
984 uint64_t csum_inner_l3:1;
985 uint64_t csum_inner_l4:2;
988 uint64_t subdesc_cnt:8;
990 uint64_t dont_send:1;
991 uint64_t post_cqe:1; /* Post CQE on no error also */
993 uint64_t subdesc_type:4; /* W0 */
995 uint64_t tso_max_paysize:14;
997 uint64_t tso_start:8;
998 uint64_t inner_l3_offset:8;
999 uint64_t inner_l4_offset:8;
1000 uint64_t rsvd2:24; /* W1 */
1004 /* Each sq entry is 128 bits wide */
1007 struct sq_hdr_subdesc hdr;
1008 struct sq_imm_subdesc imm;
1009 struct sq_gather_subdesc gather;
1010 struct sq_crc_subdesc crc;
1011 struct sq_mem_subdesc mem;
1014 NICVF_STATIC_ASSERT(sizeof(union sq_entry_t) == 16);
1016 /* Queue config register formats */
1017 struct rq_cfg { union { struct {
1018 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1019 uint64_t reserved_2_63:62;
1021 uint64_t reserved_0:1;
1023 uint64_t reserved_0:1;
1025 uint64_t reserved_2_63:62;
1031 struct cq_cfg { union { struct {
1032 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1033 uint64_t reserved_43_63:21;
1037 uint64_t reserved_35_39:5;
1039 uint64_t reserved_25_31:7;
1041 uint64_t reserved_0_15:16;
1043 uint64_t reserved_0_15:16;
1045 uint64_t reserved_25_31:7;
1047 uint64_t reserved_35_39:5;
1051 uint64_t reserved_43_63:21;
1057 struct sq_cfg { union { struct {
1058 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1059 uint64_t reserved_32_63:32;
1060 uint64_t cq_limit:8;
1062 uint64_t reserved_18_18:1;
1065 uint64_t reserved_11_15:5;
1067 uint64_t reserved_3_7:5;
1068 uint64_t tstmp_bgx_intf:3;
1070 uint64_t tstmp_bgx_intf:3;
1071 uint64_t reserved_3_7:5;
1073 uint64_t reserved_11_15:5;
1076 uint64_t reserved_18_18:1;
1078 uint64_t cq_limit:8;
1079 uint64_t reserved_32_63:32;
1085 struct rbdr_cfg { union { struct {
1086 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1087 uint64_t reserved_45_63:19;
1091 uint64_t reserved_36_41:6;
1093 uint64_t reserved_25_31:7;
1095 uint64_t reserved_12_15:4;
1099 uint64_t reserved_12_15:4;
1101 uint64_t reserved_25_31:7;
1103 uint64_t reserved_36_41:6;
1107 uint64_t reserved_45_63:19;
1113 struct pf_qs_cfg { union { struct {
1114 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1115 uint64_t reserved_32_63:32;
1117 uint64_t reserved_27_30:4;
1118 uint64_t sq_ins_ena:1;
1119 uint64_t sq_ins_pos:6;
1120 uint64_t lock_ena:1;
1121 uint64_t lock_viol_cqe_ena:1;
1122 uint64_t send_tstmp_ena:1;
1124 uint64_t reserved_7_15:9;
1128 uint64_t reserved_7_15:9;
1130 uint64_t send_tstmp_ena:1;
1131 uint64_t lock_viol_cqe_ena:1;
1132 uint64_t lock_ena:1;
1133 uint64_t sq_ins_pos:6;
1134 uint64_t sq_ins_ena:1;
1135 uint64_t reserved_27_30:4;
1137 uint64_t reserved_32_63:32;
1143 struct pf_rq_cfg { union { struct {
1144 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1145 uint64_t reserved1:1;
1146 uint64_t reserved0:34;
1147 uint64_t strip_pre_l2:1;
1151 uint64_t rbdr_cont_qs:7;
1152 uint64_t rbdr_cont_idx:1;
1153 uint64_t rbdr_strt_qs:7;
1154 uint64_t rbdr_strt_idx:1;
1156 uint64_t rbdr_strt_idx:1;
1157 uint64_t rbdr_strt_qs:7;
1158 uint64_t rbdr_cont_idx:1;
1159 uint64_t rbdr_cont_qs:7;
1163 uint64_t strip_pre_l2:1;
1164 uint64_t reserved0:34;
1165 uint64_t reserved1:1;
1171 struct pf_rq_drop_cfg { union { struct {
1172 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1173 uint64_t rbdr_red:1;
1175 uint64_t reserved3:14;
1176 uint64_t rbdr_pass:8;
1177 uint64_t rbdr_drop:8;
1178 uint64_t reserved2:8;
1181 uint64_t reserved1:8;
1183 uint64_t reserved1:8;
1186 uint64_t reserved2:8;
1187 uint64_t rbdr_drop:8;
1188 uint64_t rbdr_pass:8;
1189 uint64_t reserved3:14;
1191 uint64_t rbdr_red:1;
1197 #endif /* _THUNDERX_NICVF_HW_DEFS_H */