4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
44 #include <sys/timerfd.h>
46 #include <rte_alarm.h>
47 #include <rte_atomic.h>
48 #include <rte_branch_prediction.h>
49 #include <rte_byteorder.h>
50 #include <rte_common.h>
51 #include <rte_cycles.h>
52 #include <rte_debug.h>
55 #include <rte_ether.h>
56 #include <rte_ethdev.h>
57 #include <rte_interrupts.h>
59 #include <rte_memory.h>
60 #include <rte_memzone.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_tailq.h>
66 #include "base/nicvf_plat.h"
68 #include "nicvf_ethdev.h"
70 #include "nicvf_logs.h"
73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
74 struct rte_eth_link *link)
76 struct rte_eth_link *dst = &dev->data->dev_link;
77 struct rte_eth_link *src = link;
79 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
80 *(uint64_t *)src) == 0)
87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
89 link->link_status = nic->link_up;
90 link->link_duplex = ETH_LINK_AUTONEG;
91 if (nic->duplex == NICVF_HALF_DUPLEX)
92 link->link_duplex = ETH_LINK_HALF_DUPLEX;
93 else if (nic->duplex == NICVF_FULL_DUPLEX)
94 link->link_duplex = ETH_LINK_FULL_DUPLEX;
95 link->link_speed = nic->speed;
96 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
100 nicvf_interrupt(void *arg)
102 struct nicvf *nic = arg;
104 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
105 if (nic->eth_dev->data->dev_conf.intr_conf.lsc)
106 nicvf_set_eth_link_status(nic,
107 &nic->eth_dev->data->dev_link);
108 _rte_eth_dev_callback_process(nic->eth_dev,
109 RTE_ETH_EVENT_INTR_LSC);
112 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
113 nicvf_interrupt, nic);
117 nicvf_periodic_alarm_start(struct nicvf *nic)
119 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
120 nicvf_interrupt, nic);
124 nicvf_periodic_alarm_stop(struct nicvf *nic)
126 return rte_eal_alarm_cancel(nicvf_interrupt, nic);
130 * Return 0 means link status changed, -1 means not changed
133 nicvf_dev_link_update(struct rte_eth_dev *dev,
134 int wait_to_complete __rte_unused)
136 struct rte_eth_link link;
137 struct nicvf *nic = nicvf_pmd_priv(dev);
139 PMD_INIT_FUNC_TRACE();
141 memset(&link, 0, sizeof(link));
142 nicvf_set_eth_link_status(nic, &link);
143 return nicvf_atomic_write_link_status(dev, &link);
147 nicvf_dev_get_reg_length(struct rte_eth_dev *dev __rte_unused)
149 return nicvf_reg_get_count();
153 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
155 uint64_t *data = regs->data;
156 struct nicvf *nic = nicvf_pmd_priv(dev);
161 /* Support only full register dump */
162 if ((regs->length == 0) ||
163 (regs->length == (uint32_t)nicvf_reg_get_count())) {
164 regs->version = nic->vendor_id << 16 | nic->device_id;
165 nicvf_reg_dump(nic, data);
171 static inline uint64_t
172 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
174 uint64_t nic_rss = 0;
176 if (ethdev_rss & ETH_RSS_IPV4)
177 nic_rss |= RSS_IP_ENA;
179 if (ethdev_rss & ETH_RSS_IPV6)
180 nic_rss |= RSS_IP_ENA;
182 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
183 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
185 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
186 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
188 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
189 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
191 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
192 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
194 if (ethdev_rss & ETH_RSS_PORT)
195 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
197 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
198 if (ethdev_rss & ETH_RSS_VXLAN)
199 nic_rss |= RSS_TUN_VXLAN_ENA;
201 if (ethdev_rss & ETH_RSS_GENEVE)
202 nic_rss |= RSS_TUN_GENEVE_ENA;
204 if (ethdev_rss & ETH_RSS_NVGRE)
205 nic_rss |= RSS_TUN_NVGRE_ENA;
211 static inline uint64_t
212 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
214 uint64_t ethdev_rss = 0;
216 if (nic_rss & RSS_IP_ENA)
217 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
219 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
220 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
221 ETH_RSS_NONFRAG_IPV6_TCP);
223 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
224 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
225 ETH_RSS_NONFRAG_IPV6_UDP);
227 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
228 ethdev_rss |= ETH_RSS_PORT;
230 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
231 if (nic_rss & RSS_TUN_VXLAN_ENA)
232 ethdev_rss |= ETH_RSS_VXLAN;
234 if (nic_rss & RSS_TUN_GENEVE_ENA)
235 ethdev_rss |= ETH_RSS_GENEVE;
237 if (nic_rss & RSS_TUN_NVGRE_ENA)
238 ethdev_rss |= ETH_RSS_NVGRE;
244 nicvf_dev_reta_query(struct rte_eth_dev *dev,
245 struct rte_eth_rss_reta_entry64 *reta_conf,
248 struct nicvf *nic = nicvf_pmd_priv(dev);
249 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
252 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
253 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
254 "(%d) doesn't match the number hardware can supported "
255 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
259 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
263 /* Copy RETA table */
264 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
265 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
266 if ((reta_conf[i].mask >> j) & 0x01)
267 reta_conf[i].reta[j] = tbl[j];
274 nicvf_dev_reta_update(struct rte_eth_dev *dev,
275 struct rte_eth_rss_reta_entry64 *reta_conf,
278 struct nicvf *nic = nicvf_pmd_priv(dev);
279 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
282 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
283 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
284 "(%d) doesn't match the number hardware can supported "
285 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
289 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
293 /* Copy RETA table */
294 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
295 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
296 if ((reta_conf[i].mask >> j) & 0x01)
297 tbl[j] = reta_conf[i].reta[j];
300 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
304 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
305 struct rte_eth_rss_conf *rss_conf)
307 struct nicvf *nic = nicvf_pmd_priv(dev);
309 if (rss_conf->rss_key)
310 nicvf_rss_get_key(nic, rss_conf->rss_key);
312 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
313 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
318 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
319 struct rte_eth_rss_conf *rss_conf)
321 struct nicvf *nic = nicvf_pmd_priv(dev);
324 if (rss_conf->rss_key &&
325 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
326 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
327 rss_conf->rss_key_len);
331 if (rss_conf->rss_key)
332 nicvf_rss_set_key(nic, rss_conf->rss_key);
334 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
335 nicvf_rss_set_cfg(nic, nic_rss);
340 nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,
343 const struct rte_memzone *rz;
344 uint32_t ring_size = desc_cnt * sizeof(union cq_entry_t);
346 rz = rte_eth_dma_zone_reserve(nic->eth_dev, "cq_ring", qidx, ring_size,
347 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
349 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
353 memset(rz->addr, 0, ring_size);
355 rxq->phys = rz->phys_addr;
356 rxq->desc = rz->addr;
357 rxq->qlen_mask = desc_cnt - 1;
363 nicvf_qset_sq_alloc(struct nicvf *nic, struct nicvf_txq *sq, uint16_t qidx,
366 const struct rte_memzone *rz;
367 uint32_t ring_size = desc_cnt * sizeof(union sq_entry_t);
369 rz = rte_eth_dma_zone_reserve(nic->eth_dev, "sq", qidx, ring_size,
370 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
372 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
376 memset(rz->addr, 0, ring_size);
378 sq->phys = rz->phys_addr;
380 sq->qlen_mask = desc_cnt - 1;
386 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
391 while (head != txq->tail) {
392 if (txq->txbuffs[head]) {
393 rte_pktmbuf_free_seg(txq->txbuffs[head]);
394 txq->txbuffs[head] = NULL;
397 head = head & txq->qlen_mask;
402 nicvf_tx_queue_reset(struct nicvf_txq *txq)
404 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
406 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
407 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
414 nicvf_dev_tx_queue_release(void *sq)
416 struct nicvf_txq *txq;
418 PMD_INIT_FUNC_TRACE();
420 txq = (struct nicvf_txq *)sq;
422 if (txq->txbuffs != NULL) {
423 nicvf_tx_queue_release_mbufs(txq);
424 rte_free(txq->txbuffs);
432 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
433 uint16_t nb_desc, unsigned int socket_id,
434 const struct rte_eth_txconf *tx_conf)
436 uint16_t tx_free_thresh;
437 uint8_t is_single_pool;
438 struct nicvf_txq *txq;
439 struct nicvf *nic = nicvf_pmd_priv(dev);
441 PMD_INIT_FUNC_TRACE();
443 /* Socket id check */
444 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
445 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
446 socket_id, nic->node);
448 /* Tx deferred start is not supported */
449 if (tx_conf->tx_deferred_start) {
450 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
454 /* Roundup nb_desc to available qsize and validate max number of desc */
455 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
457 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
461 /* Validate tx_free_thresh */
462 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
463 tx_conf->tx_free_thresh :
464 NICVF_DEFAULT_TX_FREE_THRESH);
466 if (tx_free_thresh > (nb_desc) ||
467 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
469 "tx_free_thresh must be less than the number of TX "
470 "descriptors. (tx_free_thresh=%u port=%d "
471 "queue=%d)", (unsigned int)tx_free_thresh,
472 (int)dev->data->port_id, (int)qidx);
476 /* Free memory prior to re-allocation if needed. */
477 if (dev->data->tx_queues[qidx] != NULL) {
478 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
480 nicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);
481 dev->data->tx_queues[qidx] = NULL;
484 /* Allocating tx queue data structure */
485 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
486 RTE_CACHE_LINE_SIZE, nic->node);
488 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", qidx);
493 txq->queue_id = qidx;
494 txq->tx_free_thresh = tx_free_thresh;
495 txq->txq_flags = tx_conf->txq_flags;
496 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
497 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
498 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
499 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
501 /* Choose optimum free threshold value for multipool case */
502 if (!is_single_pool) {
503 txq->tx_free_thresh = (uint16_t)
504 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
505 NICVF_TX_FREE_MPOOL_THRESH :
506 tx_conf->tx_free_thresh);
509 /* Allocate software ring */
510 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
511 nb_desc * sizeof(struct rte_mbuf *),
512 RTE_CACHE_LINE_SIZE, nic->node);
514 if (txq->txbuffs == NULL) {
515 nicvf_dev_tx_queue_release(txq);
519 if (nicvf_qset_sq_alloc(nic, txq, qidx, nb_desc)) {
520 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
521 nicvf_dev_tx_queue_release(txq);
525 nicvf_tx_queue_reset(txq);
527 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
528 qidx, txq, nb_desc, txq->desc, txq->phys);
530 dev->data->tx_queues[qidx] = txq;
531 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
536 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
539 rxq->available_space = 0;
540 rxq->recv_buffers = 0;
544 nicvf_dev_rx_queue_release(void *rx_queue)
546 struct nicvf_rxq *rxq = rx_queue;
548 PMD_INIT_FUNC_TRACE();
555 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
556 uint16_t nb_desc, unsigned int socket_id,
557 const struct rte_eth_rxconf *rx_conf,
558 struct rte_mempool *mp)
560 uint16_t rx_free_thresh;
561 struct nicvf_rxq *rxq;
562 struct nicvf *nic = nicvf_pmd_priv(dev);
564 PMD_INIT_FUNC_TRACE();
566 /* Socket id check */
567 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
568 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
569 socket_id, nic->node);
571 /* Mempool memory should be contiguous */
572 if (mp->nb_mem_chunks != 1) {
573 PMD_INIT_LOG(ERR, "Non contiguous mempool, check huge page sz");
577 /* Rx deferred start is not supported */
578 if (rx_conf->rx_deferred_start) {
579 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
583 /* Roundup nb_desc to available qsize and validate max number of desc */
584 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
586 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
590 /* Check rx_free_thresh upper bound */
591 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
592 rx_conf->rx_free_thresh :
593 NICVF_DEFAULT_RX_FREE_THRESH);
594 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
595 rx_free_thresh >= nb_desc * .75) {
596 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
601 /* Free memory prior to re-allocation if needed */
602 if (dev->data->rx_queues[qidx] != NULL) {
603 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
605 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]);
606 dev->data->rx_queues[qidx] = NULL;
609 /* Allocate rxq memory */
610 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
611 RTE_CACHE_LINE_SIZE, nic->node);
613 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx);
619 rxq->queue_id = qidx;
620 rxq->port_id = dev->data->port_id;
621 rxq->rx_free_thresh = rx_free_thresh;
622 rxq->rx_drop_en = rx_conf->rx_drop_en;
623 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
624 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
625 rxq->precharge_cnt = 0;
626 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
628 /* Alloc completion queue */
629 if (nicvf_qset_cq_alloc(nic, rxq, rxq->queue_id, nb_desc)) {
630 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
631 nicvf_dev_rx_queue_release(rxq);
635 nicvf_rx_queue_reset(rxq);
637 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
638 qidx, rxq, mp->name, nb_desc,
639 rte_mempool_count(mp), rxq->phys);
641 dev->data->rx_queues[qidx] = rxq;
642 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
647 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
649 struct nicvf *nic = nicvf_pmd_priv(dev);
651 PMD_INIT_FUNC_TRACE();
653 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
654 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
655 dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
656 dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
657 dev_info->max_mac_addrs = 1;
658 dev_info->max_vfs = dev->pci_dev->max_vfs;
660 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
661 dev_info->tx_offload_capa =
662 DEV_TX_OFFLOAD_IPV4_CKSUM |
663 DEV_TX_OFFLOAD_UDP_CKSUM |
664 DEV_TX_OFFLOAD_TCP_CKSUM |
665 DEV_TX_OFFLOAD_TCP_TSO |
666 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
668 dev_info->reta_size = nic->rss_info.rss_size;
669 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
670 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
671 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
672 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
674 dev_info->default_rxconf = (struct rte_eth_rxconf) {
675 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
679 dev_info->default_txconf = (struct rte_eth_txconf) {
680 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
682 ETH_TXQ_FLAGS_NOMULTSEGS |
683 ETH_TXQ_FLAGS_NOREFCOUNT |
684 ETH_TXQ_FLAGS_NOMULTMEMP |
685 ETH_TXQ_FLAGS_NOVLANOFFL |
686 ETH_TXQ_FLAGS_NOXSUMSCTP,
691 nicvf_dev_configure(struct rte_eth_dev *dev)
693 struct rte_eth_conf *conf = &dev->data->dev_conf;
694 struct rte_eth_rxmode *rxmode = &conf->rxmode;
695 struct rte_eth_txmode *txmode = &conf->txmode;
696 struct nicvf *nic = nicvf_pmd_priv(dev);
698 PMD_INIT_FUNC_TRACE();
700 if (!rte_eal_has_hugepages()) {
701 PMD_INIT_LOG(INFO, "Huge page is not configured");
705 if (txmode->mq_mode) {
706 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
710 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
711 rxmode->mq_mode != ETH_MQ_RX_RSS) {
712 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
716 if (!rxmode->hw_strip_crc) {
717 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
718 rxmode->hw_strip_crc = 1;
721 if (rxmode->hw_ip_checksum) {
722 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
723 rxmode->hw_ip_checksum = 0;
726 if (rxmode->split_hdr_size) {
727 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
731 if (rxmode->hw_vlan_filter) {
732 PMD_INIT_LOG(INFO, "VLAN filter not supported");
736 if (rxmode->hw_vlan_extend) {
737 PMD_INIT_LOG(INFO, "VLAN extended not supported");
741 if (rxmode->enable_lro) {
742 PMD_INIT_LOG(INFO, "LRO not supported");
746 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
747 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
751 if (conf->dcb_capability_en) {
752 PMD_INIT_LOG(INFO, "DCB enable not supported");
756 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
757 PMD_INIT_LOG(INFO, "Flow director not supported");
761 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
762 dev->data->port_id, nicvf_hw_cap(nic));
767 /* Initialize and register driver with DPDK Application */
768 static const struct eth_dev_ops nicvf_eth_dev_ops = {
769 .dev_configure = nicvf_dev_configure,
770 .link_update = nicvf_dev_link_update,
771 .dev_infos_get = nicvf_dev_info_get,
772 .reta_update = nicvf_dev_reta_update,
773 .reta_query = nicvf_dev_reta_query,
774 .rss_hash_update = nicvf_dev_rss_hash_update,
775 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
776 .rx_queue_setup = nicvf_dev_rx_queue_setup,
777 .rx_queue_release = nicvf_dev_rx_queue_release,
778 .tx_queue_setup = nicvf_dev_tx_queue_setup,
779 .tx_queue_release = nicvf_dev_tx_queue_release,
780 .get_reg_length = nicvf_dev_get_reg_length,
781 .get_reg = nicvf_dev_get_regs,
785 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
788 struct rte_pci_device *pci_dev;
789 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
791 PMD_INIT_FUNC_TRACE();
793 eth_dev->dev_ops = &nicvf_eth_dev_ops;
795 pci_dev = eth_dev->pci_dev;
796 rte_eth_copy_pci_info(eth_dev, pci_dev);
798 nic->device_id = pci_dev->id.device_id;
799 nic->vendor_id = pci_dev->id.vendor_id;
800 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
801 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
802 nic->eth_dev = eth_dev;
804 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
805 pci_dev->id.vendor_id, pci_dev->id.device_id,
806 pci_dev->addr.domain, pci_dev->addr.bus,
807 pci_dev->addr.devid, pci_dev->addr.function);
809 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
810 if (!nic->reg_base) {
811 PMD_INIT_LOG(ERR, "Failed to map BAR0");
816 nicvf_disable_all_interrupts(nic);
818 ret = nicvf_periodic_alarm_start(nic);
820 PMD_INIT_LOG(ERR, "Failed to start period alarm");
824 ret = nicvf_mbox_check_pf_ready(nic);
826 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
830 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
831 nic->node, nic->vf_id,
832 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
833 nic->sqs_mode ? "true" : "false",
834 nic->loopback_supported ? "true" : "false"
839 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
840 /* Detach port by returning Positive error number */
845 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
846 if (eth_dev->data->mac_addrs == NULL) {
847 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
851 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
852 eth_random_addr(&nic->mac_addr[0]);
854 ether_addr_copy((struct ether_addr *)nic->mac_addr,
855 ð_dev->data->mac_addrs[0]);
857 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
859 PMD_INIT_LOG(ERR, "Failed to set mac addr");
863 ret = nicvf_base_init(nic);
865 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
869 ret = nicvf_mbox_get_rss_size(nic);
871 PMD_INIT_LOG(ERR, "Failed to get rss table size");
875 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
876 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
877 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
878 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
883 rte_free(eth_dev->data->mac_addrs);
885 nicvf_periodic_alarm_stop(nic);
890 static const struct rte_pci_id pci_id_nicvf_map[] = {
892 .class_id = RTE_CLASS_ANY_ID,
893 .vendor_id = PCI_VENDOR_ID_CAVIUM,
894 .device_id = PCI_DEVICE_ID_THUNDERX_PASS1_NICVF,
895 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
896 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF,
899 .class_id = RTE_CLASS_ANY_ID,
900 .vendor_id = PCI_VENDOR_ID_CAVIUM,
901 .device_id = PCI_DEVICE_ID_THUNDERX_PASS2_NICVF,
902 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
903 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF,
910 static struct eth_driver rte_nicvf_pmd = {
912 .name = "rte_nicvf_pmd",
913 .id_table = pci_id_nicvf_map,
914 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
916 .eth_dev_init = nicvf_eth_dev_init,
917 .dev_private_size = sizeof(struct nicvf),
921 rte_nicvf_pmd_init(const char *name __rte_unused, const char *para __rte_unused)
923 PMD_INIT_FUNC_TRACE();
924 PMD_INIT_LOG(INFO, "librte_pmd_thunderx nicvf version %s",
925 THUNDERX_NICVF_PMD_VERSION);
927 rte_eth_driver_register(&rte_nicvf_pmd);
931 static struct rte_driver rte_nicvf_driver = {
932 .name = "nicvf_driver",
934 .init = rte_nicvf_pmd_init,
937 PMD_REGISTER_DRIVER(rte_nicvf_driver);