1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016 Cavium, Inc
14 #include <netinet/in.h>
15 #include <sys/queue.h>
17 #include <rte_alarm.h>
18 #include <rte_branch_prediction.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_cycles.h>
22 #include <rte_debug.h>
25 #include <rte_ether.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_ethdev_pci.h>
28 #include <rte_interrupts.h>
30 #include <rte_memory.h>
31 #include <rte_memzone.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_bus_pci.h>
36 #include <rte_tailq.h>
37 #include <rte_devargs.h>
38 #include <rte_kvargs.h>
40 #include "base/nicvf_plat.h"
42 #include "nicvf_ethdev.h"
43 #include "nicvf_rxtx.h"
44 #include "nicvf_svf.h"
45 #include "nicvf_logs.h"
47 int nicvf_logtype_mbox;
48 int nicvf_logtype_init;
49 int nicvf_logtype_driver;
51 static void nicvf_dev_stop(struct rte_eth_dev *dev);
52 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
53 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
56 RTE_INIT(nicvf_init_log)
58 nicvf_logtype_mbox = rte_log_register("pmd.net.thunderx.mbox");
59 if (nicvf_logtype_mbox >= 0)
60 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE);
62 nicvf_logtype_init = rte_log_register("pmd.net.thunderx.init");
63 if (nicvf_logtype_init >= 0)
64 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE);
66 nicvf_logtype_driver = rte_log_register("pmd.net.thunderx.driver");
67 if (nicvf_logtype_driver >= 0)
68 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE);
72 nicvf_link_status_update(struct nicvf *nic,
73 struct rte_eth_link *link)
75 memset(link, 0, sizeof(*link));
77 link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
79 if (nic->duplex == NICVF_HALF_DUPLEX)
80 link->link_duplex = ETH_LINK_HALF_DUPLEX;
81 else if (nic->duplex == NICVF_FULL_DUPLEX)
82 link->link_duplex = ETH_LINK_FULL_DUPLEX;
83 link->link_speed = nic->speed;
84 link->link_autoneg = ETH_LINK_AUTONEG;
88 nicvf_interrupt(void *arg)
90 struct rte_eth_dev *dev = arg;
91 struct nicvf *nic = nicvf_pmd_priv(dev);
92 struct rte_eth_link link;
94 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
95 if (dev->data->dev_conf.intr_conf.lsc) {
96 nicvf_link_status_update(nic, &link);
97 rte_eth_linkstatus_set(dev, &link);
99 _rte_eth_dev_callback_process(dev,
100 RTE_ETH_EVENT_INTR_LSC,
105 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
106 nicvf_interrupt, dev);
110 nicvf_vf_interrupt(void *arg)
112 struct nicvf *nic = arg;
114 nicvf_reg_poll_interrupts(nic);
116 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
117 nicvf_vf_interrupt, nic);
121 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
123 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
127 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
129 return rte_eal_alarm_cancel(fn, arg);
133 * Return 0 means link status changed, -1 means not changed
136 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
138 #define CHECK_INTERVAL 100 /* 100ms */
139 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
140 struct rte_eth_link link;
141 struct nicvf *nic = nicvf_pmd_priv(dev);
144 PMD_INIT_FUNC_TRACE();
146 if (wait_to_complete) {
147 /* rte_eth_link_get() might need to wait up to 9 seconds */
148 for (i = 0; i < MAX_CHECK_TIME; i++) {
149 nicvf_link_status_update(nic, &link);
150 if (link.link_status == ETH_LINK_UP)
152 rte_delay_ms(CHECK_INTERVAL);
155 nicvf_link_status_update(nic, &link);
158 return rte_eth_linkstatus_set(dev, &link);
162 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
164 struct nicvf *nic = nicvf_pmd_priv(dev);
165 uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD;
167 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
169 PMD_INIT_FUNC_TRACE();
171 if (frame_size > NIC_HW_MAX_FRS)
174 if (frame_size < NIC_HW_MIN_FRS)
177 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
180 * Refuse mtu that requires the support of scattered packets
181 * when this feature has not been enabled before.
183 if (dev->data->dev_started && !dev->data->scattered_rx &&
184 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
187 /* check <seg size> * <max_seg> >= max_frame */
188 if (dev->data->scattered_rx &&
189 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
192 if (frame_size > ETHER_MAX_LEN)
193 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
195 rxmode->offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
197 if (nicvf_mbox_update_hw_max_frs(nic, mtu))
200 /* Update max_rx_pkt_len */
201 rxmode->max_rx_pkt_len = mtu + ETHER_HDR_LEN;
204 for (i = 0; i < nic->sqs_count; i++)
205 nic->snicvf[i]->mtu = mtu;
211 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
213 uint64_t *data = regs->data;
214 struct nicvf *nic = nicvf_pmd_priv(dev);
217 regs->length = nicvf_reg_get_count();
218 regs->width = THUNDERX_REG_BYTES;
222 /* Support only full register dump */
223 if ((regs->length == 0) ||
224 (regs->length == (uint32_t)nicvf_reg_get_count())) {
225 regs->version = nic->vendor_id << 16 | nic->device_id;
226 nicvf_reg_dump(nic, data);
233 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
236 struct nicvf_hw_rx_qstats rx_qstats;
237 struct nicvf_hw_tx_qstats tx_qstats;
238 struct nicvf_hw_stats port_stats;
239 struct nicvf *nic = nicvf_pmd_priv(dev);
240 uint16_t rx_start, rx_end;
241 uint16_t tx_start, tx_end;
244 /* RX queue indices for the first VF */
245 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
247 /* Reading per RX ring stats */
248 for (qidx = rx_start; qidx <= rx_end; qidx++) {
249 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
252 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
253 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
254 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
257 /* TX queue indices for the first VF */
258 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
260 /* Reading per TX ring stats */
261 for (qidx = tx_start; qidx <= tx_end; qidx++) {
262 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
265 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
266 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
267 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
270 for (i = 0; i < nic->sqs_count; i++) {
271 struct nicvf *snic = nic->snicvf[i];
276 /* RX queue indices for a secondary VF */
277 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
279 /* Reading per RX ring stats */
280 for (qidx = rx_start; qidx <= rx_end; qidx++) {
281 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
284 nicvf_hw_get_rx_qstats(snic, &rx_qstats,
285 qidx % MAX_RCV_QUEUES_PER_QS);
286 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
287 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
290 /* TX queue indices for a secondary VF */
291 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
292 /* Reading per TX ring stats */
293 for (qidx = tx_start; qidx <= tx_end; qidx++) {
294 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
297 nicvf_hw_get_tx_qstats(snic, &tx_qstats,
298 qidx % MAX_SND_QUEUES_PER_QS);
299 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
300 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
304 nicvf_hw_get_stats(nic, &port_stats);
305 stats->ibytes = port_stats.rx_bytes;
306 stats->ipackets = port_stats.rx_ucast_frames;
307 stats->ipackets += port_stats.rx_bcast_frames;
308 stats->ipackets += port_stats.rx_mcast_frames;
309 stats->ierrors = port_stats.rx_l2_errors;
310 stats->imissed = port_stats.rx_drop_red;
311 stats->imissed += port_stats.rx_drop_overrun;
312 stats->imissed += port_stats.rx_drop_bcast;
313 stats->imissed += port_stats.rx_drop_mcast;
314 stats->imissed += port_stats.rx_drop_l3_bcast;
315 stats->imissed += port_stats.rx_drop_l3_mcast;
317 stats->obytes = port_stats.tx_bytes_ok;
318 stats->opackets = port_stats.tx_ucast_frames_ok;
319 stats->opackets += port_stats.tx_bcast_frames_ok;
320 stats->opackets += port_stats.tx_mcast_frames_ok;
321 stats->oerrors = port_stats.tx_drops;
326 static const uint32_t *
327 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
330 static uint32_t ptypes[32];
331 struct nicvf *nic = nicvf_pmd_priv(dev);
332 static const uint32_t ptypes_common[] = {
334 RTE_PTYPE_L3_IPV4_EXT,
336 RTE_PTYPE_L3_IPV6_EXT,
341 static const uint32_t ptypes_tunnel[] = {
342 RTE_PTYPE_TUNNEL_GRE,
343 RTE_PTYPE_TUNNEL_GENEVE,
344 RTE_PTYPE_TUNNEL_VXLAN,
345 RTE_PTYPE_TUNNEL_NVGRE,
347 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
349 copied = sizeof(ptypes_common);
350 memcpy(ptypes, ptypes_common, copied);
351 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
352 memcpy((char *)ptypes + copied, ptypes_tunnel,
353 sizeof(ptypes_tunnel));
354 copied += sizeof(ptypes_tunnel);
357 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
358 if (dev->rx_pkt_burst == nicvf_recv_pkts ||
359 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
366 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
369 uint16_t rxqs = 0, txqs = 0;
370 struct nicvf *nic = nicvf_pmd_priv(dev);
371 uint16_t rx_start, rx_end;
372 uint16_t tx_start, tx_end;
374 /* Reset all primary nic counters */
375 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
376 for (i = rx_start; i <= rx_end; i++)
377 rxqs |= (0x3 << (i * 2));
379 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
380 for (i = tx_start; i <= tx_end; i++)
381 txqs |= (0x3 << (i * 2));
383 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
385 /* Reset secondary nic queue counters */
386 for (i = 0; i < nic->sqs_count; i++) {
387 struct nicvf *snic = nic->snicvf[i];
391 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
392 for (i = rx_start; i <= rx_end; i++)
393 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
395 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
396 for (i = tx_start; i <= tx_end; i++)
397 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
399 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
403 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
405 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
409 static inline uint64_t
410 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
412 uint64_t nic_rss = 0;
414 if (ethdev_rss & ETH_RSS_IPV4)
415 nic_rss |= RSS_IP_ENA;
417 if (ethdev_rss & ETH_RSS_IPV6)
418 nic_rss |= RSS_IP_ENA;
420 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
421 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
423 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
424 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
426 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
427 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
429 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
430 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
432 if (ethdev_rss & ETH_RSS_PORT)
433 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
435 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
436 if (ethdev_rss & ETH_RSS_VXLAN)
437 nic_rss |= RSS_TUN_VXLAN_ENA;
439 if (ethdev_rss & ETH_RSS_GENEVE)
440 nic_rss |= RSS_TUN_GENEVE_ENA;
442 if (ethdev_rss & ETH_RSS_NVGRE)
443 nic_rss |= RSS_TUN_NVGRE_ENA;
449 static inline uint64_t
450 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
452 uint64_t ethdev_rss = 0;
454 if (nic_rss & RSS_IP_ENA)
455 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
457 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
458 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
459 ETH_RSS_NONFRAG_IPV6_TCP);
461 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
462 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
463 ETH_RSS_NONFRAG_IPV6_UDP);
465 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
466 ethdev_rss |= ETH_RSS_PORT;
468 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
469 if (nic_rss & RSS_TUN_VXLAN_ENA)
470 ethdev_rss |= ETH_RSS_VXLAN;
472 if (nic_rss & RSS_TUN_GENEVE_ENA)
473 ethdev_rss |= ETH_RSS_GENEVE;
475 if (nic_rss & RSS_TUN_NVGRE_ENA)
476 ethdev_rss |= ETH_RSS_NVGRE;
482 nicvf_dev_reta_query(struct rte_eth_dev *dev,
483 struct rte_eth_rss_reta_entry64 *reta_conf,
486 struct nicvf *nic = nicvf_pmd_priv(dev);
487 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
490 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
491 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
492 "(%d) doesn't match the number hardware can supported "
493 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
497 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
501 /* Copy RETA table */
502 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
503 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
504 if ((reta_conf[i].mask >> j) & 0x01)
505 reta_conf[i].reta[j] = tbl[j];
512 nicvf_dev_reta_update(struct rte_eth_dev *dev,
513 struct rte_eth_rss_reta_entry64 *reta_conf,
516 struct nicvf *nic = nicvf_pmd_priv(dev);
517 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
520 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
521 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
522 "(%d) doesn't match the number hardware can supported "
523 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
527 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
531 /* Copy RETA table */
532 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
533 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
534 if ((reta_conf[i].mask >> j) & 0x01)
535 tbl[j] = reta_conf[i].reta[j];
538 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
542 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
543 struct rte_eth_rss_conf *rss_conf)
545 struct nicvf *nic = nicvf_pmd_priv(dev);
547 if (rss_conf->rss_key)
548 nicvf_rss_get_key(nic, rss_conf->rss_key);
550 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
551 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
556 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
557 struct rte_eth_rss_conf *rss_conf)
559 struct nicvf *nic = nicvf_pmd_priv(dev);
562 if (rss_conf->rss_key &&
563 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
564 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
565 rss_conf->rss_key_len);
569 if (rss_conf->rss_key)
570 nicvf_rss_set_key(nic, rss_conf->rss_key);
572 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
573 nicvf_rss_set_cfg(nic, nic_rss);
578 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
579 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
581 const struct rte_memzone *rz;
582 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
584 rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
585 nicvf_netdev_qidx(nic, qidx), ring_size,
586 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
588 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
592 memset(rz->addr, 0, ring_size);
594 rxq->phys = rz->iova;
595 rxq->desc = rz->addr;
596 rxq->qlen_mask = desc_cnt - 1;
602 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
603 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
605 const struct rte_memzone *rz;
606 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
608 rz = rte_eth_dma_zone_reserve(dev, "sq",
609 nicvf_netdev_qidx(nic, qidx), ring_size,
610 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
612 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
616 memset(rz->addr, 0, ring_size);
620 sq->qlen_mask = desc_cnt - 1;
626 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
627 uint32_t desc_cnt, uint32_t buffsz)
629 struct nicvf_rbdr *rbdr;
630 const struct rte_memzone *rz;
633 assert(nic->rbdr == NULL);
634 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
635 RTE_CACHE_LINE_SIZE, nic->node);
637 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
641 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
642 rz = rte_eth_dma_zone_reserve(dev, "rbdr",
643 nicvf_netdev_qidx(nic, 0), ring_size,
644 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
646 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
650 memset(rz->addr, 0, ring_size);
652 rbdr->phys = rz->iova;
655 rbdr->desc = rz->addr;
656 rbdr->buffsz = buffsz;
657 rbdr->qlen_mask = desc_cnt - 1;
659 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
661 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
668 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
669 nicvf_iova_addr_t phy)
673 struct nicvf_rxq *rxq;
674 uint16_t rx_start, rx_end;
676 /* Get queue ranges for this VF */
677 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
679 for (qidx = rx_start; qidx <= rx_end; qidx++) {
680 rxq = dev->data->rx_queues[qidx];
681 if (rxq->precharge_cnt) {
682 obj = (void *)nicvf_mbuff_phy2virt(phy,
684 rte_mempool_put(rxq->pool, obj);
685 rxq->precharge_cnt--;
692 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
694 uint32_t qlen_mask, head;
695 struct rbdr_entry_t *entry;
696 struct nicvf_rbdr *rbdr = nic->rbdr;
698 qlen_mask = rbdr->qlen_mask;
700 while (head != rbdr->tail) {
701 entry = rbdr->desc + head;
702 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
704 head = head & qlen_mask;
709 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
714 while (head != txq->tail) {
715 if (txq->txbuffs[head]) {
716 rte_pktmbuf_free_seg(txq->txbuffs[head]);
717 txq->txbuffs[head] = NULL;
720 head = head & txq->qlen_mask;
725 nicvf_tx_queue_reset(struct nicvf_txq *txq)
727 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
729 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
730 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
737 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
740 struct nicvf_txq *txq;
743 assert(qidx < MAX_SND_QUEUES_PER_QS);
745 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
746 RTE_ETH_QUEUE_STATE_STARTED)
749 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
751 ret = nicvf_qset_sq_config(nic, qidx, txq);
753 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
754 nic->vf_id, qidx, ret);
755 goto config_sq_error;
758 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
759 RTE_ETH_QUEUE_STATE_STARTED;
763 nicvf_qset_sq_reclaim(nic, qidx);
768 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
771 struct nicvf_txq *txq;
774 assert(qidx < MAX_SND_QUEUES_PER_QS);
776 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
777 RTE_ETH_QUEUE_STATE_STOPPED)
780 ret = nicvf_qset_sq_reclaim(nic, qidx);
782 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
783 nic->vf_id, qidx, ret);
785 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
786 nicvf_tx_queue_release_mbufs(txq);
787 nicvf_tx_queue_reset(txq);
789 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
790 RTE_ETH_QUEUE_STATE_STOPPED;
795 nicvf_configure_cpi(struct rte_eth_dev *dev)
797 struct nicvf *nic = nicvf_pmd_priv(dev);
801 /* Count started rx queues */
802 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
803 if (dev->data->rx_queue_state[qidx] ==
804 RTE_ETH_QUEUE_STATE_STARTED)
807 nic->cpi_alg = CPI_ALG_NONE;
808 ret = nicvf_mbox_config_cpi(nic, qcnt);
810 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
816 nicvf_configure_rss(struct rte_eth_dev *dev)
818 struct nicvf *nic = nicvf_pmd_priv(dev);
822 rsshf = nicvf_rss_ethdev_to_nic(nic,
823 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
824 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
825 dev->data->dev_conf.rxmode.mq_mode,
826 dev->data->nb_rx_queues,
827 dev->data->dev_conf.lpbk_mode, rsshf);
829 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
830 ret = nicvf_rss_term(nic);
831 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
832 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
834 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
840 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
842 struct nicvf *nic = nicvf_pmd_priv(dev);
843 unsigned int idx, qmap_size;
844 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
845 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
847 if (nic->cpi_alg != CPI_ALG_NONE)
850 /* Prepare queue map */
851 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
852 if (dev->data->rx_queue_state[idx] ==
853 RTE_ETH_QUEUE_STATE_STARTED)
854 qmap[qmap_size++] = idx;
857 /* Update default RSS RETA */
858 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
859 default_reta[idx] = qmap[idx % qmap_size];
861 return nicvf_rss_reta_update(nic, default_reta,
862 NIC_MAX_RSS_IDR_TBL_SIZE);
866 nicvf_dev_tx_queue_release(void *sq)
868 struct nicvf_txq *txq;
870 PMD_INIT_FUNC_TRACE();
872 txq = (struct nicvf_txq *)sq;
874 if (txq->txbuffs != NULL) {
875 nicvf_tx_queue_release_mbufs(txq);
876 rte_free(txq->txbuffs);
884 nicvf_set_tx_function(struct rte_eth_dev *dev)
886 struct nicvf_txq *txq = NULL;
888 bool multiseg = false;
890 for (i = 0; i < dev->data->nb_tx_queues; i++) {
891 txq = dev->data->tx_queues[i];
892 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
898 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
900 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
901 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
903 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
904 dev->tx_pkt_burst = nicvf_xmit_pkts;
910 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
911 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
913 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
917 nicvf_set_rx_function(struct rte_eth_dev *dev)
919 if (dev->data->scattered_rx) {
920 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
921 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
923 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
924 dev->rx_pkt_burst = nicvf_recv_pkts;
929 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
930 uint16_t nb_desc, unsigned int socket_id,
931 const struct rte_eth_txconf *tx_conf)
933 uint16_t tx_free_thresh;
935 struct nicvf_txq *txq;
936 struct nicvf *nic = nicvf_pmd_priv(dev);
939 PMD_INIT_FUNC_TRACE();
941 if (qidx >= MAX_SND_QUEUES_PER_QS)
942 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
944 qidx = qidx % MAX_SND_QUEUES_PER_QS;
946 /* Socket id check */
947 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
948 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
949 socket_id, nic->node);
951 /* Tx deferred start is not supported */
952 if (tx_conf->tx_deferred_start) {
953 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
957 /* Roundup nb_desc to available qsize and validate max number of desc */
958 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
960 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
964 /* Validate tx_free_thresh */
965 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
966 tx_conf->tx_free_thresh :
967 NICVF_DEFAULT_TX_FREE_THRESH);
969 if (tx_free_thresh > (nb_desc) ||
970 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
972 "tx_free_thresh must be less than the number of TX "
973 "descriptors. (tx_free_thresh=%u port=%d "
974 "queue=%d)", (unsigned int)tx_free_thresh,
975 (int)dev->data->port_id, (int)qidx);
979 /* Free memory prior to re-allocation if needed. */
980 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
981 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
982 nicvf_netdev_qidx(nic, qidx));
983 nicvf_dev_tx_queue_release(
984 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
985 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
988 /* Allocating tx queue data structure */
989 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
990 RTE_CACHE_LINE_SIZE, nic->node);
992 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
993 nicvf_netdev_qidx(nic, qidx));
998 txq->queue_id = qidx;
999 txq->tx_free_thresh = tx_free_thresh;
1000 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1001 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1002 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1003 txq->offloads = offloads;
1005 is_single_pool = !!(offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE);
1007 /* Choose optimum free threshold value for multipool case */
1008 if (!is_single_pool) {
1009 txq->tx_free_thresh = (uint16_t)
1010 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1011 NICVF_TX_FREE_MPOOL_THRESH :
1012 tx_conf->tx_free_thresh);
1013 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1015 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1018 /* Allocate software ring */
1019 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1020 nb_desc * sizeof(struct rte_mbuf *),
1021 RTE_CACHE_LINE_SIZE, nic->node);
1023 if (txq->txbuffs == NULL) {
1024 nicvf_dev_tx_queue_release(txq);
1028 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1029 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1030 nicvf_dev_tx_queue_release(txq);
1034 nicvf_tx_queue_reset(txq);
1036 PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p"
1037 " phys=0x%" PRIx64 " offloads=0x%" PRIx64,
1038 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1039 txq->phys, txq->offloads);
1041 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1042 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1043 RTE_ETH_QUEUE_STATE_STOPPED;
1048 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1051 uint32_t nb_pkts, released_pkts = 0;
1052 uint32_t refill_cnt = 0;
1053 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1055 if (dev->rx_pkt_burst == NULL)
1058 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1059 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1060 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1061 NICVF_MAX_RX_FREE_THRESH);
1062 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt);
1064 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1070 refill_cnt += nicvf_dev_rbdr_refill(dev,
1071 nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1073 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d",
1074 released_pkts, refill_cnt);
1078 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1081 rxq->available_space = 0;
1082 rxq->recv_buffers = 0;
1086 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1089 struct nicvf_rxq *rxq;
1092 assert(qidx < MAX_RCV_QUEUES_PER_QS);
1094 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1095 RTE_ETH_QUEUE_STATE_STARTED)
1098 /* Update rbdr pointer to all rxq */
1099 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1100 rxq->shared_rbdr = nic->rbdr;
1102 ret = nicvf_qset_rq_config(nic, qidx, rxq);
1104 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1105 nic->vf_id, qidx, ret);
1106 goto config_rq_error;
1108 ret = nicvf_qset_cq_config(nic, qidx, rxq);
1110 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1111 nic->vf_id, qidx, ret);
1112 goto config_cq_error;
1115 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1116 RTE_ETH_QUEUE_STATE_STARTED;
1120 nicvf_qset_cq_reclaim(nic, qidx);
1122 nicvf_qset_rq_reclaim(nic, qidx);
1127 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1130 struct nicvf_rxq *rxq;
1131 int ret, other_error;
1133 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1134 RTE_ETH_QUEUE_STATE_STOPPED)
1137 ret = nicvf_qset_rq_reclaim(nic, qidx);
1139 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1140 nic->vf_id, qidx, ret);
1143 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1144 nicvf_rx_queue_release_mbufs(dev, rxq);
1145 nicvf_rx_queue_reset(rxq);
1147 ret = nicvf_qset_cq_reclaim(nic, qidx);
1149 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1150 nic->vf_id, qidx, ret);
1153 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1154 RTE_ETH_QUEUE_STATE_STOPPED;
1159 nicvf_dev_rx_queue_release(void *rx_queue)
1161 PMD_INIT_FUNC_TRACE();
1167 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1169 struct nicvf *nic = nicvf_pmd_priv(dev);
1172 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1173 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1175 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1177 ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1181 ret = nicvf_configure_cpi(dev);
1185 return nicvf_configure_rss_reta(dev);
1189 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1192 struct nicvf *nic = nicvf_pmd_priv(dev);
1194 if (qidx >= MAX_SND_QUEUES_PER_QS)
1195 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1197 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1199 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1200 ret |= nicvf_configure_cpi(dev);
1201 ret |= nicvf_configure_rss_reta(dev);
1206 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1208 struct nicvf *nic = nicvf_pmd_priv(dev);
1210 if (qidx >= MAX_SND_QUEUES_PER_QS)
1211 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1213 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1215 return nicvf_vf_start_tx_queue(dev, nic, qidx);
1219 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1221 struct nicvf *nic = nicvf_pmd_priv(dev);
1223 if (qidx >= MAX_SND_QUEUES_PER_QS)
1224 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1226 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1228 return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1232 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1235 struct rte_mbuf mb_def;
1236 struct nicvf *nic = rxq->nic;
1238 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1239 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1240 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1241 offsetof(struct rte_mbuf, data_off) != 2);
1242 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1243 offsetof(struct rte_mbuf, data_off) != 4);
1244 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1245 offsetof(struct rte_mbuf, data_off) != 6);
1247 mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes);
1248 mb_def.port = rxq->port_id;
1249 rte_mbuf_refcnt_set(&mb_def, 1);
1251 /* Prevent compiler reordering: rearm_data covers previous fields */
1252 rte_compiler_barrier();
1253 p = (uintptr_t)&mb_def.rearm_data;
1254 rxq->mbuf_initializer.value = *(uint64_t *)p;
1258 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1259 uint16_t nb_desc, unsigned int socket_id,
1260 const struct rte_eth_rxconf *rx_conf,
1261 struct rte_mempool *mp)
1263 uint16_t rx_free_thresh;
1264 struct nicvf_rxq *rxq;
1265 struct nicvf *nic = nicvf_pmd_priv(dev);
1268 struct rte_pktmbuf_pool_private *mbp_priv;
1270 PMD_INIT_FUNC_TRACE();
1272 /* First skip check */
1273 mbp_priv = rte_mempool_get_priv(mp);
1274 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1275 if (buffsz < (uint32_t)(nic->skip_bytes)) {
1276 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size");
1280 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1281 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1283 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1285 /* Socket id check */
1286 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1287 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1288 socket_id, nic->node);
1290 /* Mempool memory must be contiguous, so must be one memory segment*/
1291 if (mp->nb_mem_chunks != 1) {
1292 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1296 /* Mempool memory must be physically contiguous */
1297 if (mp->flags & MEMPOOL_F_NO_IOVA_CONTIG) {
1298 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1302 /* Rx deferred start is not supported */
1303 if (rx_conf->rx_deferred_start) {
1304 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1308 /* Roundup nb_desc to available qsize and validate max number of desc */
1309 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1311 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1316 /* Check rx_free_thresh upper bound */
1317 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1318 rx_conf->rx_free_thresh :
1319 NICVF_DEFAULT_RX_FREE_THRESH);
1320 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1321 rx_free_thresh >= nb_desc * .75) {
1322 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1327 /* Free memory prior to re-allocation if needed */
1328 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1329 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1330 nicvf_netdev_qidx(nic, qidx));
1331 nicvf_dev_rx_queue_release(
1332 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1333 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1336 /* Allocate rxq memory */
1337 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1338 RTE_CACHE_LINE_SIZE, nic->node);
1340 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1341 nicvf_netdev_qidx(nic, qidx));
1347 rxq->queue_id = qidx;
1348 rxq->port_id = dev->data->port_id;
1349 rxq->rx_free_thresh = rx_free_thresh;
1350 rxq->rx_drop_en = rx_conf->rx_drop_en;
1351 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1352 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1353 rxq->precharge_cnt = 0;
1355 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1356 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1358 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1360 nicvf_rxq_mbuf_setup(rxq);
1362 /* Alloc completion queue */
1363 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1364 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1365 nicvf_dev_rx_queue_release(rxq);
1369 nicvf_rx_queue_reset(rxq);
1371 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1372 PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)"
1373 " phy=0x%" PRIx64 " offloads=0x%" PRIx64,
1374 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1375 rte_mempool_avail_count(mp), rxq->phys, offloads);
1377 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1378 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1379 RTE_ETH_QUEUE_STATE_STOPPED;
1384 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1386 struct nicvf *nic = nicvf_pmd_priv(dev);
1387 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1389 PMD_INIT_FUNC_TRACE();
1391 /* Autonegotiation may be disabled */
1392 dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
1393 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M |
1394 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
1395 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF)
1396 dev_info->speed_capa |= ETH_LINK_SPEED_40G;
1398 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1399 dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + ETHER_HDR_LEN;
1400 dev_info->max_rx_queues =
1401 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1402 dev_info->max_tx_queues =
1403 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1404 dev_info->max_mac_addrs = 1;
1405 dev_info->max_vfs = pci_dev->max_vfs;
1407 dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1408 dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1409 dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1410 dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1412 dev_info->reta_size = nic->rss_info.rss_size;
1413 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1414 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1415 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1416 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1418 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1419 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1421 .offloads = DEV_RX_OFFLOAD_CRC_STRIP,
1424 dev_info->default_txconf = (struct rte_eth_txconf) {
1425 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1426 .offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE |
1427 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1428 DEV_TX_OFFLOAD_UDP_CKSUM |
1429 DEV_TX_OFFLOAD_TCP_CKSUM,
1433 static nicvf_iova_addr_t
1434 rbdr_rte_mempool_get(void *dev, void *opaque)
1438 struct nicvf_rxq *rxq;
1439 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1440 struct nicvf *nic = (struct nicvf *)opaque;
1441 uint16_t rx_start, rx_end;
1443 /* Get queue ranges for this VF */
1444 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1446 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1447 rxq = eth_dev->data->rx_queues[qidx];
1448 /* Maintain equal buffer count across all pools */
1449 if (rxq->precharge_cnt >= rxq->qlen_mask)
1451 rxq->precharge_cnt++;
1452 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1454 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1460 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1463 uint16_t qidx, data_off;
1464 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1465 uint64_t mbuf_phys_off = 0;
1466 struct nicvf_rxq *rxq;
1467 struct rte_mbuf *mbuf;
1468 uint16_t rx_start, rx_end;
1469 uint16_t tx_start, tx_end;
1472 PMD_INIT_FUNC_TRACE();
1474 /* Userspace process exited without proper shutdown in last run */
1475 if (nicvf_qset_rbdr_active(nic, 0))
1476 nicvf_vf_stop(dev, nic, false);
1478 /* Get queue ranges for this VF */
1479 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1482 * Thunderx nicvf PMD can support more than one pool per port only when
1483 * 1) Data payload size is same across all the pools in given port
1485 * 2) All mbuffs in the pools are from the same hugepage
1487 * 3) Mbuff metadata size is same across all the pools in given port
1489 * This is to support existing application that uses multiple pool/port.
1490 * But, the purpose of using multipool for QoS will not be addressed.
1494 /* Validate mempool attributes */
1495 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1496 rxq = dev->data->rx_queues[qidx];
1497 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1498 mbuf = rte_pktmbuf_alloc(rxq->pool);
1500 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1502 nic->vf_id, qidx, rxq->pool->name);
1505 data_off = nicvf_mbuff_meta_length(mbuf);
1506 data_off += RTE_PKTMBUF_HEADROOM;
1507 rte_pktmbuf_free(mbuf);
1509 if (data_off % RTE_CACHE_LINE_SIZE) {
1510 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1511 rxq->pool->name, data_off,
1512 data_off % RTE_CACHE_LINE_SIZE);
1515 rxq->mbuf_phys_off -= data_off;
1516 rxq->mbuf_phys_off -= nic->skip_bytes;
1518 if (mbuf_phys_off == 0)
1519 mbuf_phys_off = rxq->mbuf_phys_off;
1520 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1521 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1522 PRIx64, rxq->pool->name, nic->vf_id,
1528 /* Check the level of buffers in the pool */
1530 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1531 rxq = dev->data->rx_queues[qidx];
1532 /* Count total numbers of rxq descs */
1533 total_rxq_desc += rxq->qlen_mask + 1;
1534 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1535 exp_buffs *= dev->data->nb_rx_queues;
1536 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1537 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1539 rte_mempool_avail_count(rxq->pool),
1545 /* Check RBDR desc overflow */
1546 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1548 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1549 "VF%d", nic->vf_id);
1554 ret = nicvf_qset_config(nic);
1556 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1561 /* Allocate RBDR and RBDR ring desc */
1562 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1563 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1565 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1566 "VF%d", nic->vf_id);
1570 /* Enable and configure RBDR registers */
1571 ret = nicvf_qset_rbdr_config(nic, 0);
1573 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1575 goto qset_rbdr_free;
1578 /* Fill rte_mempool buffers in RBDR pool and precharge it */
1579 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1582 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1584 goto qset_rbdr_reclaim;
1587 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1588 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1590 /* Configure VLAN Strip */
1591 vlan_strip = !!(dev->data->dev_conf.rxmode.offloads &
1592 DEV_RX_OFFLOAD_VLAN_STRIP);
1593 nicvf_vlan_hw_strip(nic, vlan_strip);
1595 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1596 * to the 64bit memory address.
1597 * The alignment creates a hole in mbuf(between the end of headroom and
1598 * packet data start). The new revision of the HW provides an option to
1599 * disable the L3 alignment feature and make mbuf layout looks
1600 * more like other NICs. For better application compatibility, disabling
1601 * l3 alignment feature on the hardware revisions it supports
1603 nicvf_apad_config(nic, false);
1605 /* Get queue ranges for this VF */
1606 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1608 /* Configure TX queues */
1609 for (qidx = tx_start; qidx <= tx_end; qidx++) {
1610 ret = nicvf_vf_start_tx_queue(dev, nic,
1611 qidx % MAX_SND_QUEUES_PER_QS);
1613 goto start_txq_error;
1616 /* Configure RX queues */
1617 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1618 ret = nicvf_vf_start_rx_queue(dev, nic,
1619 qidx % MAX_RCV_QUEUES_PER_QS);
1621 goto start_rxq_error;
1624 if (!nic->sqs_mode) {
1625 /* Configure CPI algorithm */
1626 ret = nicvf_configure_cpi(dev);
1628 goto start_txq_error;
1630 ret = nicvf_mbox_get_rss_size(nic);
1632 PMD_INIT_LOG(ERR, "Failed to get rss table size");
1633 goto qset_rss_error;
1637 ret = nicvf_configure_rss(dev);
1639 goto qset_rss_error;
1642 /* Done; Let PF make the BGX's RX and TX switches to ON position */
1643 nicvf_mbox_cfg_done(nic);
1647 nicvf_rss_term(nic);
1649 for (qidx = rx_start; qidx <= rx_end; qidx++)
1650 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1652 for (qidx = tx_start; qidx <= tx_end; qidx++)
1653 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1655 nicvf_qset_rbdr_reclaim(nic, 0);
1656 nicvf_rbdr_release_mbufs(dev, nic);
1659 rte_free(nic->rbdr);
1663 nicvf_qset_reclaim(nic);
1668 nicvf_dev_start(struct rte_eth_dev *dev)
1673 struct nicvf *nic = nicvf_pmd_priv(dev);
1674 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1676 uint32_t buffsz = 0, rbdrsz = 0;
1677 struct rte_pktmbuf_pool_private *mbp_priv;
1678 struct nicvf_rxq *rxq;
1680 PMD_INIT_FUNC_TRACE();
1682 /* This function must be called for a primary device */
1683 assert_primary(nic);
1685 /* Validate RBDR buff size */
1686 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1687 rxq = dev->data->rx_queues[qidx];
1688 mbp_priv = rte_mempool_get_priv(rxq->pool);
1689 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1691 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1696 if (rbdrsz != buffsz) {
1697 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1698 qidx, rbdrsz, buffsz);
1703 /* Configure loopback */
1704 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1706 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1710 /* Reset all statistics counters attached to this port */
1711 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1713 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1717 /* Setup scatter mode if needed by jumbo */
1718 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1719 2 * VLAN_TAG_SIZE > buffsz)
1720 dev->data->scattered_rx = 1;
1721 if ((rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) != 0)
1722 dev->data->scattered_rx = 1;
1724 /* Setup MTU based on max_rx_pkt_len or default */
1725 mtu = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ?
1726 dev->data->dev_conf.rxmode.max_rx_pkt_len
1727 - ETHER_HDR_LEN : ETHER_MTU;
1729 if (nicvf_dev_set_mtu(dev, mtu)) {
1730 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1734 ret = nicvf_vf_start(dev, nic, rbdrsz);
1738 for (i = 0; i < nic->sqs_count; i++) {
1739 assert(nic->snicvf[i]);
1741 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1746 /* Configure callbacks based on scatter mode */
1747 nicvf_set_tx_function(dev);
1748 nicvf_set_rx_function(dev);
1754 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1758 struct nicvf *nic = nicvf_pmd_priv(dev);
1760 PMD_INIT_FUNC_TRACE();
1762 /* Teardown secondary vf first */
1763 for (i = 0; i < nic->sqs_count; i++) {
1764 if (!nic->snicvf[i])
1767 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1770 /* Stop the primary VF now */
1771 nicvf_vf_stop(dev, nic, cleanup);
1773 /* Disable loopback */
1774 ret = nicvf_loopback_config(nic, 0);
1776 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1778 /* Reclaim CPI configuration */
1779 ret = nicvf_mbox_config_cpi(nic, 0);
1781 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1785 nicvf_dev_stop(struct rte_eth_dev *dev)
1787 PMD_INIT_FUNC_TRACE();
1789 nicvf_dev_stop_cleanup(dev, false);
1793 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1797 uint16_t tx_start, tx_end;
1798 uint16_t rx_start, rx_end;
1800 PMD_INIT_FUNC_TRACE();
1803 /* Let PF make the BGX's RX and TX switches to OFF position */
1804 nicvf_mbox_shutdown(nic);
1807 /* Disable VLAN Strip */
1808 nicvf_vlan_hw_strip(nic, 0);
1810 /* Get queue ranges for this VF */
1811 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1813 for (qidx = tx_start; qidx <= tx_end; qidx++)
1814 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1816 /* Get queue ranges for this VF */
1817 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1820 for (qidx = rx_start; qidx <= rx_end; qidx++)
1821 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1824 ret = nicvf_qset_rbdr_reclaim(nic, 0);
1826 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1828 /* Move all charged buffers in RBDR back to pool */
1829 if (nic->rbdr != NULL)
1830 nicvf_rbdr_release_mbufs(dev, nic);
1833 ret = nicvf_qset_reclaim(nic);
1835 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1837 /* Disable all interrupts */
1838 nicvf_disable_all_interrupts(nic);
1840 /* Free RBDR SW structure */
1842 rte_free(nic->rbdr);
1848 nicvf_dev_close(struct rte_eth_dev *dev)
1851 struct nicvf *nic = nicvf_pmd_priv(dev);
1853 PMD_INIT_FUNC_TRACE();
1855 nicvf_dev_stop_cleanup(dev, true);
1856 nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1858 for (i = 0; i < nic->sqs_count; i++) {
1859 if (!nic->snicvf[i])
1862 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1867 nicvf_request_sqs(struct nicvf *nic)
1871 assert_primary(nic);
1872 assert(nic->sqs_count > 0);
1873 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1875 /* Set no of Rx/Tx queues in each of the SQsets */
1876 for (i = 0; i < nic->sqs_count; i++) {
1877 if (nicvf_svf_empty())
1878 rte_panic("Cannot assign sufficient number of "
1879 "secondary queues to primary VF%" PRIu8 "\n",
1882 nic->snicvf[i] = nicvf_svf_pop();
1883 nic->snicvf[i]->sqs_id = i;
1886 return nicvf_mbox_request_sqs(nic);
1890 nicvf_dev_configure(struct rte_eth_dev *dev)
1892 struct rte_eth_dev_data *data = dev->data;
1893 struct rte_eth_conf *conf = &data->dev_conf;
1894 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1895 struct rte_eth_txmode *txmode = &conf->txmode;
1896 struct nicvf *nic = nicvf_pmd_priv(dev);
1899 PMD_INIT_FUNC_TRACE();
1901 if (!rte_eal_has_hugepages()) {
1902 PMD_INIT_LOG(INFO, "Huge page is not configured");
1906 /* KEEP_CRC offload flag is not supported by PMD
1907 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
1909 if (rte_eth_dev_must_keep_crc(rxmode->offloads)) {
1910 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1911 rxmode->offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
1914 if (txmode->mq_mode) {
1915 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1919 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1920 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1921 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1925 if (rxmode->split_hdr_size) {
1926 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1930 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1931 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1935 if (conf->dcb_capability_en) {
1936 PMD_INIT_LOG(INFO, "DCB enable not supported");
1940 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1941 PMD_INIT_LOG(INFO, "Flow director not supported");
1945 assert_primary(nic);
1946 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1947 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1948 if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1949 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1950 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1955 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1957 if (nic->sqs_count > 0) {
1958 if (nicvf_request_sqs(nic)) {
1959 rte_panic("Cannot assign sufficient number of "
1960 "secondary queues to PORT%d VF%" PRIu8 "\n",
1961 dev->data->port_id, nic->vf_id);
1965 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1966 dev->data->port_id, nicvf_hw_cap(nic));
1971 /* Initialize and register driver with DPDK Application */
1972 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1973 .dev_configure = nicvf_dev_configure,
1974 .dev_start = nicvf_dev_start,
1975 .dev_stop = nicvf_dev_stop,
1976 .link_update = nicvf_dev_link_update,
1977 .dev_close = nicvf_dev_close,
1978 .stats_get = nicvf_dev_stats_get,
1979 .stats_reset = nicvf_dev_stats_reset,
1980 .promiscuous_enable = nicvf_dev_promisc_enable,
1981 .dev_infos_get = nicvf_dev_info_get,
1982 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1983 .mtu_set = nicvf_dev_set_mtu,
1984 .reta_update = nicvf_dev_reta_update,
1985 .reta_query = nicvf_dev_reta_query,
1986 .rss_hash_update = nicvf_dev_rss_hash_update,
1987 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
1988 .rx_queue_start = nicvf_dev_rx_queue_start,
1989 .rx_queue_stop = nicvf_dev_rx_queue_stop,
1990 .tx_queue_start = nicvf_dev_tx_queue_start,
1991 .tx_queue_stop = nicvf_dev_tx_queue_stop,
1992 .rx_queue_setup = nicvf_dev_rx_queue_setup,
1993 .rx_queue_release = nicvf_dev_rx_queue_release,
1994 .rx_queue_count = nicvf_dev_rx_queue_count,
1995 .tx_queue_setup = nicvf_dev_tx_queue_setup,
1996 .tx_queue_release = nicvf_dev_tx_queue_release,
1997 .get_reg = nicvf_dev_get_regs,
2001 nicvf_set_first_skip(struct rte_eth_dev *dev)
2003 int bytes_to_skip = 0;
2006 struct rte_kvargs *kvlist;
2007 static const char *const skip[] = {
2010 struct nicvf *nic = nicvf_pmd_priv(dev);
2012 if (!dev->device->devargs) {
2013 nicvf_first_skip_config(nic, 0);
2017 kvlist = rte_kvargs_parse(dev->device->devargs->args, skip);
2021 if (kvlist->count == 0)
2024 for (i = 0; i != kvlist->count; ++i) {
2025 const struct rte_kvargs_pair *pair = &kvlist->pairs[i];
2027 if (!strcmp(pair->key, SKIP_DATA_BYTES))
2028 bytes_to_skip = atoi(pair->value);
2031 /*128 bytes amounts to one cache line*/
2032 if (bytes_to_skip >= 0 && bytes_to_skip < 128) {
2033 if (!(bytes_to_skip % 8)) {
2034 nicvf_first_skip_config(nic, (bytes_to_skip / 8));
2035 nic->skip_bytes = bytes_to_skip;
2038 PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8");
2043 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128");
2048 nicvf_first_skip_config(nic, 0);
2050 rte_kvargs_free(kvlist);
2054 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2057 struct rte_pci_device *pci_dev;
2058 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2060 PMD_INIT_FUNC_TRACE();
2062 eth_dev->dev_ops = &nicvf_eth_dev_ops;
2064 /* For secondary processes, the primary has done all the work */
2065 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2067 /* Setup callbacks for secondary process */
2068 nicvf_set_tx_function(eth_dev);
2069 nicvf_set_rx_function(eth_dev);
2072 /* If nic == NULL than it is secondary function
2073 * so ethdev need to be released by caller */
2078 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2079 rte_eth_copy_pci_info(eth_dev, pci_dev);
2081 nic->device_id = pci_dev->id.device_id;
2082 nic->vendor_id = pci_dev->id.vendor_id;
2083 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2084 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2086 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2087 pci_dev->id.vendor_id, pci_dev->id.device_id,
2088 pci_dev->addr.domain, pci_dev->addr.bus,
2089 pci_dev->addr.devid, pci_dev->addr.function);
2091 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2092 if (!nic->reg_base) {
2093 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2098 nicvf_disable_all_interrupts(nic);
2100 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2102 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2106 ret = nicvf_mbox_check_pf_ready(nic);
2108 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2112 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2113 nic->node, nic->vf_id,
2114 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2115 nic->sqs_mode ? "true" : "false",
2116 nic->loopback_supported ? "true" : "false"
2120 ret = nicvf_base_init(nic);
2122 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2126 if (nic->sqs_mode) {
2127 /* Push nic to stack of secondary vfs */
2128 nicvf_svf_push(nic);
2130 /* Steal nic pointer from the device for further reuse */
2131 eth_dev->data->dev_private = NULL;
2133 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2134 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2136 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2140 /* Detach port by returning positive error number */
2144 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2145 if (eth_dev->data->mac_addrs == NULL) {
2146 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2150 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2151 eth_random_addr(&nic->mac_addr[0]);
2153 ether_addr_copy((struct ether_addr *)nic->mac_addr,
2154 ð_dev->data->mac_addrs[0]);
2156 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2158 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2162 ret = nicvf_set_first_skip(eth_dev);
2164 PMD_INIT_LOG(ERR, "Failed to configure first skip");
2167 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2168 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2169 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2170 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2175 rte_free(eth_dev->data->mac_addrs);
2177 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2182 static const struct rte_pci_id pci_id_nicvf_map[] = {
2184 .class_id = RTE_CLASS_ANY_ID,
2185 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2186 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2187 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2188 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2191 .class_id = RTE_CLASS_ANY_ID,
2192 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2193 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2194 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2195 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2198 .class_id = RTE_CLASS_ANY_ID,
2199 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2200 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2201 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2202 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2205 .class_id = RTE_CLASS_ANY_ID,
2206 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2207 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2208 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2209 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2216 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2217 struct rte_pci_device *pci_dev)
2219 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2220 nicvf_eth_dev_init);
2223 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2225 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2228 static struct rte_pci_driver rte_nicvf_pmd = {
2229 .id_table = pci_id_nicvf_map,
2230 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2231 RTE_PCI_DRV_INTR_LSC,
2232 .probe = nicvf_eth_pci_probe,
2233 .remove = nicvf_eth_pci_remove,
2236 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2237 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2238 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");
2239 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>");