4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
44 #include <sys/timerfd.h>
46 #include <rte_alarm.h>
47 #include <rte_atomic.h>
48 #include <rte_branch_prediction.h>
49 #include <rte_byteorder.h>
50 #include <rte_common.h>
51 #include <rte_cycles.h>
52 #include <rte_debug.h>
55 #include <rte_ether.h>
56 #include <rte_ethdev.h>
57 #include <rte_interrupts.h>
59 #include <rte_memory.h>
60 #include <rte_memzone.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_tailq.h>
66 #include "base/nicvf_plat.h"
68 #include "nicvf_ethdev.h"
69 #include "nicvf_rxtx.h"
70 #include "nicvf_svf.h"
71 #include "nicvf_logs.h"
73 static void nicvf_dev_stop(struct rte_eth_dev *dev);
74 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
75 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
79 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
80 struct rte_eth_link *link)
82 struct rte_eth_link *dst = &dev->data->dev_link;
83 struct rte_eth_link *src = link;
85 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
86 *(uint64_t *)src) == 0)
93 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
95 link->link_status = nic->link_up;
96 link->link_duplex = ETH_LINK_AUTONEG;
97 if (nic->duplex == NICVF_HALF_DUPLEX)
98 link->link_duplex = ETH_LINK_HALF_DUPLEX;
99 else if (nic->duplex == NICVF_FULL_DUPLEX)
100 link->link_duplex = ETH_LINK_FULL_DUPLEX;
101 link->link_speed = nic->speed;
102 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
106 nicvf_interrupt(void *arg)
108 struct rte_eth_dev *dev = arg;
109 struct nicvf *nic = nicvf_pmd_priv(dev);
111 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
112 if (dev->data->dev_conf.intr_conf.lsc)
113 nicvf_set_eth_link_status(nic, &dev->data->dev_link);
114 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
117 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
118 nicvf_interrupt, dev);
121 static void __rte_unused
122 nicvf_vf_interrupt(void *arg)
124 struct nicvf *nic = arg;
126 nicvf_reg_poll_interrupts(nic);
128 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
129 nicvf_vf_interrupt, nic);
133 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
135 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
139 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
141 return rte_eal_alarm_cancel(fn, arg);
145 * Return 0 means link status changed, -1 means not changed
148 nicvf_dev_link_update(struct rte_eth_dev *dev,
149 int wait_to_complete __rte_unused)
151 struct rte_eth_link link;
152 struct nicvf *nic = nicvf_pmd_priv(dev);
154 PMD_INIT_FUNC_TRACE();
156 memset(&link, 0, sizeof(link));
157 nicvf_set_eth_link_status(nic, &link);
158 return nicvf_atomic_write_link_status(dev, &link);
162 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
164 struct nicvf *nic = nicvf_pmd_priv(dev);
165 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
167 PMD_INIT_FUNC_TRACE();
169 if (frame_size > NIC_HW_MAX_FRS)
172 if (frame_size < NIC_HW_MIN_FRS)
175 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
178 * Refuse mtu that requires the support of scattered packets
179 * when this feature has not been enabled before.
181 if (!dev->data->scattered_rx &&
182 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
185 /* check <seg size> * <max_seg> >= max_frame */
186 if (dev->data->scattered_rx &&
187 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
190 if (frame_size > ETHER_MAX_LEN)
191 dev->data->dev_conf.rxmode.jumbo_frame = 1;
193 dev->data->dev_conf.rxmode.jumbo_frame = 0;
195 if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
198 /* Update max frame size */
199 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
205 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
207 uint64_t *data = regs->data;
208 struct nicvf *nic = nicvf_pmd_priv(dev);
211 regs->length = nicvf_reg_get_count();
212 regs->width = THUNDERX_REG_BYTES;
216 /* Support only full register dump */
217 if ((regs->length == 0) ||
218 (regs->length == (uint32_t)nicvf_reg_get_count())) {
219 regs->version = nic->vendor_id << 16 | nic->device_id;
220 nicvf_reg_dump(nic, data);
227 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
230 struct nicvf_hw_rx_qstats rx_qstats;
231 struct nicvf_hw_tx_qstats tx_qstats;
232 struct nicvf_hw_stats port_stats;
233 struct nicvf *nic = nicvf_pmd_priv(dev);
235 /* Reading per RX ring stats */
236 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
237 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
240 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
241 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
242 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
245 /* Reading per TX ring stats */
246 for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++) {
247 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
250 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
251 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
252 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
255 nicvf_hw_get_stats(nic, &port_stats);
256 stats->ibytes = port_stats.rx_bytes;
257 stats->ipackets = port_stats.rx_ucast_frames;
258 stats->ipackets += port_stats.rx_bcast_frames;
259 stats->ipackets += port_stats.rx_mcast_frames;
260 stats->ierrors = port_stats.rx_l2_errors;
261 stats->imissed = port_stats.rx_drop_red;
262 stats->imissed += port_stats.rx_drop_overrun;
263 stats->imissed += port_stats.rx_drop_bcast;
264 stats->imissed += port_stats.rx_drop_mcast;
265 stats->imissed += port_stats.rx_drop_l3_bcast;
266 stats->imissed += port_stats.rx_drop_l3_mcast;
268 stats->obytes = port_stats.tx_bytes_ok;
269 stats->opackets = port_stats.tx_ucast_frames_ok;
270 stats->opackets += port_stats.tx_bcast_frames_ok;
271 stats->opackets += port_stats.tx_mcast_frames_ok;
272 stats->oerrors = port_stats.tx_drops;
275 static const uint32_t *
276 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
279 static uint32_t ptypes[32];
280 struct nicvf *nic = nicvf_pmd_priv(dev);
281 static const uint32_t ptypes_common[] = {
283 RTE_PTYPE_L3_IPV4_EXT,
285 RTE_PTYPE_L3_IPV6_EXT,
290 static const uint32_t ptypes_tunnel[] = {
291 RTE_PTYPE_TUNNEL_GRE,
292 RTE_PTYPE_TUNNEL_GENEVE,
293 RTE_PTYPE_TUNNEL_VXLAN,
294 RTE_PTYPE_TUNNEL_NVGRE,
296 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
298 copied = sizeof(ptypes_common);
299 memcpy(ptypes, ptypes_common, copied);
300 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
301 memcpy((char *)ptypes + copied, ptypes_tunnel,
302 sizeof(ptypes_tunnel));
303 copied += sizeof(ptypes_tunnel);
306 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
307 if (dev->rx_pkt_burst == nicvf_recv_pkts ||
308 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
315 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
318 uint16_t rxqs = 0, txqs = 0;
319 struct nicvf *nic = nicvf_pmd_priv(dev);
321 for (i = 0; i < dev->data->nb_rx_queues; i++)
322 rxqs |= (0x3 << (i * 2));
323 for (i = 0; i < dev->data->nb_tx_queues; i++)
324 txqs |= (0x3 << (i * 2));
326 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
329 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
331 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
335 static inline uint64_t
336 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
338 uint64_t nic_rss = 0;
340 if (ethdev_rss & ETH_RSS_IPV4)
341 nic_rss |= RSS_IP_ENA;
343 if (ethdev_rss & ETH_RSS_IPV6)
344 nic_rss |= RSS_IP_ENA;
346 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
347 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
349 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
350 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
352 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
353 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
355 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
356 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
358 if (ethdev_rss & ETH_RSS_PORT)
359 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
361 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
362 if (ethdev_rss & ETH_RSS_VXLAN)
363 nic_rss |= RSS_TUN_VXLAN_ENA;
365 if (ethdev_rss & ETH_RSS_GENEVE)
366 nic_rss |= RSS_TUN_GENEVE_ENA;
368 if (ethdev_rss & ETH_RSS_NVGRE)
369 nic_rss |= RSS_TUN_NVGRE_ENA;
375 static inline uint64_t
376 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
378 uint64_t ethdev_rss = 0;
380 if (nic_rss & RSS_IP_ENA)
381 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
383 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
384 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
385 ETH_RSS_NONFRAG_IPV6_TCP);
387 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
388 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
389 ETH_RSS_NONFRAG_IPV6_UDP);
391 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
392 ethdev_rss |= ETH_RSS_PORT;
394 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
395 if (nic_rss & RSS_TUN_VXLAN_ENA)
396 ethdev_rss |= ETH_RSS_VXLAN;
398 if (nic_rss & RSS_TUN_GENEVE_ENA)
399 ethdev_rss |= ETH_RSS_GENEVE;
401 if (nic_rss & RSS_TUN_NVGRE_ENA)
402 ethdev_rss |= ETH_RSS_NVGRE;
408 nicvf_dev_reta_query(struct rte_eth_dev *dev,
409 struct rte_eth_rss_reta_entry64 *reta_conf,
412 struct nicvf *nic = nicvf_pmd_priv(dev);
413 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
416 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
417 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
418 "(%d) doesn't match the number hardware can supported "
419 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
423 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
427 /* Copy RETA table */
428 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
429 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
430 if ((reta_conf[i].mask >> j) & 0x01)
431 reta_conf[i].reta[j] = tbl[j];
438 nicvf_dev_reta_update(struct rte_eth_dev *dev,
439 struct rte_eth_rss_reta_entry64 *reta_conf,
442 struct nicvf *nic = nicvf_pmd_priv(dev);
443 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
446 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
447 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
448 "(%d) doesn't match the number hardware can supported "
449 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
453 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
457 /* Copy RETA table */
458 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
459 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
460 if ((reta_conf[i].mask >> j) & 0x01)
461 tbl[j] = reta_conf[i].reta[j];
464 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
468 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
469 struct rte_eth_rss_conf *rss_conf)
471 struct nicvf *nic = nicvf_pmd_priv(dev);
473 if (rss_conf->rss_key)
474 nicvf_rss_get_key(nic, rss_conf->rss_key);
476 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
477 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
482 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
483 struct rte_eth_rss_conf *rss_conf)
485 struct nicvf *nic = nicvf_pmd_priv(dev);
488 if (rss_conf->rss_key &&
489 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
490 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
491 rss_conf->rss_key_len);
495 if (rss_conf->rss_key)
496 nicvf_rss_set_key(nic, rss_conf->rss_key);
498 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
499 nicvf_rss_set_cfg(nic, nic_rss);
504 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
505 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
507 const struct rte_memzone *rz;
508 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
510 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", qidx, ring_size,
511 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
513 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
517 memset(rz->addr, 0, ring_size);
519 rxq->phys = rz->phys_addr;
520 rxq->desc = rz->addr;
521 rxq->qlen_mask = desc_cnt - 1;
527 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
528 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
530 const struct rte_memzone *rz;
531 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
533 rz = rte_eth_dma_zone_reserve(dev, "sq", qidx, ring_size,
534 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
536 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
540 memset(rz->addr, 0, ring_size);
542 sq->phys = rz->phys_addr;
544 sq->qlen_mask = desc_cnt - 1;
550 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
551 uint32_t desc_cnt, uint32_t buffsz)
553 struct nicvf_rbdr *rbdr;
554 const struct rte_memzone *rz;
557 assert(nic->rbdr == NULL);
558 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
559 RTE_CACHE_LINE_SIZE, nic->node);
561 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
565 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
566 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 0, ring_size,
567 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
569 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
573 memset(rz->addr, 0, ring_size);
575 rbdr->phys = rz->phys_addr;
578 rbdr->desc = rz->addr;
579 rbdr->buffsz = buffsz;
580 rbdr->qlen_mask = desc_cnt - 1;
582 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
584 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
591 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic __rte_unused,
592 nicvf_phys_addr_t phy)
596 struct nicvf_rxq *rxq;
598 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
599 rxq = dev->data->rx_queues[qidx];
600 if (rxq->precharge_cnt) {
601 obj = (void *)nicvf_mbuff_phy2virt(phy,
603 rte_mempool_put(rxq->pool, obj);
604 rxq->precharge_cnt--;
611 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
613 uint32_t qlen_mask, head;
614 struct rbdr_entry_t *entry;
615 struct nicvf_rbdr *rbdr = nic->rbdr;
617 qlen_mask = rbdr->qlen_mask;
619 while (head != rbdr->tail) {
620 entry = rbdr->desc + head;
621 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
623 head = head & qlen_mask;
628 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
633 while (head != txq->tail) {
634 if (txq->txbuffs[head]) {
635 rte_pktmbuf_free_seg(txq->txbuffs[head]);
636 txq->txbuffs[head] = NULL;
639 head = head & txq->qlen_mask;
644 nicvf_tx_queue_reset(struct nicvf_txq *txq)
646 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
648 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
649 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
656 nicvf_start_tx_queue(struct rte_eth_dev *dev, uint16_t qidx)
658 struct nicvf_txq *txq;
661 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
664 txq = dev->data->tx_queues[qidx];
666 ret = nicvf_qset_sq_config(nicvf_pmd_priv(dev), qidx, txq);
668 PMD_INIT_LOG(ERR, "Failed to configure sq %d %d", qidx, ret);
669 goto config_sq_error;
672 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
676 nicvf_qset_sq_reclaim(nicvf_pmd_priv(dev), qidx);
681 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
684 struct nicvf_txq *txq;
687 assert(qidx < MAX_SND_QUEUES_PER_QS);
689 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
690 RTE_ETH_QUEUE_STATE_STOPPED)
693 ret = nicvf_qset_sq_reclaim(nic, qidx);
695 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
696 nic->vf_id, qidx, ret);
698 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
699 nicvf_tx_queue_release_mbufs(txq);
700 nicvf_tx_queue_reset(txq);
702 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
703 RTE_ETH_QUEUE_STATE_STOPPED;
708 nicvf_configure_cpi(struct rte_eth_dev *dev)
710 struct nicvf *nic = nicvf_pmd_priv(dev);
714 /* Count started rx queues */
715 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
716 if (dev->data->rx_queue_state[qidx] ==
717 RTE_ETH_QUEUE_STATE_STARTED)
720 nic->cpi_alg = CPI_ALG_NONE;
721 ret = nicvf_mbox_config_cpi(nic, qcnt);
723 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
729 nicvf_configure_rss(struct rte_eth_dev *dev)
731 struct nicvf *nic = nicvf_pmd_priv(dev);
735 rsshf = nicvf_rss_ethdev_to_nic(nic,
736 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
737 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
738 dev->data->dev_conf.rxmode.mq_mode,
739 dev->data->nb_rx_queues,
740 dev->data->dev_conf.lpbk_mode, rsshf);
742 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
743 ret = nicvf_rss_term(nic);
744 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
745 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
747 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
753 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
755 struct nicvf *nic = nicvf_pmd_priv(dev);
756 unsigned int idx, qmap_size;
757 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
758 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
760 if (nic->cpi_alg != CPI_ALG_NONE)
763 /* Prepare queue map */
764 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
765 if (dev->data->rx_queue_state[idx] ==
766 RTE_ETH_QUEUE_STATE_STARTED)
767 qmap[qmap_size++] = idx;
770 /* Update default RSS RETA */
771 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
772 default_reta[idx] = qmap[idx % qmap_size];
774 return nicvf_rss_reta_update(nic, default_reta,
775 NIC_MAX_RSS_IDR_TBL_SIZE);
779 nicvf_dev_tx_queue_release(void *sq)
781 struct nicvf_txq *txq;
783 PMD_INIT_FUNC_TRACE();
785 txq = (struct nicvf_txq *)sq;
787 if (txq->txbuffs != NULL) {
788 nicvf_tx_queue_release_mbufs(txq);
789 rte_free(txq->txbuffs);
797 nicvf_set_tx_function(struct rte_eth_dev *dev)
799 struct nicvf_txq *txq;
801 bool multiseg = false;
803 for (i = 0; i < dev->data->nb_tx_queues; i++) {
804 txq = dev->data->tx_queues[i];
805 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
811 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
813 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
814 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
816 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
817 dev->tx_pkt_burst = nicvf_xmit_pkts;
820 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
821 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
823 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
827 nicvf_set_rx_function(struct rte_eth_dev *dev)
829 if (dev->data->scattered_rx) {
830 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
831 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
833 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
834 dev->rx_pkt_burst = nicvf_recv_pkts;
839 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
840 uint16_t nb_desc, unsigned int socket_id,
841 const struct rte_eth_txconf *tx_conf)
843 uint16_t tx_free_thresh;
844 uint8_t is_single_pool;
845 struct nicvf_txq *txq;
846 struct nicvf *nic = nicvf_pmd_priv(dev);
848 PMD_INIT_FUNC_TRACE();
850 /* Socket id check */
851 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
852 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
853 socket_id, nic->node);
855 /* Tx deferred start is not supported */
856 if (tx_conf->tx_deferred_start) {
857 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
861 /* Roundup nb_desc to available qsize and validate max number of desc */
862 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
864 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
868 /* Validate tx_free_thresh */
869 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
870 tx_conf->tx_free_thresh :
871 NICVF_DEFAULT_TX_FREE_THRESH);
873 if (tx_free_thresh > (nb_desc) ||
874 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
876 "tx_free_thresh must be less than the number of TX "
877 "descriptors. (tx_free_thresh=%u port=%d "
878 "queue=%d)", (unsigned int)tx_free_thresh,
879 (int)dev->data->port_id, (int)qidx);
883 /* Free memory prior to re-allocation if needed. */
884 if (dev->data->tx_queues[qidx] != NULL) {
885 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
887 nicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);
888 dev->data->tx_queues[qidx] = NULL;
891 /* Allocating tx queue data structure */
892 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
893 RTE_CACHE_LINE_SIZE, nic->node);
895 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", qidx);
900 txq->queue_id = qidx;
901 txq->tx_free_thresh = tx_free_thresh;
902 txq->txq_flags = tx_conf->txq_flags;
903 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
904 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
905 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
906 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
908 /* Choose optimum free threshold value for multipool case */
909 if (!is_single_pool) {
910 txq->tx_free_thresh = (uint16_t)
911 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
912 NICVF_TX_FREE_MPOOL_THRESH :
913 tx_conf->tx_free_thresh);
914 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
916 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
919 /* Allocate software ring */
920 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
921 nb_desc * sizeof(struct rte_mbuf *),
922 RTE_CACHE_LINE_SIZE, nic->node);
924 if (txq->txbuffs == NULL) {
925 nicvf_dev_tx_queue_release(txq);
929 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
930 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
931 nicvf_dev_tx_queue_release(txq);
935 nicvf_tx_queue_reset(txq);
937 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
938 qidx, txq, nb_desc, txq->desc, txq->phys);
940 dev->data->tx_queues[qidx] = txq;
941 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
946 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
949 uint32_t nb_pkts, released_pkts = 0;
950 uint32_t refill_cnt = 0;
951 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
953 if (dev->rx_pkt_burst == NULL)
956 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev, rxq->queue_id))) {
957 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
958 NICVF_MAX_RX_FREE_THRESH);
959 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt);
961 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
966 refill_cnt += nicvf_dev_rbdr_refill(dev, rxq->queue_id);
967 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d",
968 released_pkts, refill_cnt);
972 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
975 rxq->available_space = 0;
976 rxq->recv_buffers = 0;
980 nicvf_start_rx_queue(struct rte_eth_dev *dev, uint16_t qidx)
982 struct nicvf *nic = nicvf_pmd_priv(dev);
983 struct nicvf_rxq *rxq;
986 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
989 /* Update rbdr pointer to all rxq */
990 rxq = dev->data->rx_queues[qidx];
991 rxq->shared_rbdr = nic->rbdr;
993 ret = nicvf_qset_rq_config(nic, qidx, rxq);
995 PMD_INIT_LOG(ERR, "Failed to configure rq %d %d", qidx, ret);
996 goto config_rq_error;
998 ret = nicvf_qset_cq_config(nic, qidx, rxq);
1000 PMD_INIT_LOG(ERR, "Failed to configure cq %d %d", qidx, ret);
1001 goto config_cq_error;
1004 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1008 nicvf_qset_cq_reclaim(nic, qidx);
1010 nicvf_qset_rq_reclaim(nic, qidx);
1015 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1018 struct nicvf_rxq *rxq;
1019 int ret, other_error;
1021 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1022 RTE_ETH_QUEUE_STATE_STOPPED)
1025 ret = nicvf_qset_rq_reclaim(nic, qidx);
1027 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1028 nic->vf_id, qidx, ret);
1031 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1032 nicvf_rx_queue_release_mbufs(dev, rxq);
1033 nicvf_rx_queue_reset(rxq);
1035 ret = nicvf_qset_cq_reclaim(nic, qidx);
1037 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1038 nic->vf_id, qidx, ret);
1041 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1042 RTE_ETH_QUEUE_STATE_STOPPED;
1047 nicvf_dev_rx_queue_release(void *rx_queue)
1049 PMD_INIT_FUNC_TRACE();
1055 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1059 ret = nicvf_start_rx_queue(dev, qidx);
1063 ret = nicvf_configure_cpi(dev);
1067 return nicvf_configure_rss_reta(dev);
1071 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1074 struct nicvf *nic = nicvf_pmd_priv(dev);
1076 if (qidx >= MAX_SND_QUEUES_PER_QS)
1077 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1079 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1081 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1082 ret |= nicvf_configure_cpi(dev);
1083 ret |= nicvf_configure_rss_reta(dev);
1088 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1090 return nicvf_start_tx_queue(dev, qidx);
1094 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1096 struct nicvf *nic = nicvf_pmd_priv(dev);
1098 if (qidx >= MAX_SND_QUEUES_PER_QS)
1099 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1101 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1103 return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1108 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1109 uint16_t nb_desc, unsigned int socket_id,
1110 const struct rte_eth_rxconf *rx_conf,
1111 struct rte_mempool *mp)
1113 uint16_t rx_free_thresh;
1114 struct nicvf_rxq *rxq;
1115 struct nicvf *nic = nicvf_pmd_priv(dev);
1117 PMD_INIT_FUNC_TRACE();
1119 /* Socket id check */
1120 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1121 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1122 socket_id, nic->node);
1124 /* Mempool memory must be contiguous, so must be one memory segment*/
1125 if (mp->nb_mem_chunks != 1) {
1126 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1130 /* Mempool memory must be physically contiguous */
1131 if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1132 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1136 /* Rx deferred start is not supported */
1137 if (rx_conf->rx_deferred_start) {
1138 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1142 /* Roundup nb_desc to available qsize and validate max number of desc */
1143 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1145 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1149 /* Check rx_free_thresh upper bound */
1150 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1151 rx_conf->rx_free_thresh :
1152 NICVF_DEFAULT_RX_FREE_THRESH);
1153 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1154 rx_free_thresh >= nb_desc * .75) {
1155 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1160 /* Free memory prior to re-allocation if needed */
1161 if (dev->data->rx_queues[qidx] != NULL) {
1162 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1164 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]);
1165 dev->data->rx_queues[qidx] = NULL;
1168 /* Allocate rxq memory */
1169 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1170 RTE_CACHE_LINE_SIZE, nic->node);
1172 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx);
1178 rxq->queue_id = qidx;
1179 rxq->port_id = dev->data->port_id;
1180 rxq->rx_free_thresh = rx_free_thresh;
1181 rxq->rx_drop_en = rx_conf->rx_drop_en;
1182 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1183 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1184 rxq->precharge_cnt = 0;
1186 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1187 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1189 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1192 /* Alloc completion queue */
1193 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1194 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1195 nicvf_dev_rx_queue_release(rxq);
1199 nicvf_rx_queue_reset(rxq);
1201 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1202 qidx, rxq, mp->name, nb_desc,
1203 rte_mempool_avail_count(mp), rxq->phys);
1205 dev->data->rx_queues[qidx] = rxq;
1206 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1211 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1213 struct nicvf *nic = nicvf_pmd_priv(dev);
1215 PMD_INIT_FUNC_TRACE();
1217 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1218 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1219 dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
1220 dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
1221 dev_info->max_mac_addrs = 1;
1222 dev_info->max_vfs = dev->pci_dev->max_vfs;
1224 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1225 dev_info->tx_offload_capa =
1226 DEV_TX_OFFLOAD_IPV4_CKSUM |
1227 DEV_TX_OFFLOAD_UDP_CKSUM |
1228 DEV_TX_OFFLOAD_TCP_CKSUM |
1229 DEV_TX_OFFLOAD_TCP_TSO |
1230 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1232 dev_info->reta_size = nic->rss_info.rss_size;
1233 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1234 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1235 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1236 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1238 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1239 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1243 dev_info->default_txconf = (struct rte_eth_txconf) {
1244 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1246 ETH_TXQ_FLAGS_NOMULTSEGS |
1247 ETH_TXQ_FLAGS_NOREFCOUNT |
1248 ETH_TXQ_FLAGS_NOMULTMEMP |
1249 ETH_TXQ_FLAGS_NOVLANOFFL |
1250 ETH_TXQ_FLAGS_NOXSUMSCTP,
1254 static nicvf_phys_addr_t
1255 rbdr_rte_mempool_get(void *dev, void *opaque)
1259 struct nicvf_rxq *rxq;
1260 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1261 struct nicvf *nic __rte_unused = (struct nicvf *)opaque;
1263 for (qidx = 0; qidx < eth_dev->data->nb_rx_queues; qidx++) {
1264 rxq = eth_dev->data->rx_queues[qidx];
1265 /* Maintain equal buffer count across all pools */
1266 if (rxq->precharge_cnt >= rxq->qlen_mask)
1268 rxq->precharge_cnt++;
1269 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1271 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1277 nicvf_dev_start(struct rte_eth_dev *dev)
1281 uint32_t buffsz = 0, rbdrsz = 0;
1282 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1283 uint64_t mbuf_phys_off = 0;
1284 struct nicvf_rxq *rxq;
1285 struct rte_pktmbuf_pool_private *mbp_priv;
1286 struct rte_mbuf *mbuf;
1287 struct nicvf *nic = nicvf_pmd_priv(dev);
1288 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1291 PMD_INIT_FUNC_TRACE();
1293 /* Userspace process exited without proper shutdown in last run */
1294 if (nicvf_qset_rbdr_active(nic, 0))
1295 nicvf_dev_stop(dev);
1298 * Thunderx nicvf PMD can support more than one pool per port only when
1299 * 1) Data payload size is same across all the pools in given port
1301 * 2) All mbuffs in the pools are from the same hugepage
1303 * 3) Mbuff metadata size is same across all the pools in given port
1305 * This is to support existing application that uses multiple pool/port.
1306 * But, the purpose of using multipool for QoS will not be addressed.
1310 /* Validate RBDR buff size */
1311 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1312 rxq = dev->data->rx_queues[qidx];
1313 mbp_priv = rte_mempool_get_priv(rxq->pool);
1314 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1316 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1321 if (rbdrsz != buffsz) {
1322 PMD_INIT_LOG(ERR, "buffsz not same, qid=%d (%d/%d)",
1323 qidx, rbdrsz, buffsz);
1328 /* Validate mempool attributes */
1329 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1330 rxq = dev->data->rx_queues[qidx];
1331 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1332 mbuf = rte_pktmbuf_alloc(rxq->pool);
1334 PMD_INIT_LOG(ERR, "Failed allocate mbuf qid=%d pool=%s",
1335 qidx, rxq->pool->name);
1338 rxq->mbuf_phys_off -= nicvf_mbuff_meta_length(mbuf);
1339 rxq->mbuf_phys_off -= RTE_PKTMBUF_HEADROOM;
1340 rte_pktmbuf_free(mbuf);
1342 if (mbuf_phys_off == 0)
1343 mbuf_phys_off = rxq->mbuf_phys_off;
1344 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1345 PMD_INIT_LOG(ERR, "pool params not same,%s %" PRIx64,
1346 rxq->pool->name, mbuf_phys_off);
1351 /* Check the level of buffers in the pool */
1353 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1354 rxq = dev->data->rx_queues[qidx];
1355 /* Count total numbers of rxq descs */
1356 total_rxq_desc += rxq->qlen_mask + 1;
1357 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1358 exp_buffs *= dev->data->nb_rx_queues;
1359 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1360 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1362 rte_mempool_avail_count(rxq->pool),
1368 /* Check RBDR desc overflow */
1369 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1371 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc");
1376 ret = nicvf_qset_config(nic);
1378 PMD_INIT_LOG(ERR, "Failed to enable qset %d", ret);
1382 /* Allocate RBDR and RBDR ring desc */
1383 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1384 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1386 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc");
1390 /* Enable and configure RBDR registers */
1391 ret = nicvf_qset_rbdr_config(nic, 0);
1393 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d", ret);
1394 goto qset_rbdr_free;
1397 /* Fill rte_mempool buffers in RBDR pool and precharge it */
1398 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1401 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d", ret);
1402 goto qset_rbdr_reclaim;
1405 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR",
1406 nic->rbdr->tail, nb_rbdr_desc);
1408 /* Configure RX queues */
1409 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1410 ret = nicvf_start_rx_queue(dev, qidx);
1412 goto start_rxq_error;
1415 /* Configure VLAN Strip */
1416 nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1418 /* Configure TX queues */
1419 for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++) {
1420 ret = nicvf_start_tx_queue(dev, qidx);
1422 goto start_txq_error;
1425 /* Configure CPI algorithm */
1426 ret = nicvf_configure_cpi(dev);
1428 goto start_txq_error;
1431 ret = nicvf_configure_rss(dev);
1433 goto qset_rss_error;
1435 /* Configure loopback */
1436 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1438 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1439 goto qset_rss_error;
1442 /* Reset all statistics counters attached to this port */
1443 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1445 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1446 goto qset_rss_error;
1449 /* Setup scatter mode if needed by jumbo */
1450 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1451 2 * VLAN_TAG_SIZE > buffsz)
1452 dev->data->scattered_rx = 1;
1453 if (rx_conf->enable_scatter)
1454 dev->data->scattered_rx = 1;
1456 /* Setup MTU based on max_rx_pkt_len or default */
1457 mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1458 dev->data->dev_conf.rxmode.max_rx_pkt_len
1459 - ETHER_HDR_LEN - ETHER_CRC_LEN
1462 if (nicvf_dev_set_mtu(dev, mtu)) {
1463 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1467 /* Configure callbacks based on scatter mode */
1468 nicvf_set_tx_function(dev);
1469 nicvf_set_rx_function(dev);
1471 /* Done; Let PF make the BGX's RX and TX switches to ON position */
1472 nicvf_mbox_cfg_done(nic);
1476 nicvf_rss_term(nic);
1478 for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++)
1479 nicvf_vf_stop_tx_queue(dev, nic, qidx);
1481 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++)
1482 nicvf_vf_stop_rx_queue(dev, nic, qidx);
1484 nicvf_qset_rbdr_reclaim(nic, 0);
1485 nicvf_rbdr_release_mbufs(dev, nic);
1488 rte_free(nic->rbdr);
1492 nicvf_qset_reclaim(nic);
1497 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1501 struct nicvf *nic = nicvf_pmd_priv(dev);
1503 PMD_INIT_FUNC_TRACE();
1505 /* Teardown secondary vf first */
1506 for (i = 0; i < nic->sqs_count; i++) {
1507 if (!nic->snicvf[i])
1510 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1513 /* Stop the primary VF now */
1514 nicvf_vf_stop(dev, nic, cleanup);
1516 /* Disable loopback */
1517 ret = nicvf_loopback_config(nic, 0);
1519 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1521 /* Reclaim CPI configuration */
1522 ret = nicvf_mbox_config_cpi(nic, 0);
1524 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1528 nicvf_dev_stop(struct rte_eth_dev *dev)
1530 PMD_INIT_FUNC_TRACE();
1532 nicvf_dev_stop_cleanup(dev, false);
1536 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1540 uint16_t tx_start, tx_end;
1541 uint16_t rx_start, rx_end;
1543 PMD_INIT_FUNC_TRACE();
1546 /* Let PF make the BGX's RX and TX switches to OFF position */
1547 nicvf_mbox_shutdown(nic);
1550 /* Disable VLAN Strip */
1551 nicvf_vlan_hw_strip(nic, 0);
1553 /* Get queue ranges for this VF */
1554 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1556 for (qidx = tx_start; qidx <= tx_end; qidx++)
1557 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1559 /* Get queue ranges for this VF */
1560 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1563 for (qidx = rx_start; qidx <= rx_end; qidx++)
1564 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1567 ret = nicvf_qset_rbdr_reclaim(nic, 0);
1569 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1571 /* Move all charged buffers in RBDR back to pool */
1572 if (nic->rbdr != NULL)
1573 nicvf_rbdr_release_mbufs(dev, nic);
1576 ret = nicvf_qset_reclaim(nic);
1578 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1580 /* Disable all interrupts */
1581 nicvf_disable_all_interrupts(nic);
1583 /* Free RBDR SW structure */
1585 rte_free(nic->rbdr);
1591 nicvf_dev_close(struct rte_eth_dev *dev)
1594 struct nicvf *nic = nicvf_pmd_priv(dev);
1596 PMD_INIT_FUNC_TRACE();
1598 nicvf_dev_stop_cleanup(dev, true);
1599 nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1601 for (i = 0; i < nic->sqs_count; i++) {
1602 if (!nic->snicvf[i])
1605 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1610 nicvf_dev_configure(struct rte_eth_dev *dev)
1612 struct rte_eth_conf *conf = &dev->data->dev_conf;
1613 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1614 struct rte_eth_txmode *txmode = &conf->txmode;
1615 struct nicvf *nic = nicvf_pmd_priv(dev);
1617 PMD_INIT_FUNC_TRACE();
1619 if (!rte_eal_has_hugepages()) {
1620 PMD_INIT_LOG(INFO, "Huge page is not configured");
1624 if (txmode->mq_mode) {
1625 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1629 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1630 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1631 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1635 if (!rxmode->hw_strip_crc) {
1636 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1637 rxmode->hw_strip_crc = 1;
1640 if (rxmode->hw_ip_checksum) {
1641 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1642 rxmode->hw_ip_checksum = 0;
1645 if (rxmode->split_hdr_size) {
1646 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1650 if (rxmode->hw_vlan_filter) {
1651 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1655 if (rxmode->hw_vlan_extend) {
1656 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1660 if (rxmode->enable_lro) {
1661 PMD_INIT_LOG(INFO, "LRO not supported");
1665 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1666 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1670 if (conf->dcb_capability_en) {
1671 PMD_INIT_LOG(INFO, "DCB enable not supported");
1675 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1676 PMD_INIT_LOG(INFO, "Flow director not supported");
1680 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1681 dev->data->port_id, nicvf_hw_cap(nic));
1686 /* Initialize and register driver with DPDK Application */
1687 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1688 .dev_configure = nicvf_dev_configure,
1689 .dev_start = nicvf_dev_start,
1690 .dev_stop = nicvf_dev_stop,
1691 .link_update = nicvf_dev_link_update,
1692 .dev_close = nicvf_dev_close,
1693 .stats_get = nicvf_dev_stats_get,
1694 .stats_reset = nicvf_dev_stats_reset,
1695 .promiscuous_enable = nicvf_dev_promisc_enable,
1696 .dev_infos_get = nicvf_dev_info_get,
1697 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1698 .mtu_set = nicvf_dev_set_mtu,
1699 .reta_update = nicvf_dev_reta_update,
1700 .reta_query = nicvf_dev_reta_query,
1701 .rss_hash_update = nicvf_dev_rss_hash_update,
1702 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
1703 .rx_queue_start = nicvf_dev_rx_queue_start,
1704 .rx_queue_stop = nicvf_dev_rx_queue_stop,
1705 .tx_queue_start = nicvf_dev_tx_queue_start,
1706 .tx_queue_stop = nicvf_dev_tx_queue_stop,
1707 .rx_queue_setup = nicvf_dev_rx_queue_setup,
1708 .rx_queue_release = nicvf_dev_rx_queue_release,
1709 .rx_queue_count = nicvf_dev_rx_queue_count,
1710 .tx_queue_setup = nicvf_dev_tx_queue_setup,
1711 .tx_queue_release = nicvf_dev_tx_queue_release,
1712 .get_reg = nicvf_dev_get_regs,
1716 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
1719 struct rte_pci_device *pci_dev;
1720 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
1722 PMD_INIT_FUNC_TRACE();
1724 eth_dev->dev_ops = &nicvf_eth_dev_ops;
1726 /* For secondary processes, the primary has done all the work */
1727 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1728 /* Setup callbacks for secondary process */
1729 nicvf_set_tx_function(eth_dev);
1730 nicvf_set_rx_function(eth_dev);
1734 pci_dev = eth_dev->pci_dev;
1735 rte_eth_copy_pci_info(eth_dev, pci_dev);
1737 nic->device_id = pci_dev->id.device_id;
1738 nic->vendor_id = pci_dev->id.vendor_id;
1739 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
1740 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1742 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
1743 pci_dev->id.vendor_id, pci_dev->id.device_id,
1744 pci_dev->addr.domain, pci_dev->addr.bus,
1745 pci_dev->addr.devid, pci_dev->addr.function);
1747 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
1748 if (!nic->reg_base) {
1749 PMD_INIT_LOG(ERR, "Failed to map BAR0");
1754 nicvf_disable_all_interrupts(nic);
1756 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
1758 PMD_INIT_LOG(ERR, "Failed to start period alarm");
1762 ret = nicvf_mbox_check_pf_ready(nic);
1764 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
1768 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
1769 nic->node, nic->vf_id,
1770 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
1771 nic->sqs_mode ? "true" : "false",
1772 nic->loopback_supported ? "true" : "false"
1776 if (nic->sqs_mode) {
1777 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
1778 /* Detach port by returning Positive error number */
1783 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
1784 if (eth_dev->data->mac_addrs == NULL) {
1785 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
1789 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
1790 eth_random_addr(&nic->mac_addr[0]);
1792 ether_addr_copy((struct ether_addr *)nic->mac_addr,
1793 ð_dev->data->mac_addrs[0]);
1795 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
1797 PMD_INIT_LOG(ERR, "Failed to set mac addr");
1801 ret = nicvf_base_init(nic);
1803 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
1807 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
1808 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
1809 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
1810 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
1815 rte_free(eth_dev->data->mac_addrs);
1817 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
1822 static const struct rte_pci_id pci_id_nicvf_map[] = {
1824 .class_id = RTE_CLASS_ANY_ID,
1825 .vendor_id = PCI_VENDOR_ID_CAVIUM,
1826 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
1827 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
1828 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
1831 .class_id = RTE_CLASS_ANY_ID,
1832 .vendor_id = PCI_VENDOR_ID_CAVIUM,
1833 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
1834 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
1835 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
1838 .class_id = RTE_CLASS_ANY_ID,
1839 .vendor_id = PCI_VENDOR_ID_CAVIUM,
1840 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
1841 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
1842 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
1849 static struct eth_driver rte_nicvf_pmd = {
1851 .id_table = pci_id_nicvf_map,
1852 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1853 .probe = rte_eth_dev_pci_probe,
1854 .remove = rte_eth_dev_pci_remove,
1856 .eth_dev_init = nicvf_eth_dev_init,
1857 .dev_private_size = sizeof(struct nicvf),
1860 DRIVER_REGISTER_PCI(net_thunderx, rte_nicvf_pmd.pci_drv);
1861 DRIVER_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);