4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
45 #include <rte_alarm.h>
46 #include <rte_atomic.h>
47 #include <rte_branch_prediction.h>
48 #include <rte_byteorder.h>
49 #include <rte_common.h>
50 #include <rte_cycles.h>
51 #include <rte_debug.h>
54 #include <rte_ether.h>
55 #include <rte_ethdev.h>
56 #include <rte_interrupts.h>
58 #include <rte_memory.h>
59 #include <rte_memzone.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_tailq.h>
65 #include "base/nicvf_plat.h"
67 #include "nicvf_ethdev.h"
68 #include "nicvf_rxtx.h"
69 #include "nicvf_svf.h"
70 #include "nicvf_logs.h"
72 static void nicvf_dev_stop(struct rte_eth_dev *dev);
73 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
74 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
78 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
79 struct rte_eth_link *link)
81 struct rte_eth_link *dst = &dev->data->dev_link;
82 struct rte_eth_link *src = link;
84 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
85 *(uint64_t *)src) == 0)
92 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
94 link->link_status = nic->link_up;
95 link->link_duplex = ETH_LINK_AUTONEG;
96 if (nic->duplex == NICVF_HALF_DUPLEX)
97 link->link_duplex = ETH_LINK_HALF_DUPLEX;
98 else if (nic->duplex == NICVF_FULL_DUPLEX)
99 link->link_duplex = ETH_LINK_FULL_DUPLEX;
100 link->link_speed = nic->speed;
101 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
105 nicvf_interrupt(void *arg)
107 struct rte_eth_dev *dev = arg;
108 struct nicvf *nic = nicvf_pmd_priv(dev);
110 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
111 if (dev->data->dev_conf.intr_conf.lsc)
112 nicvf_set_eth_link_status(nic, &dev->data->dev_link);
113 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
116 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
117 nicvf_interrupt, dev);
121 nicvf_vf_interrupt(void *arg)
123 struct nicvf *nic = arg;
125 nicvf_reg_poll_interrupts(nic);
127 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
128 nicvf_vf_interrupt, nic);
132 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
134 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
138 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
140 return rte_eal_alarm_cancel(fn, arg);
144 * Return 0 means link status changed, -1 means not changed
147 nicvf_dev_link_update(struct rte_eth_dev *dev,
148 int wait_to_complete __rte_unused)
150 struct rte_eth_link link;
151 struct nicvf *nic = nicvf_pmd_priv(dev);
153 PMD_INIT_FUNC_TRACE();
155 memset(&link, 0, sizeof(link));
156 nicvf_set_eth_link_status(nic, &link);
157 return nicvf_atomic_write_link_status(dev, &link);
161 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
163 struct nicvf *nic = nicvf_pmd_priv(dev);
164 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
167 PMD_INIT_FUNC_TRACE();
169 if (frame_size > NIC_HW_MAX_FRS)
172 if (frame_size < NIC_HW_MIN_FRS)
175 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
178 * Refuse mtu that requires the support of scattered packets
179 * when this feature has not been enabled before.
181 if (!dev->data->scattered_rx &&
182 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
185 /* check <seg size> * <max_seg> >= max_frame */
186 if (dev->data->scattered_rx &&
187 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
190 if (frame_size > ETHER_MAX_LEN)
191 dev->data->dev_conf.rxmode.jumbo_frame = 1;
193 dev->data->dev_conf.rxmode.jumbo_frame = 0;
195 if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
198 /* Update max frame size */
199 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
202 for (i = 0; i < nic->sqs_count; i++)
203 nic->snicvf[i]->mtu = mtu;
209 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
211 uint64_t *data = regs->data;
212 struct nicvf *nic = nicvf_pmd_priv(dev);
215 regs->length = nicvf_reg_get_count();
216 regs->width = THUNDERX_REG_BYTES;
220 /* Support only full register dump */
221 if ((regs->length == 0) ||
222 (regs->length == (uint32_t)nicvf_reg_get_count())) {
223 regs->version = nic->vendor_id << 16 | nic->device_id;
224 nicvf_reg_dump(nic, data);
231 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
234 struct nicvf_hw_rx_qstats rx_qstats;
235 struct nicvf_hw_tx_qstats tx_qstats;
236 struct nicvf_hw_stats port_stats;
237 struct nicvf *nic = nicvf_pmd_priv(dev);
238 uint16_t rx_start, rx_end;
239 uint16_t tx_start, tx_end;
242 /* RX queue indices for the first VF */
243 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
245 /* Reading per RX ring stats */
246 for (qidx = rx_start; qidx <= rx_end; qidx++) {
247 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
250 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
251 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
252 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
255 /* TX queue indices for the first VF */
256 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
258 /* Reading per TX ring stats */
259 for (qidx = tx_start; qidx <= tx_end; qidx++) {
260 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
263 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
264 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
265 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
268 for (i = 0; i < nic->sqs_count; i++) {
269 struct nicvf *snic = nic->snicvf[i];
274 /* RX queue indices for a secondary VF */
275 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
277 /* Reading per RX ring stats */
278 for (qidx = rx_start; qidx <= rx_end; qidx++) {
279 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
282 nicvf_hw_get_rx_qstats(snic, &rx_qstats,
283 qidx % MAX_RCV_QUEUES_PER_QS);
284 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
285 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
288 /* TX queue indices for a secondary VF */
289 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
290 /* Reading per TX ring stats */
291 for (qidx = tx_start; qidx <= tx_end; qidx++) {
292 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
295 nicvf_hw_get_tx_qstats(snic, &tx_qstats,
296 qidx % MAX_SND_QUEUES_PER_QS);
297 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
298 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
302 nicvf_hw_get_stats(nic, &port_stats);
303 stats->ibytes = port_stats.rx_bytes;
304 stats->ipackets = port_stats.rx_ucast_frames;
305 stats->ipackets += port_stats.rx_bcast_frames;
306 stats->ipackets += port_stats.rx_mcast_frames;
307 stats->ierrors = port_stats.rx_l2_errors;
308 stats->imissed = port_stats.rx_drop_red;
309 stats->imissed += port_stats.rx_drop_overrun;
310 stats->imissed += port_stats.rx_drop_bcast;
311 stats->imissed += port_stats.rx_drop_mcast;
312 stats->imissed += port_stats.rx_drop_l3_bcast;
313 stats->imissed += port_stats.rx_drop_l3_mcast;
315 stats->obytes = port_stats.tx_bytes_ok;
316 stats->opackets = port_stats.tx_ucast_frames_ok;
317 stats->opackets += port_stats.tx_bcast_frames_ok;
318 stats->opackets += port_stats.tx_mcast_frames_ok;
319 stats->oerrors = port_stats.tx_drops;
322 static const uint32_t *
323 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
326 static uint32_t ptypes[32];
327 struct nicvf *nic = nicvf_pmd_priv(dev);
328 static const uint32_t ptypes_common[] = {
330 RTE_PTYPE_L3_IPV4_EXT,
332 RTE_PTYPE_L3_IPV6_EXT,
337 static const uint32_t ptypes_tunnel[] = {
338 RTE_PTYPE_TUNNEL_GRE,
339 RTE_PTYPE_TUNNEL_GENEVE,
340 RTE_PTYPE_TUNNEL_VXLAN,
341 RTE_PTYPE_TUNNEL_NVGRE,
343 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
345 copied = sizeof(ptypes_common);
346 memcpy(ptypes, ptypes_common, copied);
347 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
348 memcpy((char *)ptypes + copied, ptypes_tunnel,
349 sizeof(ptypes_tunnel));
350 copied += sizeof(ptypes_tunnel);
353 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
354 if (dev->rx_pkt_burst == nicvf_recv_pkts ||
355 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
362 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
365 uint16_t rxqs = 0, txqs = 0;
366 struct nicvf *nic = nicvf_pmd_priv(dev);
367 uint16_t rx_start, rx_end;
368 uint16_t tx_start, tx_end;
370 /* Reset all primary nic counters */
371 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
372 for (i = rx_start; i <= rx_end; i++)
373 rxqs |= (0x3 << (i * 2));
375 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
376 for (i = tx_start; i <= tx_end; i++)
377 txqs |= (0x3 << (i * 2));
379 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
381 /* Reset secondary nic queue counters */
382 for (i = 0; i < nic->sqs_count; i++) {
383 struct nicvf *snic = nic->snicvf[i];
387 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
388 for (i = rx_start; i <= rx_end; i++)
389 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
391 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
392 for (i = tx_start; i <= tx_end; i++)
393 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
395 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
399 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
401 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
405 static inline uint64_t
406 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
408 uint64_t nic_rss = 0;
410 if (ethdev_rss & ETH_RSS_IPV4)
411 nic_rss |= RSS_IP_ENA;
413 if (ethdev_rss & ETH_RSS_IPV6)
414 nic_rss |= RSS_IP_ENA;
416 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
417 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
419 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
420 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
422 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
423 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
425 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
426 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
428 if (ethdev_rss & ETH_RSS_PORT)
429 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
431 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
432 if (ethdev_rss & ETH_RSS_VXLAN)
433 nic_rss |= RSS_TUN_VXLAN_ENA;
435 if (ethdev_rss & ETH_RSS_GENEVE)
436 nic_rss |= RSS_TUN_GENEVE_ENA;
438 if (ethdev_rss & ETH_RSS_NVGRE)
439 nic_rss |= RSS_TUN_NVGRE_ENA;
445 static inline uint64_t
446 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
448 uint64_t ethdev_rss = 0;
450 if (nic_rss & RSS_IP_ENA)
451 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
453 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
454 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
455 ETH_RSS_NONFRAG_IPV6_TCP);
457 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
458 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
459 ETH_RSS_NONFRAG_IPV6_UDP);
461 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
462 ethdev_rss |= ETH_RSS_PORT;
464 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
465 if (nic_rss & RSS_TUN_VXLAN_ENA)
466 ethdev_rss |= ETH_RSS_VXLAN;
468 if (nic_rss & RSS_TUN_GENEVE_ENA)
469 ethdev_rss |= ETH_RSS_GENEVE;
471 if (nic_rss & RSS_TUN_NVGRE_ENA)
472 ethdev_rss |= ETH_RSS_NVGRE;
478 nicvf_dev_reta_query(struct rte_eth_dev *dev,
479 struct rte_eth_rss_reta_entry64 *reta_conf,
482 struct nicvf *nic = nicvf_pmd_priv(dev);
483 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
486 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
487 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
488 "(%d) doesn't match the number hardware can supported "
489 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
493 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
497 /* Copy RETA table */
498 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
499 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
500 if ((reta_conf[i].mask >> j) & 0x01)
501 reta_conf[i].reta[j] = tbl[j];
508 nicvf_dev_reta_update(struct rte_eth_dev *dev,
509 struct rte_eth_rss_reta_entry64 *reta_conf,
512 struct nicvf *nic = nicvf_pmd_priv(dev);
513 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
516 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
517 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
518 "(%d) doesn't match the number hardware can supported "
519 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
523 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
527 /* Copy RETA table */
528 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
529 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
530 if ((reta_conf[i].mask >> j) & 0x01)
531 tbl[j] = reta_conf[i].reta[j];
534 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
538 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
539 struct rte_eth_rss_conf *rss_conf)
541 struct nicvf *nic = nicvf_pmd_priv(dev);
543 if (rss_conf->rss_key)
544 nicvf_rss_get_key(nic, rss_conf->rss_key);
546 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
547 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
552 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
553 struct rte_eth_rss_conf *rss_conf)
555 struct nicvf *nic = nicvf_pmd_priv(dev);
558 if (rss_conf->rss_key &&
559 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
560 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
561 rss_conf->rss_key_len);
565 if (rss_conf->rss_key)
566 nicvf_rss_set_key(nic, rss_conf->rss_key);
568 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
569 nicvf_rss_set_cfg(nic, nic_rss);
574 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
575 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
577 const struct rte_memzone *rz;
578 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
580 rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
581 nicvf_netdev_qidx(nic, qidx), ring_size,
582 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
584 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
588 memset(rz->addr, 0, ring_size);
590 rxq->phys = rz->phys_addr;
591 rxq->desc = rz->addr;
592 rxq->qlen_mask = desc_cnt - 1;
598 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
599 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
601 const struct rte_memzone *rz;
602 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
604 rz = rte_eth_dma_zone_reserve(dev, "sq",
605 nicvf_netdev_qidx(nic, qidx), ring_size,
606 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
608 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
612 memset(rz->addr, 0, ring_size);
614 sq->phys = rz->phys_addr;
616 sq->qlen_mask = desc_cnt - 1;
622 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
623 uint32_t desc_cnt, uint32_t buffsz)
625 struct nicvf_rbdr *rbdr;
626 const struct rte_memzone *rz;
629 assert(nic->rbdr == NULL);
630 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
631 RTE_CACHE_LINE_SIZE, nic->node);
633 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
637 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
638 rz = rte_eth_dma_zone_reserve(dev, "rbdr",
639 nicvf_netdev_qidx(nic, 0), ring_size,
640 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
642 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
646 memset(rz->addr, 0, ring_size);
648 rbdr->phys = rz->phys_addr;
651 rbdr->desc = rz->addr;
652 rbdr->buffsz = buffsz;
653 rbdr->qlen_mask = desc_cnt - 1;
655 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
657 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
664 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
665 nicvf_phys_addr_t phy)
669 struct nicvf_rxq *rxq;
670 uint16_t rx_start, rx_end;
672 /* Get queue ranges for this VF */
673 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
675 for (qidx = rx_start; qidx <= rx_end; qidx++) {
676 rxq = dev->data->rx_queues[qidx];
677 if (rxq->precharge_cnt) {
678 obj = (void *)nicvf_mbuff_phy2virt(phy,
680 rte_mempool_put(rxq->pool, obj);
681 rxq->precharge_cnt--;
688 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
690 uint32_t qlen_mask, head;
691 struct rbdr_entry_t *entry;
692 struct nicvf_rbdr *rbdr = nic->rbdr;
694 qlen_mask = rbdr->qlen_mask;
696 while (head != rbdr->tail) {
697 entry = rbdr->desc + head;
698 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
700 head = head & qlen_mask;
705 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
710 while (head != txq->tail) {
711 if (txq->txbuffs[head]) {
712 rte_pktmbuf_free_seg(txq->txbuffs[head]);
713 txq->txbuffs[head] = NULL;
716 head = head & txq->qlen_mask;
721 nicvf_tx_queue_reset(struct nicvf_txq *txq)
723 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
725 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
726 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
733 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
736 struct nicvf_txq *txq;
739 assert(qidx < MAX_SND_QUEUES_PER_QS);
741 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
742 RTE_ETH_QUEUE_STATE_STARTED)
745 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
747 ret = nicvf_qset_sq_config(nic, qidx, txq);
749 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
750 nic->vf_id, qidx, ret);
751 goto config_sq_error;
754 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
755 RTE_ETH_QUEUE_STATE_STARTED;
759 nicvf_qset_sq_reclaim(nic, qidx);
764 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
767 struct nicvf_txq *txq;
770 assert(qidx < MAX_SND_QUEUES_PER_QS);
772 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
773 RTE_ETH_QUEUE_STATE_STOPPED)
776 ret = nicvf_qset_sq_reclaim(nic, qidx);
778 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
779 nic->vf_id, qidx, ret);
781 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
782 nicvf_tx_queue_release_mbufs(txq);
783 nicvf_tx_queue_reset(txq);
785 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
786 RTE_ETH_QUEUE_STATE_STOPPED;
791 nicvf_configure_cpi(struct rte_eth_dev *dev)
793 struct nicvf *nic = nicvf_pmd_priv(dev);
797 /* Count started rx queues */
798 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
799 if (dev->data->rx_queue_state[qidx] ==
800 RTE_ETH_QUEUE_STATE_STARTED)
803 nic->cpi_alg = CPI_ALG_NONE;
804 ret = nicvf_mbox_config_cpi(nic, qcnt);
806 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
812 nicvf_configure_rss(struct rte_eth_dev *dev)
814 struct nicvf *nic = nicvf_pmd_priv(dev);
818 rsshf = nicvf_rss_ethdev_to_nic(nic,
819 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
820 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
821 dev->data->dev_conf.rxmode.mq_mode,
822 dev->data->nb_rx_queues,
823 dev->data->dev_conf.lpbk_mode, rsshf);
825 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
826 ret = nicvf_rss_term(nic);
827 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
828 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
830 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
836 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
838 struct nicvf *nic = nicvf_pmd_priv(dev);
839 unsigned int idx, qmap_size;
840 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
841 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
843 if (nic->cpi_alg != CPI_ALG_NONE)
846 /* Prepare queue map */
847 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
848 if (dev->data->rx_queue_state[idx] ==
849 RTE_ETH_QUEUE_STATE_STARTED)
850 qmap[qmap_size++] = idx;
853 /* Update default RSS RETA */
854 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
855 default_reta[idx] = qmap[idx % qmap_size];
857 return nicvf_rss_reta_update(nic, default_reta,
858 NIC_MAX_RSS_IDR_TBL_SIZE);
862 nicvf_dev_tx_queue_release(void *sq)
864 struct nicvf_txq *txq;
866 PMD_INIT_FUNC_TRACE();
868 txq = (struct nicvf_txq *)sq;
870 if (txq->txbuffs != NULL) {
871 nicvf_tx_queue_release_mbufs(txq);
872 rte_free(txq->txbuffs);
880 nicvf_set_tx_function(struct rte_eth_dev *dev)
882 struct nicvf_txq *txq;
884 bool multiseg = false;
886 for (i = 0; i < dev->data->nb_tx_queues; i++) {
887 txq = dev->data->tx_queues[i];
888 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
894 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
896 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
897 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
899 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
900 dev->tx_pkt_burst = nicvf_xmit_pkts;
903 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
904 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
906 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
910 nicvf_set_rx_function(struct rte_eth_dev *dev)
912 if (dev->data->scattered_rx) {
913 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
914 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
916 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
917 dev->rx_pkt_burst = nicvf_recv_pkts;
922 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
923 uint16_t nb_desc, unsigned int socket_id,
924 const struct rte_eth_txconf *tx_conf)
926 uint16_t tx_free_thresh;
927 uint8_t is_single_pool;
928 struct nicvf_txq *txq;
929 struct nicvf *nic = nicvf_pmd_priv(dev);
931 PMD_INIT_FUNC_TRACE();
933 if (qidx >= MAX_SND_QUEUES_PER_QS)
934 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
936 qidx = qidx % MAX_SND_QUEUES_PER_QS;
938 /* Socket id check */
939 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
940 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
941 socket_id, nic->node);
943 /* Tx deferred start is not supported */
944 if (tx_conf->tx_deferred_start) {
945 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
949 /* Roundup nb_desc to available qsize and validate max number of desc */
950 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
952 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
956 /* Validate tx_free_thresh */
957 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
958 tx_conf->tx_free_thresh :
959 NICVF_DEFAULT_TX_FREE_THRESH);
961 if (tx_free_thresh > (nb_desc) ||
962 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
964 "tx_free_thresh must be less than the number of TX "
965 "descriptors. (tx_free_thresh=%u port=%d "
966 "queue=%d)", (unsigned int)tx_free_thresh,
967 (int)dev->data->port_id, (int)qidx);
971 /* Free memory prior to re-allocation if needed. */
972 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
973 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
974 nicvf_netdev_qidx(nic, qidx));
975 nicvf_dev_tx_queue_release(
976 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
977 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
980 /* Allocating tx queue data structure */
981 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
982 RTE_CACHE_LINE_SIZE, nic->node);
984 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
985 nicvf_netdev_qidx(nic, qidx));
990 txq->queue_id = qidx;
991 txq->tx_free_thresh = tx_free_thresh;
992 txq->txq_flags = tx_conf->txq_flags;
993 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
994 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
995 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
996 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
998 /* Choose optimum free threshold value for multipool case */
999 if (!is_single_pool) {
1000 txq->tx_free_thresh = (uint16_t)
1001 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1002 NICVF_TX_FREE_MPOOL_THRESH :
1003 tx_conf->tx_free_thresh);
1004 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1006 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1009 /* Allocate software ring */
1010 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1011 nb_desc * sizeof(struct rte_mbuf *),
1012 RTE_CACHE_LINE_SIZE, nic->node);
1014 if (txq->txbuffs == NULL) {
1015 nicvf_dev_tx_queue_release(txq);
1019 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1020 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1021 nicvf_dev_tx_queue_release(txq);
1025 nicvf_tx_queue_reset(txq);
1027 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
1028 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1031 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1032 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1033 RTE_ETH_QUEUE_STATE_STOPPED;
1038 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1041 uint32_t nb_pkts, released_pkts = 0;
1042 uint32_t refill_cnt = 0;
1043 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1045 if (dev->rx_pkt_burst == NULL)
1048 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1049 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1050 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1051 NICVF_MAX_RX_FREE_THRESH);
1052 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt);
1054 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1060 refill_cnt += nicvf_dev_rbdr_refill(dev,
1061 nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1063 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d",
1064 released_pkts, refill_cnt);
1068 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1071 rxq->available_space = 0;
1072 rxq->recv_buffers = 0;
1076 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1079 struct nicvf_rxq *rxq;
1082 assert(qidx < MAX_RCV_QUEUES_PER_QS);
1084 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1085 RTE_ETH_QUEUE_STATE_STARTED)
1088 /* Update rbdr pointer to all rxq */
1089 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1090 rxq->shared_rbdr = nic->rbdr;
1092 ret = nicvf_qset_rq_config(nic, qidx, rxq);
1094 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1095 nic->vf_id, qidx, ret);
1096 goto config_rq_error;
1098 ret = nicvf_qset_cq_config(nic, qidx, rxq);
1100 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1101 nic->vf_id, qidx, ret);
1102 goto config_cq_error;
1105 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1106 RTE_ETH_QUEUE_STATE_STARTED;
1110 nicvf_qset_cq_reclaim(nic, qidx);
1112 nicvf_qset_rq_reclaim(nic, qidx);
1117 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1120 struct nicvf_rxq *rxq;
1121 int ret, other_error;
1123 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1124 RTE_ETH_QUEUE_STATE_STOPPED)
1127 ret = nicvf_qset_rq_reclaim(nic, qidx);
1129 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1130 nic->vf_id, qidx, ret);
1133 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1134 nicvf_rx_queue_release_mbufs(dev, rxq);
1135 nicvf_rx_queue_reset(rxq);
1137 ret = nicvf_qset_cq_reclaim(nic, qidx);
1139 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1140 nic->vf_id, qidx, ret);
1143 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1144 RTE_ETH_QUEUE_STATE_STOPPED;
1149 nicvf_dev_rx_queue_release(void *rx_queue)
1151 PMD_INIT_FUNC_TRACE();
1157 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1159 struct nicvf *nic = nicvf_pmd_priv(dev);
1162 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1163 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1165 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1167 ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1171 ret = nicvf_configure_cpi(dev);
1175 return nicvf_configure_rss_reta(dev);
1179 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1182 struct nicvf *nic = nicvf_pmd_priv(dev);
1184 if (qidx >= MAX_SND_QUEUES_PER_QS)
1185 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1187 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1189 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1190 ret |= nicvf_configure_cpi(dev);
1191 ret |= nicvf_configure_rss_reta(dev);
1196 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1198 struct nicvf *nic = nicvf_pmd_priv(dev);
1200 if (qidx >= MAX_SND_QUEUES_PER_QS)
1201 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1203 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1205 return nicvf_vf_start_tx_queue(dev, nic, qidx);
1209 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1211 struct nicvf *nic = nicvf_pmd_priv(dev);
1213 if (qidx >= MAX_SND_QUEUES_PER_QS)
1214 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1216 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1218 return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1223 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1224 uint16_t nb_desc, unsigned int socket_id,
1225 const struct rte_eth_rxconf *rx_conf,
1226 struct rte_mempool *mp)
1228 uint16_t rx_free_thresh;
1229 struct nicvf_rxq *rxq;
1230 struct nicvf *nic = nicvf_pmd_priv(dev);
1232 PMD_INIT_FUNC_TRACE();
1234 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1235 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1237 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1239 /* Socket id check */
1240 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1241 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1242 socket_id, nic->node);
1244 /* Mempool memory must be contiguous, so must be one memory segment*/
1245 if (mp->nb_mem_chunks != 1) {
1246 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1250 /* Mempool memory must be physically contiguous */
1251 if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1252 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1256 /* Rx deferred start is not supported */
1257 if (rx_conf->rx_deferred_start) {
1258 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1262 /* Roundup nb_desc to available qsize and validate max number of desc */
1263 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1265 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1269 /* Check rx_free_thresh upper bound */
1270 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1271 rx_conf->rx_free_thresh :
1272 NICVF_DEFAULT_RX_FREE_THRESH);
1273 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1274 rx_free_thresh >= nb_desc * .75) {
1275 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1280 /* Free memory prior to re-allocation if needed */
1281 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1282 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1283 nicvf_netdev_qidx(nic, qidx));
1284 nicvf_dev_rx_queue_release(
1285 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1286 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1289 /* Allocate rxq memory */
1290 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1291 RTE_CACHE_LINE_SIZE, nic->node);
1293 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1294 nicvf_netdev_qidx(nic, qidx));
1300 rxq->queue_id = qidx;
1301 rxq->port_id = dev->data->port_id;
1302 rxq->rx_free_thresh = rx_free_thresh;
1303 rxq->rx_drop_en = rx_conf->rx_drop_en;
1304 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1305 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1306 rxq->precharge_cnt = 0;
1308 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1309 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1311 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1314 /* Alloc completion queue */
1315 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1316 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1317 nicvf_dev_rx_queue_release(rxq);
1321 nicvf_rx_queue_reset(rxq);
1323 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1324 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1325 rte_mempool_avail_count(mp), rxq->phys);
1327 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1328 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1329 RTE_ETH_QUEUE_STATE_STOPPED;
1334 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1336 struct nicvf *nic = nicvf_pmd_priv(dev);
1337 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1339 PMD_INIT_FUNC_TRACE();
1341 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1343 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1344 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1345 dev_info->max_rx_queues =
1346 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1347 dev_info->max_tx_queues =
1348 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1349 dev_info->max_mac_addrs = 1;
1350 dev_info->max_vfs = pci_dev->max_vfs;
1352 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1353 dev_info->tx_offload_capa =
1354 DEV_TX_OFFLOAD_IPV4_CKSUM |
1355 DEV_TX_OFFLOAD_UDP_CKSUM |
1356 DEV_TX_OFFLOAD_TCP_CKSUM |
1357 DEV_TX_OFFLOAD_TCP_TSO |
1358 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1360 dev_info->reta_size = nic->rss_info.rss_size;
1361 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1362 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1363 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1364 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1366 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1367 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1371 dev_info->default_txconf = (struct rte_eth_txconf) {
1372 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1374 ETH_TXQ_FLAGS_NOMULTSEGS |
1375 ETH_TXQ_FLAGS_NOREFCOUNT |
1376 ETH_TXQ_FLAGS_NOMULTMEMP |
1377 ETH_TXQ_FLAGS_NOVLANOFFL |
1378 ETH_TXQ_FLAGS_NOXSUMSCTP,
1382 static nicvf_phys_addr_t
1383 rbdr_rte_mempool_get(void *dev, void *opaque)
1387 struct nicvf_rxq *rxq;
1388 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1389 struct nicvf *nic = (struct nicvf *)opaque;
1390 uint16_t rx_start, rx_end;
1392 /* Get queue ranges for this VF */
1393 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1395 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1396 rxq = eth_dev->data->rx_queues[qidx];
1397 /* Maintain equal buffer count across all pools */
1398 if (rxq->precharge_cnt >= rxq->qlen_mask)
1400 rxq->precharge_cnt++;
1401 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1403 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1409 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1412 uint16_t qidx, data_off;
1413 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1414 uint64_t mbuf_phys_off = 0;
1415 struct nicvf_rxq *rxq;
1416 struct rte_mbuf *mbuf;
1417 uint16_t rx_start, rx_end;
1418 uint16_t tx_start, tx_end;
1420 PMD_INIT_FUNC_TRACE();
1422 /* Userspace process exited without proper shutdown in last run */
1423 if (nicvf_qset_rbdr_active(nic, 0))
1424 nicvf_vf_stop(dev, nic, false);
1426 /* Get queue ranges for this VF */
1427 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1430 * Thunderx nicvf PMD can support more than one pool per port only when
1431 * 1) Data payload size is same across all the pools in given port
1433 * 2) All mbuffs in the pools are from the same hugepage
1435 * 3) Mbuff metadata size is same across all the pools in given port
1437 * This is to support existing application that uses multiple pool/port.
1438 * But, the purpose of using multipool for QoS will not be addressed.
1442 /* Validate mempool attributes */
1443 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1444 rxq = dev->data->rx_queues[qidx];
1445 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1446 mbuf = rte_pktmbuf_alloc(rxq->pool);
1448 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1450 nic->vf_id, qidx, rxq->pool->name);
1453 data_off = nicvf_mbuff_meta_length(mbuf);
1454 data_off += RTE_PKTMBUF_HEADROOM;
1455 rte_pktmbuf_free(mbuf);
1457 if (data_off % RTE_CACHE_LINE_SIZE) {
1458 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1459 rxq->pool->name, data_off,
1460 data_off % RTE_CACHE_LINE_SIZE);
1463 rxq->mbuf_phys_off -= data_off;
1465 if (mbuf_phys_off == 0)
1466 mbuf_phys_off = rxq->mbuf_phys_off;
1467 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1468 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1469 PRIx64, rxq->pool->name, nic->vf_id,
1475 /* Check the level of buffers in the pool */
1477 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1478 rxq = dev->data->rx_queues[qidx];
1479 /* Count total numbers of rxq descs */
1480 total_rxq_desc += rxq->qlen_mask + 1;
1481 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1482 exp_buffs *= dev->data->nb_rx_queues;
1483 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1484 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1486 rte_mempool_avail_count(rxq->pool),
1492 /* Check RBDR desc overflow */
1493 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1495 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1496 "VF%d", nic->vf_id);
1501 ret = nicvf_qset_config(nic);
1503 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1508 /* Allocate RBDR and RBDR ring desc */
1509 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1510 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1512 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1513 "VF%d", nic->vf_id);
1517 /* Enable and configure RBDR registers */
1518 ret = nicvf_qset_rbdr_config(nic, 0);
1520 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1522 goto qset_rbdr_free;
1525 /* Fill rte_mempool buffers in RBDR pool and precharge it */
1526 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1529 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1531 goto qset_rbdr_reclaim;
1534 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1535 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1537 /* Configure VLAN Strip */
1538 nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1540 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1541 * to the 64bit memory address.
1542 * The alignment creates a hole in mbuf(between the end of headroom and
1543 * packet data start). The new revision of the HW provides an option to
1544 * disable the L3 alignment feature and make mbuf layout looks
1545 * more like other NICs. For better application compatibility, disabling
1546 * l3 alignment feature on the hardware revisions it supports
1548 nicvf_apad_config(nic, false);
1550 /* Get queue ranges for this VF */
1551 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1553 /* Configure TX queues */
1554 for (qidx = tx_start; qidx <= tx_end; qidx++) {
1555 ret = nicvf_vf_start_tx_queue(dev, nic,
1556 qidx % MAX_SND_QUEUES_PER_QS);
1558 goto start_txq_error;
1561 /* Configure RX queues */
1562 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1563 ret = nicvf_vf_start_rx_queue(dev, nic,
1564 qidx % MAX_RCV_QUEUES_PER_QS);
1566 goto start_rxq_error;
1569 if (!nic->sqs_mode) {
1570 /* Configure CPI algorithm */
1571 ret = nicvf_configure_cpi(dev);
1573 goto start_txq_error;
1575 ret = nicvf_mbox_get_rss_size(nic);
1577 PMD_INIT_LOG(ERR, "Failed to get rss table size");
1578 goto qset_rss_error;
1582 ret = nicvf_configure_rss(dev);
1584 goto qset_rss_error;
1587 /* Done; Let PF make the BGX's RX and TX switches to ON position */
1588 nicvf_mbox_cfg_done(nic);
1592 nicvf_rss_term(nic);
1594 for (qidx = rx_start; qidx <= rx_end; qidx++)
1595 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1597 for (qidx = tx_start; qidx <= tx_end; qidx++)
1598 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1600 nicvf_qset_rbdr_reclaim(nic, 0);
1601 nicvf_rbdr_release_mbufs(dev, nic);
1604 rte_free(nic->rbdr);
1608 nicvf_qset_reclaim(nic);
1613 nicvf_dev_start(struct rte_eth_dev *dev)
1618 struct nicvf *nic = nicvf_pmd_priv(dev);
1619 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1621 uint32_t buffsz = 0, rbdrsz = 0;
1622 struct rte_pktmbuf_pool_private *mbp_priv;
1623 struct nicvf_rxq *rxq;
1625 PMD_INIT_FUNC_TRACE();
1627 /* This function must be called for a primary device */
1628 assert_primary(nic);
1630 /* Validate RBDR buff size */
1631 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1632 rxq = dev->data->rx_queues[qidx];
1633 mbp_priv = rte_mempool_get_priv(rxq->pool);
1634 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1636 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1641 if (rbdrsz != buffsz) {
1642 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1643 qidx, rbdrsz, buffsz);
1648 /* Configure loopback */
1649 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1651 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1655 /* Reset all statistics counters attached to this port */
1656 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1658 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1662 /* Setup scatter mode if needed by jumbo */
1663 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1664 2 * VLAN_TAG_SIZE > buffsz)
1665 dev->data->scattered_rx = 1;
1666 if (rx_conf->enable_scatter)
1667 dev->data->scattered_rx = 1;
1669 /* Setup MTU based on max_rx_pkt_len or default */
1670 mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1671 dev->data->dev_conf.rxmode.max_rx_pkt_len
1672 - ETHER_HDR_LEN - ETHER_CRC_LEN
1675 if (nicvf_dev_set_mtu(dev, mtu)) {
1676 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1680 ret = nicvf_vf_start(dev, nic, rbdrsz);
1684 for (i = 0; i < nic->sqs_count; i++) {
1685 assert(nic->snicvf[i]);
1687 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1692 /* Configure callbacks based on scatter mode */
1693 nicvf_set_tx_function(dev);
1694 nicvf_set_rx_function(dev);
1700 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1704 struct nicvf *nic = nicvf_pmd_priv(dev);
1706 PMD_INIT_FUNC_TRACE();
1708 /* Teardown secondary vf first */
1709 for (i = 0; i < nic->sqs_count; i++) {
1710 if (!nic->snicvf[i])
1713 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1716 /* Stop the primary VF now */
1717 nicvf_vf_stop(dev, nic, cleanup);
1719 /* Disable loopback */
1720 ret = nicvf_loopback_config(nic, 0);
1722 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1724 /* Reclaim CPI configuration */
1725 ret = nicvf_mbox_config_cpi(nic, 0);
1727 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1731 nicvf_dev_stop(struct rte_eth_dev *dev)
1733 PMD_INIT_FUNC_TRACE();
1735 nicvf_dev_stop_cleanup(dev, false);
1739 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1743 uint16_t tx_start, tx_end;
1744 uint16_t rx_start, rx_end;
1746 PMD_INIT_FUNC_TRACE();
1749 /* Let PF make the BGX's RX and TX switches to OFF position */
1750 nicvf_mbox_shutdown(nic);
1753 /* Disable VLAN Strip */
1754 nicvf_vlan_hw_strip(nic, 0);
1756 /* Get queue ranges for this VF */
1757 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1759 for (qidx = tx_start; qidx <= tx_end; qidx++)
1760 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1762 /* Get queue ranges for this VF */
1763 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1766 for (qidx = rx_start; qidx <= rx_end; qidx++)
1767 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1770 ret = nicvf_qset_rbdr_reclaim(nic, 0);
1772 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1774 /* Move all charged buffers in RBDR back to pool */
1775 if (nic->rbdr != NULL)
1776 nicvf_rbdr_release_mbufs(dev, nic);
1779 ret = nicvf_qset_reclaim(nic);
1781 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1783 /* Disable all interrupts */
1784 nicvf_disable_all_interrupts(nic);
1786 /* Free RBDR SW structure */
1788 rte_free(nic->rbdr);
1794 nicvf_dev_close(struct rte_eth_dev *dev)
1797 struct nicvf *nic = nicvf_pmd_priv(dev);
1799 PMD_INIT_FUNC_TRACE();
1801 nicvf_dev_stop_cleanup(dev, true);
1802 nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1804 for (i = 0; i < nic->sqs_count; i++) {
1805 if (!nic->snicvf[i])
1808 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1813 nicvf_request_sqs(struct nicvf *nic)
1817 assert_primary(nic);
1818 assert(nic->sqs_count > 0);
1819 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1821 /* Set no of Rx/Tx queues in each of the SQsets */
1822 for (i = 0; i < nic->sqs_count; i++) {
1823 if (nicvf_svf_empty())
1824 rte_panic("Cannot assign sufficient number of "
1825 "secondary queues to primary VF%" PRIu8 "\n",
1828 nic->snicvf[i] = nicvf_svf_pop();
1829 nic->snicvf[i]->sqs_id = i;
1832 return nicvf_mbox_request_sqs(nic);
1836 nicvf_dev_configure(struct rte_eth_dev *dev)
1838 struct rte_eth_dev_data *data = dev->data;
1839 struct rte_eth_conf *conf = &data->dev_conf;
1840 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1841 struct rte_eth_txmode *txmode = &conf->txmode;
1842 struct nicvf *nic = nicvf_pmd_priv(dev);
1845 PMD_INIT_FUNC_TRACE();
1847 if (!rte_eal_has_hugepages()) {
1848 PMD_INIT_LOG(INFO, "Huge page is not configured");
1852 if (txmode->mq_mode) {
1853 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1857 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1858 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1859 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1863 if (!rxmode->hw_strip_crc) {
1864 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1865 rxmode->hw_strip_crc = 1;
1868 if (rxmode->hw_ip_checksum) {
1869 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1870 rxmode->hw_ip_checksum = 0;
1873 if (rxmode->split_hdr_size) {
1874 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1878 if (rxmode->hw_vlan_filter) {
1879 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1883 if (rxmode->hw_vlan_extend) {
1884 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1888 if (rxmode->enable_lro) {
1889 PMD_INIT_LOG(INFO, "LRO not supported");
1893 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1894 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1898 if (conf->dcb_capability_en) {
1899 PMD_INIT_LOG(INFO, "DCB enable not supported");
1903 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1904 PMD_INIT_LOG(INFO, "Flow director not supported");
1908 assert_primary(nic);
1909 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1910 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1911 if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1912 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1913 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1918 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1920 if (nic->sqs_count > 0) {
1921 if (nicvf_request_sqs(nic)) {
1922 rte_panic("Cannot assign sufficient number of "
1923 "secondary queues to PORT%d VF%" PRIu8 "\n",
1924 dev->data->port_id, nic->vf_id);
1928 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1929 dev->data->port_id, nicvf_hw_cap(nic));
1934 /* Initialize and register driver with DPDK Application */
1935 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1936 .dev_configure = nicvf_dev_configure,
1937 .dev_start = nicvf_dev_start,
1938 .dev_stop = nicvf_dev_stop,
1939 .link_update = nicvf_dev_link_update,
1940 .dev_close = nicvf_dev_close,
1941 .stats_get = nicvf_dev_stats_get,
1942 .stats_reset = nicvf_dev_stats_reset,
1943 .promiscuous_enable = nicvf_dev_promisc_enable,
1944 .dev_infos_get = nicvf_dev_info_get,
1945 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1946 .mtu_set = nicvf_dev_set_mtu,
1947 .reta_update = nicvf_dev_reta_update,
1948 .reta_query = nicvf_dev_reta_query,
1949 .rss_hash_update = nicvf_dev_rss_hash_update,
1950 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
1951 .rx_queue_start = nicvf_dev_rx_queue_start,
1952 .rx_queue_stop = nicvf_dev_rx_queue_stop,
1953 .tx_queue_start = nicvf_dev_tx_queue_start,
1954 .tx_queue_stop = nicvf_dev_tx_queue_stop,
1955 .rx_queue_setup = nicvf_dev_rx_queue_setup,
1956 .rx_queue_release = nicvf_dev_rx_queue_release,
1957 .rx_queue_count = nicvf_dev_rx_queue_count,
1958 .tx_queue_setup = nicvf_dev_tx_queue_setup,
1959 .tx_queue_release = nicvf_dev_tx_queue_release,
1960 .get_reg = nicvf_dev_get_regs,
1964 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
1967 struct rte_pci_device *pci_dev;
1968 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
1970 PMD_INIT_FUNC_TRACE();
1972 eth_dev->dev_ops = &nicvf_eth_dev_ops;
1974 /* For secondary processes, the primary has done all the work */
1975 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1977 /* Setup callbacks for secondary process */
1978 nicvf_set_tx_function(eth_dev);
1979 nicvf_set_rx_function(eth_dev);
1982 /* If nic == NULL than it is secondary function
1983 * so ethdev need to be released by caller */
1988 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1989 rte_eth_copy_pci_info(eth_dev, pci_dev);
1991 nic->device_id = pci_dev->id.device_id;
1992 nic->vendor_id = pci_dev->id.vendor_id;
1993 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
1994 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1996 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
1997 pci_dev->id.vendor_id, pci_dev->id.device_id,
1998 pci_dev->addr.domain, pci_dev->addr.bus,
1999 pci_dev->addr.devid, pci_dev->addr.function);
2001 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2002 if (!nic->reg_base) {
2003 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2008 nicvf_disable_all_interrupts(nic);
2010 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2012 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2016 ret = nicvf_mbox_check_pf_ready(nic);
2018 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2022 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2023 nic->node, nic->vf_id,
2024 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2025 nic->sqs_mode ? "true" : "false",
2026 nic->loopback_supported ? "true" : "false"
2030 ret = nicvf_base_init(nic);
2032 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2036 if (nic->sqs_mode) {
2037 /* Push nic to stack of secondary vfs */
2038 nicvf_svf_push(nic);
2040 /* Steal nic pointer from the device for further reuse */
2041 eth_dev->data->dev_private = NULL;
2043 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2044 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2046 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2050 /* Detach port by returning postive error number */
2054 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2055 if (eth_dev->data->mac_addrs == NULL) {
2056 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2060 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2061 eth_random_addr(&nic->mac_addr[0]);
2063 ether_addr_copy((struct ether_addr *)nic->mac_addr,
2064 ð_dev->data->mac_addrs[0]);
2066 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2068 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2072 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2073 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2074 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2075 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2080 rte_free(eth_dev->data->mac_addrs);
2082 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2087 static const struct rte_pci_id pci_id_nicvf_map[] = {
2089 .class_id = RTE_CLASS_ANY_ID,
2090 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2091 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2092 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2093 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2096 .class_id = RTE_CLASS_ANY_ID,
2097 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2098 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2099 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2100 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2103 .class_id = RTE_CLASS_ANY_ID,
2104 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2105 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2106 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2107 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2110 .class_id = RTE_CLASS_ANY_ID,
2111 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2112 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2113 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2114 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2121 static struct eth_driver rte_nicvf_pmd = {
2123 .id_table = pci_id_nicvf_map,
2124 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2125 .probe = rte_eth_dev_pci_probe,
2126 .remove = rte_eth_dev_pci_remove,
2128 .eth_dev_init = nicvf_eth_dev_init,
2129 .dev_private_size = sizeof(struct nicvf),
2132 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd.pci_drv);
2133 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2134 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio");