4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
44 #include <sys/timerfd.h>
46 #include <rte_alarm.h>
47 #include <rte_atomic.h>
48 #include <rte_branch_prediction.h>
49 #include <rte_byteorder.h>
50 #include <rte_common.h>
51 #include <rte_cycles.h>
52 #include <rte_debug.h>
55 #include <rte_ether.h>
56 #include <rte_ethdev.h>
57 #include <rte_interrupts.h>
59 #include <rte_memory.h>
60 #include <rte_memzone.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_tailq.h>
66 #include "base/nicvf_plat.h"
68 #include "nicvf_ethdev.h"
70 #include "nicvf_logs.h"
73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
74 struct rte_eth_link *link)
76 struct rte_eth_link *dst = &dev->data->dev_link;
77 struct rte_eth_link *src = link;
79 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
80 *(uint64_t *)src) == 0)
87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
89 link->link_status = nic->link_up;
90 link->link_duplex = ETH_LINK_AUTONEG;
91 if (nic->duplex == NICVF_HALF_DUPLEX)
92 link->link_duplex = ETH_LINK_HALF_DUPLEX;
93 else if (nic->duplex == NICVF_FULL_DUPLEX)
94 link->link_duplex = ETH_LINK_FULL_DUPLEX;
95 link->link_speed = nic->speed;
96 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
100 nicvf_interrupt(void *arg)
102 struct nicvf *nic = arg;
104 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
105 if (nic->eth_dev->data->dev_conf.intr_conf.lsc)
106 nicvf_set_eth_link_status(nic,
107 &nic->eth_dev->data->dev_link);
108 _rte_eth_dev_callback_process(nic->eth_dev,
109 RTE_ETH_EVENT_INTR_LSC);
112 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
113 nicvf_interrupt, nic);
117 nicvf_periodic_alarm_start(struct nicvf *nic)
119 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
120 nicvf_interrupt, nic);
124 nicvf_periodic_alarm_stop(struct nicvf *nic)
126 return rte_eal_alarm_cancel(nicvf_interrupt, nic);
130 * Return 0 means link status changed, -1 means not changed
133 nicvf_dev_link_update(struct rte_eth_dev *dev,
134 int wait_to_complete __rte_unused)
136 struct rte_eth_link link;
137 struct nicvf *nic = nicvf_pmd_priv(dev);
139 PMD_INIT_FUNC_TRACE();
141 memset(&link, 0, sizeof(link));
142 nicvf_set_eth_link_status(nic, &link);
143 return nicvf_atomic_write_link_status(dev, &link);
147 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
149 struct nicvf *nic = nicvf_pmd_priv(dev);
150 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
152 PMD_INIT_FUNC_TRACE();
154 if (frame_size > NIC_HW_MAX_FRS)
157 if (frame_size < NIC_HW_MIN_FRS)
160 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
163 * Refuse mtu that requires the support of scattered packets
164 * when this feature has not been enabled before.
166 if (!dev->data->scattered_rx &&
167 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
170 /* check <seg size> * <max_seg> >= max_frame */
171 if (dev->data->scattered_rx &&
172 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
175 if (frame_size > ETHER_MAX_LEN)
176 dev->data->dev_conf.rxmode.jumbo_frame = 1;
178 dev->data->dev_conf.rxmode.jumbo_frame = 0;
180 if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
183 /* Update max frame size */
184 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
190 nicvf_dev_get_reg_length(struct rte_eth_dev *dev __rte_unused)
192 return nicvf_reg_get_count();
196 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
198 uint64_t *data = regs->data;
199 struct nicvf *nic = nicvf_pmd_priv(dev);
204 /* Support only full register dump */
205 if ((regs->length == 0) ||
206 (regs->length == (uint32_t)nicvf_reg_get_count())) {
207 regs->version = nic->vendor_id << 16 | nic->device_id;
208 nicvf_reg_dump(nic, data);
214 static inline uint64_t
215 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
217 uint64_t nic_rss = 0;
219 if (ethdev_rss & ETH_RSS_IPV4)
220 nic_rss |= RSS_IP_ENA;
222 if (ethdev_rss & ETH_RSS_IPV6)
223 nic_rss |= RSS_IP_ENA;
225 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
226 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
228 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
229 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
231 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
232 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
234 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
235 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
237 if (ethdev_rss & ETH_RSS_PORT)
238 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
240 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
241 if (ethdev_rss & ETH_RSS_VXLAN)
242 nic_rss |= RSS_TUN_VXLAN_ENA;
244 if (ethdev_rss & ETH_RSS_GENEVE)
245 nic_rss |= RSS_TUN_GENEVE_ENA;
247 if (ethdev_rss & ETH_RSS_NVGRE)
248 nic_rss |= RSS_TUN_NVGRE_ENA;
254 static inline uint64_t
255 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
257 uint64_t ethdev_rss = 0;
259 if (nic_rss & RSS_IP_ENA)
260 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
262 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
263 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
264 ETH_RSS_NONFRAG_IPV6_TCP);
266 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
267 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
268 ETH_RSS_NONFRAG_IPV6_UDP);
270 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
271 ethdev_rss |= ETH_RSS_PORT;
273 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
274 if (nic_rss & RSS_TUN_VXLAN_ENA)
275 ethdev_rss |= ETH_RSS_VXLAN;
277 if (nic_rss & RSS_TUN_GENEVE_ENA)
278 ethdev_rss |= ETH_RSS_GENEVE;
280 if (nic_rss & RSS_TUN_NVGRE_ENA)
281 ethdev_rss |= ETH_RSS_NVGRE;
287 nicvf_dev_reta_query(struct rte_eth_dev *dev,
288 struct rte_eth_rss_reta_entry64 *reta_conf,
291 struct nicvf *nic = nicvf_pmd_priv(dev);
292 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
295 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
296 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
297 "(%d) doesn't match the number hardware can supported "
298 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
302 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
306 /* Copy RETA table */
307 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
308 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
309 if ((reta_conf[i].mask >> j) & 0x01)
310 reta_conf[i].reta[j] = tbl[j];
317 nicvf_dev_reta_update(struct rte_eth_dev *dev,
318 struct rte_eth_rss_reta_entry64 *reta_conf,
321 struct nicvf *nic = nicvf_pmd_priv(dev);
322 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
325 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
326 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
327 "(%d) doesn't match the number hardware can supported "
328 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
332 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
336 /* Copy RETA table */
337 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
338 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
339 if ((reta_conf[i].mask >> j) & 0x01)
340 tbl[j] = reta_conf[i].reta[j];
343 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
347 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
348 struct rte_eth_rss_conf *rss_conf)
350 struct nicvf *nic = nicvf_pmd_priv(dev);
352 if (rss_conf->rss_key)
353 nicvf_rss_get_key(nic, rss_conf->rss_key);
355 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
356 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
361 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
362 struct rte_eth_rss_conf *rss_conf)
364 struct nicvf *nic = nicvf_pmd_priv(dev);
367 if (rss_conf->rss_key &&
368 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
369 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
370 rss_conf->rss_key_len);
374 if (rss_conf->rss_key)
375 nicvf_rss_set_key(nic, rss_conf->rss_key);
377 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
378 nicvf_rss_set_cfg(nic, nic_rss);
383 nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,
386 const struct rte_memzone *rz;
387 uint32_t ring_size = desc_cnt * sizeof(union cq_entry_t);
389 rz = rte_eth_dma_zone_reserve(nic->eth_dev, "cq_ring", qidx, ring_size,
390 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
392 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
396 memset(rz->addr, 0, ring_size);
398 rxq->phys = rz->phys_addr;
399 rxq->desc = rz->addr;
400 rxq->qlen_mask = desc_cnt - 1;
406 nicvf_qset_sq_alloc(struct nicvf *nic, struct nicvf_txq *sq, uint16_t qidx,
409 const struct rte_memzone *rz;
410 uint32_t ring_size = desc_cnt * sizeof(union sq_entry_t);
412 rz = rte_eth_dma_zone_reserve(nic->eth_dev, "sq", qidx, ring_size,
413 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
415 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
419 memset(rz->addr, 0, ring_size);
421 sq->phys = rz->phys_addr;
423 sq->qlen_mask = desc_cnt - 1;
429 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
434 while (head != txq->tail) {
435 if (txq->txbuffs[head]) {
436 rte_pktmbuf_free_seg(txq->txbuffs[head]);
437 txq->txbuffs[head] = NULL;
440 head = head & txq->qlen_mask;
445 nicvf_tx_queue_reset(struct nicvf_txq *txq)
447 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
449 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
450 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
457 nicvf_dev_tx_queue_release(void *sq)
459 struct nicvf_txq *txq;
461 PMD_INIT_FUNC_TRACE();
463 txq = (struct nicvf_txq *)sq;
465 if (txq->txbuffs != NULL) {
466 nicvf_tx_queue_release_mbufs(txq);
467 rte_free(txq->txbuffs);
475 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
476 uint16_t nb_desc, unsigned int socket_id,
477 const struct rte_eth_txconf *tx_conf)
479 uint16_t tx_free_thresh;
480 uint8_t is_single_pool;
481 struct nicvf_txq *txq;
482 struct nicvf *nic = nicvf_pmd_priv(dev);
484 PMD_INIT_FUNC_TRACE();
486 /* Socket id check */
487 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
488 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
489 socket_id, nic->node);
491 /* Tx deferred start is not supported */
492 if (tx_conf->tx_deferred_start) {
493 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
497 /* Roundup nb_desc to available qsize and validate max number of desc */
498 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
500 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
504 /* Validate tx_free_thresh */
505 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
506 tx_conf->tx_free_thresh :
507 NICVF_DEFAULT_TX_FREE_THRESH);
509 if (tx_free_thresh > (nb_desc) ||
510 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
512 "tx_free_thresh must be less than the number of TX "
513 "descriptors. (tx_free_thresh=%u port=%d "
514 "queue=%d)", (unsigned int)tx_free_thresh,
515 (int)dev->data->port_id, (int)qidx);
519 /* Free memory prior to re-allocation if needed. */
520 if (dev->data->tx_queues[qidx] != NULL) {
521 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
523 nicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);
524 dev->data->tx_queues[qidx] = NULL;
527 /* Allocating tx queue data structure */
528 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
529 RTE_CACHE_LINE_SIZE, nic->node);
531 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", qidx);
536 txq->queue_id = qidx;
537 txq->tx_free_thresh = tx_free_thresh;
538 txq->txq_flags = tx_conf->txq_flags;
539 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
540 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
541 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
542 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
544 /* Choose optimum free threshold value for multipool case */
545 if (!is_single_pool) {
546 txq->tx_free_thresh = (uint16_t)
547 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
548 NICVF_TX_FREE_MPOOL_THRESH :
549 tx_conf->tx_free_thresh);
552 /* Allocate software ring */
553 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
554 nb_desc * sizeof(struct rte_mbuf *),
555 RTE_CACHE_LINE_SIZE, nic->node);
557 if (txq->txbuffs == NULL) {
558 nicvf_dev_tx_queue_release(txq);
562 if (nicvf_qset_sq_alloc(nic, txq, qidx, nb_desc)) {
563 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
564 nicvf_dev_tx_queue_release(txq);
568 nicvf_tx_queue_reset(txq);
570 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
571 qidx, txq, nb_desc, txq->desc, txq->phys);
573 dev->data->tx_queues[qidx] = txq;
574 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
579 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
582 rxq->available_space = 0;
583 rxq->recv_buffers = 0;
587 nicvf_dev_rx_queue_release(void *rx_queue)
589 struct nicvf_rxq *rxq = rx_queue;
591 PMD_INIT_FUNC_TRACE();
598 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
599 uint16_t nb_desc, unsigned int socket_id,
600 const struct rte_eth_rxconf *rx_conf,
601 struct rte_mempool *mp)
603 uint16_t rx_free_thresh;
604 struct nicvf_rxq *rxq;
605 struct nicvf *nic = nicvf_pmd_priv(dev);
607 PMD_INIT_FUNC_TRACE();
609 /* Socket id check */
610 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
611 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
612 socket_id, nic->node);
614 /* Mempool memory should be contiguous */
615 if (mp->nb_mem_chunks != 1) {
616 PMD_INIT_LOG(ERR, "Non contiguous mempool, check huge page sz");
620 /* Rx deferred start is not supported */
621 if (rx_conf->rx_deferred_start) {
622 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
626 /* Roundup nb_desc to available qsize and validate max number of desc */
627 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
629 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
633 /* Check rx_free_thresh upper bound */
634 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
635 rx_conf->rx_free_thresh :
636 NICVF_DEFAULT_RX_FREE_THRESH);
637 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
638 rx_free_thresh >= nb_desc * .75) {
639 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
644 /* Free memory prior to re-allocation if needed */
645 if (dev->data->rx_queues[qidx] != NULL) {
646 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
648 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]);
649 dev->data->rx_queues[qidx] = NULL;
652 /* Allocate rxq memory */
653 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
654 RTE_CACHE_LINE_SIZE, nic->node);
656 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx);
662 rxq->queue_id = qidx;
663 rxq->port_id = dev->data->port_id;
664 rxq->rx_free_thresh = rx_free_thresh;
665 rxq->rx_drop_en = rx_conf->rx_drop_en;
666 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
667 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
668 rxq->precharge_cnt = 0;
669 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
671 /* Alloc completion queue */
672 if (nicvf_qset_cq_alloc(nic, rxq, rxq->queue_id, nb_desc)) {
673 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
674 nicvf_dev_rx_queue_release(rxq);
678 nicvf_rx_queue_reset(rxq);
680 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
681 qidx, rxq, mp->name, nb_desc,
682 rte_mempool_count(mp), rxq->phys);
684 dev->data->rx_queues[qidx] = rxq;
685 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
690 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
692 struct nicvf *nic = nicvf_pmd_priv(dev);
694 PMD_INIT_FUNC_TRACE();
696 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
697 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
698 dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
699 dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
700 dev_info->max_mac_addrs = 1;
701 dev_info->max_vfs = dev->pci_dev->max_vfs;
703 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
704 dev_info->tx_offload_capa =
705 DEV_TX_OFFLOAD_IPV4_CKSUM |
706 DEV_TX_OFFLOAD_UDP_CKSUM |
707 DEV_TX_OFFLOAD_TCP_CKSUM |
708 DEV_TX_OFFLOAD_TCP_TSO |
709 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
711 dev_info->reta_size = nic->rss_info.rss_size;
712 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
713 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
714 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
715 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
717 dev_info->default_rxconf = (struct rte_eth_rxconf) {
718 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
722 dev_info->default_txconf = (struct rte_eth_txconf) {
723 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
725 ETH_TXQ_FLAGS_NOMULTSEGS |
726 ETH_TXQ_FLAGS_NOREFCOUNT |
727 ETH_TXQ_FLAGS_NOMULTMEMP |
728 ETH_TXQ_FLAGS_NOVLANOFFL |
729 ETH_TXQ_FLAGS_NOXSUMSCTP,
734 nicvf_dev_configure(struct rte_eth_dev *dev)
736 struct rte_eth_conf *conf = &dev->data->dev_conf;
737 struct rte_eth_rxmode *rxmode = &conf->rxmode;
738 struct rte_eth_txmode *txmode = &conf->txmode;
739 struct nicvf *nic = nicvf_pmd_priv(dev);
741 PMD_INIT_FUNC_TRACE();
743 if (!rte_eal_has_hugepages()) {
744 PMD_INIT_LOG(INFO, "Huge page is not configured");
748 if (txmode->mq_mode) {
749 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
753 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
754 rxmode->mq_mode != ETH_MQ_RX_RSS) {
755 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
759 if (!rxmode->hw_strip_crc) {
760 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
761 rxmode->hw_strip_crc = 1;
764 if (rxmode->hw_ip_checksum) {
765 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
766 rxmode->hw_ip_checksum = 0;
769 if (rxmode->split_hdr_size) {
770 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
774 if (rxmode->hw_vlan_filter) {
775 PMD_INIT_LOG(INFO, "VLAN filter not supported");
779 if (rxmode->hw_vlan_extend) {
780 PMD_INIT_LOG(INFO, "VLAN extended not supported");
784 if (rxmode->enable_lro) {
785 PMD_INIT_LOG(INFO, "LRO not supported");
789 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
790 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
794 if (conf->dcb_capability_en) {
795 PMD_INIT_LOG(INFO, "DCB enable not supported");
799 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
800 PMD_INIT_LOG(INFO, "Flow director not supported");
804 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
805 dev->data->port_id, nicvf_hw_cap(nic));
810 /* Initialize and register driver with DPDK Application */
811 static const struct eth_dev_ops nicvf_eth_dev_ops = {
812 .dev_configure = nicvf_dev_configure,
813 .link_update = nicvf_dev_link_update,
814 .dev_infos_get = nicvf_dev_info_get,
815 .mtu_set = nicvf_dev_set_mtu,
816 .reta_update = nicvf_dev_reta_update,
817 .reta_query = nicvf_dev_reta_query,
818 .rss_hash_update = nicvf_dev_rss_hash_update,
819 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
820 .rx_queue_setup = nicvf_dev_rx_queue_setup,
821 .rx_queue_release = nicvf_dev_rx_queue_release,
822 .tx_queue_setup = nicvf_dev_tx_queue_setup,
823 .tx_queue_release = nicvf_dev_tx_queue_release,
824 .get_reg_length = nicvf_dev_get_reg_length,
825 .get_reg = nicvf_dev_get_regs,
829 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
832 struct rte_pci_device *pci_dev;
833 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
835 PMD_INIT_FUNC_TRACE();
837 eth_dev->dev_ops = &nicvf_eth_dev_ops;
839 pci_dev = eth_dev->pci_dev;
840 rte_eth_copy_pci_info(eth_dev, pci_dev);
842 nic->device_id = pci_dev->id.device_id;
843 nic->vendor_id = pci_dev->id.vendor_id;
844 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
845 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
846 nic->eth_dev = eth_dev;
848 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
849 pci_dev->id.vendor_id, pci_dev->id.device_id,
850 pci_dev->addr.domain, pci_dev->addr.bus,
851 pci_dev->addr.devid, pci_dev->addr.function);
853 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
854 if (!nic->reg_base) {
855 PMD_INIT_LOG(ERR, "Failed to map BAR0");
860 nicvf_disable_all_interrupts(nic);
862 ret = nicvf_periodic_alarm_start(nic);
864 PMD_INIT_LOG(ERR, "Failed to start period alarm");
868 ret = nicvf_mbox_check_pf_ready(nic);
870 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
874 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
875 nic->node, nic->vf_id,
876 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
877 nic->sqs_mode ? "true" : "false",
878 nic->loopback_supported ? "true" : "false"
883 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
884 /* Detach port by returning Positive error number */
889 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
890 if (eth_dev->data->mac_addrs == NULL) {
891 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
895 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
896 eth_random_addr(&nic->mac_addr[0]);
898 ether_addr_copy((struct ether_addr *)nic->mac_addr,
899 ð_dev->data->mac_addrs[0]);
901 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
903 PMD_INIT_LOG(ERR, "Failed to set mac addr");
907 ret = nicvf_base_init(nic);
909 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
913 ret = nicvf_mbox_get_rss_size(nic);
915 PMD_INIT_LOG(ERR, "Failed to get rss table size");
919 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
920 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
921 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
922 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
927 rte_free(eth_dev->data->mac_addrs);
929 nicvf_periodic_alarm_stop(nic);
934 static const struct rte_pci_id pci_id_nicvf_map[] = {
936 .class_id = RTE_CLASS_ANY_ID,
937 .vendor_id = PCI_VENDOR_ID_CAVIUM,
938 .device_id = PCI_DEVICE_ID_THUNDERX_PASS1_NICVF,
939 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
940 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF,
943 .class_id = RTE_CLASS_ANY_ID,
944 .vendor_id = PCI_VENDOR_ID_CAVIUM,
945 .device_id = PCI_DEVICE_ID_THUNDERX_PASS2_NICVF,
946 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
947 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF,
954 static struct eth_driver rte_nicvf_pmd = {
956 .name = "rte_nicvf_pmd",
957 .id_table = pci_id_nicvf_map,
958 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
960 .eth_dev_init = nicvf_eth_dev_init,
961 .dev_private_size = sizeof(struct nicvf),
965 rte_nicvf_pmd_init(const char *name __rte_unused, const char *para __rte_unused)
967 PMD_INIT_FUNC_TRACE();
968 PMD_INIT_LOG(INFO, "librte_pmd_thunderx nicvf version %s",
969 THUNDERX_NICVF_PMD_VERSION);
971 rte_eth_driver_register(&rte_nicvf_pmd);
975 static struct rte_driver rte_nicvf_driver = {
976 .name = "nicvf_driver",
978 .init = rte_nicvf_pmd_init,
981 PMD_REGISTER_DRIVER(rte_nicvf_driver);