4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
44 #include <sys/timerfd.h>
46 #include <rte_alarm.h>
47 #include <rte_atomic.h>
48 #include <rte_branch_prediction.h>
49 #include <rte_byteorder.h>
50 #include <rte_common.h>
51 #include <rte_cycles.h>
52 #include <rte_debug.h>
55 #include <rte_ether.h>
56 #include <rte_ethdev.h>
57 #include <rte_interrupts.h>
59 #include <rte_memory.h>
60 #include <rte_memzone.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_tailq.h>
66 #include "base/nicvf_plat.h"
68 #include "nicvf_ethdev.h"
70 #include "nicvf_logs.h"
73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
74 struct rte_eth_link *link)
76 struct rte_eth_link *dst = &dev->data->dev_link;
77 struct rte_eth_link *src = link;
79 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
80 *(uint64_t *)src) == 0)
87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
89 link->link_status = nic->link_up;
90 link->link_duplex = ETH_LINK_AUTONEG;
91 if (nic->duplex == NICVF_HALF_DUPLEX)
92 link->link_duplex = ETH_LINK_HALF_DUPLEX;
93 else if (nic->duplex == NICVF_FULL_DUPLEX)
94 link->link_duplex = ETH_LINK_FULL_DUPLEX;
95 link->link_speed = nic->speed;
96 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
100 nicvf_interrupt(void *arg)
102 struct nicvf *nic = arg;
104 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
105 if (nic->eth_dev->data->dev_conf.intr_conf.lsc)
106 nicvf_set_eth_link_status(nic,
107 &nic->eth_dev->data->dev_link);
108 _rte_eth_dev_callback_process(nic->eth_dev,
109 RTE_ETH_EVENT_INTR_LSC);
112 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
113 nicvf_interrupt, nic);
117 nicvf_periodic_alarm_start(struct nicvf *nic)
119 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
120 nicvf_interrupt, nic);
124 nicvf_periodic_alarm_stop(struct nicvf *nic)
126 return rte_eal_alarm_cancel(nicvf_interrupt, nic);
130 * Return 0 means link status changed, -1 means not changed
133 nicvf_dev_link_update(struct rte_eth_dev *dev,
134 int wait_to_complete __rte_unused)
136 struct rte_eth_link link;
137 struct nicvf *nic = nicvf_pmd_priv(dev);
139 PMD_INIT_FUNC_TRACE();
141 memset(&link, 0, sizeof(link));
142 nicvf_set_eth_link_status(nic, &link);
143 return nicvf_atomic_write_link_status(dev, &link);
147 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
149 struct nicvf *nic = nicvf_pmd_priv(dev);
150 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
152 PMD_INIT_FUNC_TRACE();
154 if (frame_size > NIC_HW_MAX_FRS)
157 if (frame_size < NIC_HW_MIN_FRS)
160 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
163 * Refuse mtu that requires the support of scattered packets
164 * when this feature has not been enabled before.
166 if (!dev->data->scattered_rx &&
167 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
170 /* check <seg size> * <max_seg> >= max_frame */
171 if (dev->data->scattered_rx &&
172 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
175 if (frame_size > ETHER_MAX_LEN)
176 dev->data->dev_conf.rxmode.jumbo_frame = 1;
178 dev->data->dev_conf.rxmode.jumbo_frame = 0;
180 if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
183 /* Update max frame size */
184 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
190 nicvf_dev_get_reg_length(struct rte_eth_dev *dev __rte_unused)
192 return nicvf_reg_get_count();
196 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
198 uint64_t *data = regs->data;
199 struct nicvf *nic = nicvf_pmd_priv(dev);
204 /* Support only full register dump */
205 if ((regs->length == 0) ||
206 (regs->length == (uint32_t)nicvf_reg_get_count())) {
207 regs->version = nic->vendor_id << 16 | nic->device_id;
208 nicvf_reg_dump(nic, data);
214 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
216 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
220 static inline uint64_t
221 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
223 uint64_t nic_rss = 0;
225 if (ethdev_rss & ETH_RSS_IPV4)
226 nic_rss |= RSS_IP_ENA;
228 if (ethdev_rss & ETH_RSS_IPV6)
229 nic_rss |= RSS_IP_ENA;
231 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
232 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
234 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
235 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
237 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
238 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
240 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
241 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
243 if (ethdev_rss & ETH_RSS_PORT)
244 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
246 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
247 if (ethdev_rss & ETH_RSS_VXLAN)
248 nic_rss |= RSS_TUN_VXLAN_ENA;
250 if (ethdev_rss & ETH_RSS_GENEVE)
251 nic_rss |= RSS_TUN_GENEVE_ENA;
253 if (ethdev_rss & ETH_RSS_NVGRE)
254 nic_rss |= RSS_TUN_NVGRE_ENA;
260 static inline uint64_t
261 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
263 uint64_t ethdev_rss = 0;
265 if (nic_rss & RSS_IP_ENA)
266 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
268 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
269 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
270 ETH_RSS_NONFRAG_IPV6_TCP);
272 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
273 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
274 ETH_RSS_NONFRAG_IPV6_UDP);
276 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
277 ethdev_rss |= ETH_RSS_PORT;
279 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
280 if (nic_rss & RSS_TUN_VXLAN_ENA)
281 ethdev_rss |= ETH_RSS_VXLAN;
283 if (nic_rss & RSS_TUN_GENEVE_ENA)
284 ethdev_rss |= ETH_RSS_GENEVE;
286 if (nic_rss & RSS_TUN_NVGRE_ENA)
287 ethdev_rss |= ETH_RSS_NVGRE;
293 nicvf_dev_reta_query(struct rte_eth_dev *dev,
294 struct rte_eth_rss_reta_entry64 *reta_conf,
297 struct nicvf *nic = nicvf_pmd_priv(dev);
298 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
301 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
302 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
303 "(%d) doesn't match the number hardware can supported "
304 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
308 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
312 /* Copy RETA table */
313 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
314 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
315 if ((reta_conf[i].mask >> j) & 0x01)
316 reta_conf[i].reta[j] = tbl[j];
323 nicvf_dev_reta_update(struct rte_eth_dev *dev,
324 struct rte_eth_rss_reta_entry64 *reta_conf,
327 struct nicvf *nic = nicvf_pmd_priv(dev);
328 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
331 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
332 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
333 "(%d) doesn't match the number hardware can supported "
334 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
338 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
342 /* Copy RETA table */
343 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
344 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
345 if ((reta_conf[i].mask >> j) & 0x01)
346 tbl[j] = reta_conf[i].reta[j];
349 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
353 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
354 struct rte_eth_rss_conf *rss_conf)
356 struct nicvf *nic = nicvf_pmd_priv(dev);
358 if (rss_conf->rss_key)
359 nicvf_rss_get_key(nic, rss_conf->rss_key);
361 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
362 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
367 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
368 struct rte_eth_rss_conf *rss_conf)
370 struct nicvf *nic = nicvf_pmd_priv(dev);
373 if (rss_conf->rss_key &&
374 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
375 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
376 rss_conf->rss_key_len);
380 if (rss_conf->rss_key)
381 nicvf_rss_set_key(nic, rss_conf->rss_key);
383 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
384 nicvf_rss_set_cfg(nic, nic_rss);
389 nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,
392 const struct rte_memzone *rz;
393 uint32_t ring_size = desc_cnt * sizeof(union cq_entry_t);
395 rz = rte_eth_dma_zone_reserve(nic->eth_dev, "cq_ring", qidx, ring_size,
396 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
398 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
402 memset(rz->addr, 0, ring_size);
404 rxq->phys = rz->phys_addr;
405 rxq->desc = rz->addr;
406 rxq->qlen_mask = desc_cnt - 1;
412 nicvf_qset_sq_alloc(struct nicvf *nic, struct nicvf_txq *sq, uint16_t qidx,
415 const struct rte_memzone *rz;
416 uint32_t ring_size = desc_cnt * sizeof(union sq_entry_t);
418 rz = rte_eth_dma_zone_reserve(nic->eth_dev, "sq", qidx, ring_size,
419 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
421 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
425 memset(rz->addr, 0, ring_size);
427 sq->phys = rz->phys_addr;
429 sq->qlen_mask = desc_cnt - 1;
435 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
440 while (head != txq->tail) {
441 if (txq->txbuffs[head]) {
442 rte_pktmbuf_free_seg(txq->txbuffs[head]);
443 txq->txbuffs[head] = NULL;
446 head = head & txq->qlen_mask;
451 nicvf_tx_queue_reset(struct nicvf_txq *txq)
453 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
455 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
456 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
463 nicvf_dev_tx_queue_release(void *sq)
465 struct nicvf_txq *txq;
467 PMD_INIT_FUNC_TRACE();
469 txq = (struct nicvf_txq *)sq;
471 if (txq->txbuffs != NULL) {
472 nicvf_tx_queue_release_mbufs(txq);
473 rte_free(txq->txbuffs);
481 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
482 uint16_t nb_desc, unsigned int socket_id,
483 const struct rte_eth_txconf *tx_conf)
485 uint16_t tx_free_thresh;
486 uint8_t is_single_pool;
487 struct nicvf_txq *txq;
488 struct nicvf *nic = nicvf_pmd_priv(dev);
490 PMD_INIT_FUNC_TRACE();
492 /* Socket id check */
493 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
494 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
495 socket_id, nic->node);
497 /* Tx deferred start is not supported */
498 if (tx_conf->tx_deferred_start) {
499 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
503 /* Roundup nb_desc to available qsize and validate max number of desc */
504 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
506 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
510 /* Validate tx_free_thresh */
511 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
512 tx_conf->tx_free_thresh :
513 NICVF_DEFAULT_TX_FREE_THRESH);
515 if (tx_free_thresh > (nb_desc) ||
516 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
518 "tx_free_thresh must be less than the number of TX "
519 "descriptors. (tx_free_thresh=%u port=%d "
520 "queue=%d)", (unsigned int)tx_free_thresh,
521 (int)dev->data->port_id, (int)qidx);
525 /* Free memory prior to re-allocation if needed. */
526 if (dev->data->tx_queues[qidx] != NULL) {
527 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
529 nicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);
530 dev->data->tx_queues[qidx] = NULL;
533 /* Allocating tx queue data structure */
534 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
535 RTE_CACHE_LINE_SIZE, nic->node);
537 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", qidx);
542 txq->queue_id = qidx;
543 txq->tx_free_thresh = tx_free_thresh;
544 txq->txq_flags = tx_conf->txq_flags;
545 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
546 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
547 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
548 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
550 /* Choose optimum free threshold value for multipool case */
551 if (!is_single_pool) {
552 txq->tx_free_thresh = (uint16_t)
553 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
554 NICVF_TX_FREE_MPOOL_THRESH :
555 tx_conf->tx_free_thresh);
558 /* Allocate software ring */
559 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
560 nb_desc * sizeof(struct rte_mbuf *),
561 RTE_CACHE_LINE_SIZE, nic->node);
563 if (txq->txbuffs == NULL) {
564 nicvf_dev_tx_queue_release(txq);
568 if (nicvf_qset_sq_alloc(nic, txq, qidx, nb_desc)) {
569 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
570 nicvf_dev_tx_queue_release(txq);
574 nicvf_tx_queue_reset(txq);
576 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
577 qidx, txq, nb_desc, txq->desc, txq->phys);
579 dev->data->tx_queues[qidx] = txq;
580 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
585 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
588 rxq->available_space = 0;
589 rxq->recv_buffers = 0;
593 nicvf_dev_rx_queue_release(void *rx_queue)
595 struct nicvf_rxq *rxq = rx_queue;
597 PMD_INIT_FUNC_TRACE();
604 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
605 uint16_t nb_desc, unsigned int socket_id,
606 const struct rte_eth_rxconf *rx_conf,
607 struct rte_mempool *mp)
609 uint16_t rx_free_thresh;
610 struct nicvf_rxq *rxq;
611 struct nicvf *nic = nicvf_pmd_priv(dev);
613 PMD_INIT_FUNC_TRACE();
615 /* Socket id check */
616 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
617 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
618 socket_id, nic->node);
620 /* Mempool memory should be contiguous */
621 if (mp->nb_mem_chunks != 1) {
622 PMD_INIT_LOG(ERR, "Non contiguous mempool, check huge page sz");
626 /* Rx deferred start is not supported */
627 if (rx_conf->rx_deferred_start) {
628 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
632 /* Roundup nb_desc to available qsize and validate max number of desc */
633 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
635 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
639 /* Check rx_free_thresh upper bound */
640 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
641 rx_conf->rx_free_thresh :
642 NICVF_DEFAULT_RX_FREE_THRESH);
643 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
644 rx_free_thresh >= nb_desc * .75) {
645 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
650 /* Free memory prior to re-allocation if needed */
651 if (dev->data->rx_queues[qidx] != NULL) {
652 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
654 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]);
655 dev->data->rx_queues[qidx] = NULL;
658 /* Allocate rxq memory */
659 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
660 RTE_CACHE_LINE_SIZE, nic->node);
662 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx);
668 rxq->queue_id = qidx;
669 rxq->port_id = dev->data->port_id;
670 rxq->rx_free_thresh = rx_free_thresh;
671 rxq->rx_drop_en = rx_conf->rx_drop_en;
672 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
673 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
674 rxq->precharge_cnt = 0;
675 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
677 /* Alloc completion queue */
678 if (nicvf_qset_cq_alloc(nic, rxq, rxq->queue_id, nb_desc)) {
679 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
680 nicvf_dev_rx_queue_release(rxq);
684 nicvf_rx_queue_reset(rxq);
686 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
687 qidx, rxq, mp->name, nb_desc,
688 rte_mempool_count(mp), rxq->phys);
690 dev->data->rx_queues[qidx] = rxq;
691 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
696 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
698 struct nicvf *nic = nicvf_pmd_priv(dev);
700 PMD_INIT_FUNC_TRACE();
702 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
703 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
704 dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
705 dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
706 dev_info->max_mac_addrs = 1;
707 dev_info->max_vfs = dev->pci_dev->max_vfs;
709 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
710 dev_info->tx_offload_capa =
711 DEV_TX_OFFLOAD_IPV4_CKSUM |
712 DEV_TX_OFFLOAD_UDP_CKSUM |
713 DEV_TX_OFFLOAD_TCP_CKSUM |
714 DEV_TX_OFFLOAD_TCP_TSO |
715 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
717 dev_info->reta_size = nic->rss_info.rss_size;
718 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
719 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
720 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
721 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
723 dev_info->default_rxconf = (struct rte_eth_rxconf) {
724 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
728 dev_info->default_txconf = (struct rte_eth_txconf) {
729 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
731 ETH_TXQ_FLAGS_NOMULTSEGS |
732 ETH_TXQ_FLAGS_NOREFCOUNT |
733 ETH_TXQ_FLAGS_NOMULTMEMP |
734 ETH_TXQ_FLAGS_NOVLANOFFL |
735 ETH_TXQ_FLAGS_NOXSUMSCTP,
740 nicvf_dev_configure(struct rte_eth_dev *dev)
742 struct rte_eth_conf *conf = &dev->data->dev_conf;
743 struct rte_eth_rxmode *rxmode = &conf->rxmode;
744 struct rte_eth_txmode *txmode = &conf->txmode;
745 struct nicvf *nic = nicvf_pmd_priv(dev);
747 PMD_INIT_FUNC_TRACE();
749 if (!rte_eal_has_hugepages()) {
750 PMD_INIT_LOG(INFO, "Huge page is not configured");
754 if (txmode->mq_mode) {
755 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
759 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
760 rxmode->mq_mode != ETH_MQ_RX_RSS) {
761 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
765 if (!rxmode->hw_strip_crc) {
766 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
767 rxmode->hw_strip_crc = 1;
770 if (rxmode->hw_ip_checksum) {
771 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
772 rxmode->hw_ip_checksum = 0;
775 if (rxmode->split_hdr_size) {
776 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
780 if (rxmode->hw_vlan_filter) {
781 PMD_INIT_LOG(INFO, "VLAN filter not supported");
785 if (rxmode->hw_vlan_extend) {
786 PMD_INIT_LOG(INFO, "VLAN extended not supported");
790 if (rxmode->enable_lro) {
791 PMD_INIT_LOG(INFO, "LRO not supported");
795 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
796 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
800 if (conf->dcb_capability_en) {
801 PMD_INIT_LOG(INFO, "DCB enable not supported");
805 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
806 PMD_INIT_LOG(INFO, "Flow director not supported");
810 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
811 dev->data->port_id, nicvf_hw_cap(nic));
816 /* Initialize and register driver with DPDK Application */
817 static const struct eth_dev_ops nicvf_eth_dev_ops = {
818 .dev_configure = nicvf_dev_configure,
819 .link_update = nicvf_dev_link_update,
820 .promiscuous_enable = nicvf_dev_promisc_enable,
821 .dev_infos_get = nicvf_dev_info_get,
822 .mtu_set = nicvf_dev_set_mtu,
823 .reta_update = nicvf_dev_reta_update,
824 .reta_query = nicvf_dev_reta_query,
825 .rss_hash_update = nicvf_dev_rss_hash_update,
826 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
827 .rx_queue_setup = nicvf_dev_rx_queue_setup,
828 .rx_queue_release = nicvf_dev_rx_queue_release,
829 .tx_queue_setup = nicvf_dev_tx_queue_setup,
830 .tx_queue_release = nicvf_dev_tx_queue_release,
831 .get_reg_length = nicvf_dev_get_reg_length,
832 .get_reg = nicvf_dev_get_regs,
836 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
839 struct rte_pci_device *pci_dev;
840 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
842 PMD_INIT_FUNC_TRACE();
844 eth_dev->dev_ops = &nicvf_eth_dev_ops;
846 pci_dev = eth_dev->pci_dev;
847 rte_eth_copy_pci_info(eth_dev, pci_dev);
849 nic->device_id = pci_dev->id.device_id;
850 nic->vendor_id = pci_dev->id.vendor_id;
851 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
852 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
853 nic->eth_dev = eth_dev;
855 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
856 pci_dev->id.vendor_id, pci_dev->id.device_id,
857 pci_dev->addr.domain, pci_dev->addr.bus,
858 pci_dev->addr.devid, pci_dev->addr.function);
860 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
861 if (!nic->reg_base) {
862 PMD_INIT_LOG(ERR, "Failed to map BAR0");
867 nicvf_disable_all_interrupts(nic);
869 ret = nicvf_periodic_alarm_start(nic);
871 PMD_INIT_LOG(ERR, "Failed to start period alarm");
875 ret = nicvf_mbox_check_pf_ready(nic);
877 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
881 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
882 nic->node, nic->vf_id,
883 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
884 nic->sqs_mode ? "true" : "false",
885 nic->loopback_supported ? "true" : "false"
890 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
891 /* Detach port by returning Positive error number */
896 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
897 if (eth_dev->data->mac_addrs == NULL) {
898 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
902 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
903 eth_random_addr(&nic->mac_addr[0]);
905 ether_addr_copy((struct ether_addr *)nic->mac_addr,
906 ð_dev->data->mac_addrs[0]);
908 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
910 PMD_INIT_LOG(ERR, "Failed to set mac addr");
914 ret = nicvf_base_init(nic);
916 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
920 ret = nicvf_mbox_get_rss_size(nic);
922 PMD_INIT_LOG(ERR, "Failed to get rss table size");
926 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
927 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
928 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
929 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
934 rte_free(eth_dev->data->mac_addrs);
936 nicvf_periodic_alarm_stop(nic);
941 static const struct rte_pci_id pci_id_nicvf_map[] = {
943 .class_id = RTE_CLASS_ANY_ID,
944 .vendor_id = PCI_VENDOR_ID_CAVIUM,
945 .device_id = PCI_DEVICE_ID_THUNDERX_PASS1_NICVF,
946 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
947 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF,
950 .class_id = RTE_CLASS_ANY_ID,
951 .vendor_id = PCI_VENDOR_ID_CAVIUM,
952 .device_id = PCI_DEVICE_ID_THUNDERX_PASS2_NICVF,
953 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
954 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF,
961 static struct eth_driver rte_nicvf_pmd = {
963 .name = "rte_nicvf_pmd",
964 .id_table = pci_id_nicvf_map,
965 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
967 .eth_dev_init = nicvf_eth_dev_init,
968 .dev_private_size = sizeof(struct nicvf),
972 rte_nicvf_pmd_init(const char *name __rte_unused, const char *para __rte_unused)
974 PMD_INIT_FUNC_TRACE();
975 PMD_INIT_LOG(INFO, "librte_pmd_thunderx nicvf version %s",
976 THUNDERX_NICVF_PMD_VERSION);
978 rte_eth_driver_register(&rte_nicvf_pmd);
982 static struct rte_driver rte_nicvf_driver = {
983 .name = "nicvf_driver",
985 .init = rte_nicvf_pmd_init,
988 PMD_REGISTER_DRIVER(rte_nicvf_driver);