drivers/net/thunderx/nicvf_ethdev.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <assert.h>
  34 #include <stdio.h>
  35 #include <stdbool.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <sys/queue.h>
  44 #include <sys/timerfd.h>
  45
  46 #include <rte_alarm.h>
  47 #include <rte_atomic.h>
  48 #include <rte_branch_prediction.h>
  49 #include <rte_byteorder.h>
  50 #include <rte_common.h>
  51 #include <rte_cycles.h>
  52 #include <rte_debug.h>
  53 #include <rte_dev.h>
  54 #include <rte_eal.h>
  55 #include <rte_ether.h>
  56 #include <rte_ethdev.h>
  57 #include <rte_interrupts.h>
  58 #include <rte_log.h>
  59 #include <rte_memory.h>
  60 #include <rte_memzone.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_pci.h>
  64 #include <rte_tailq.h>
  65
  66 #include "base/nicvf_plat.h"
  67
  68 #include "nicvf_ethdev.h"
  69 #include "nicvf_rxtx.h"
  70 #include "nicvf_logs.h"
  71
  72 static void nicvf_dev_stop(struct rte_eth_dev *dev);
  73
  74 static inline int
  75 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
  76                                struct rte_eth_link *link)
  77 {
  78         struct rte_eth_link *dst = &dev->data->dev_link;
  79         struct rte_eth_link *src = link;
  80
  81         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
  82                 *(uint64_t *)src) == 0)
  83                 return -1;
  84
  85         return 0;
  86 }
  87
  88 static inline void
  89 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
  90 {
  91         link->link_status = nic->link_up;
  92         link->link_duplex = ETH_LINK_AUTONEG;
  93         if (nic->duplex == NICVF_HALF_DUPLEX)
  94                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  95         else if (nic->duplex == NICVF_FULL_DUPLEX)
  96                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
  97         link->link_speed = nic->speed;
  98         link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
  99 }
 100
 101 static void
 102 nicvf_interrupt(void *arg)
 103 {
 104         struct nicvf *nic = arg;
 105
 106         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
 107                 if (nic->eth_dev->data->dev_conf.intr_conf.lsc)
 108                         nicvf_set_eth_link_status(nic,
 109                                         &nic->eth_dev->data->dev_link);
 110                 _rte_eth_dev_callback_process(nic->eth_dev,
 111                                 RTE_ETH_EVENT_INTR_LSC);
 112         }
 113
 114         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 115                                 nicvf_interrupt, nic);
 116 }
 117
 118 static int
 119 nicvf_periodic_alarm_start(struct nicvf *nic)
 120 {
 121         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 122                                         nicvf_interrupt, nic);
 123 }
 124
 125 static int
 126 nicvf_periodic_alarm_stop(struct nicvf *nic)
 127 {
 128         return rte_eal_alarm_cancel(nicvf_interrupt, nic);
 129 }
 130
 131 /*
 132  * Return 0 means link status changed, -1 means not changed
 133  */
 134 static int
 135 nicvf_dev_link_update(struct rte_eth_dev *dev,
 136                       int wait_to_complete __rte_unused)
 137 {
 138         struct rte_eth_link link;
 139         struct nicvf *nic = nicvf_pmd_priv(dev);
 140
 141         PMD_INIT_FUNC_TRACE();
 142
 143         memset(&link, 0, sizeof(link));
 144         nicvf_set_eth_link_status(nic, &link);
 145         return nicvf_atomic_write_link_status(dev, &link);
 146 }
 147
 148 static int
 149 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 150 {
 151         struct nicvf *nic = nicvf_pmd_priv(dev);
 152         uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 153
 154         PMD_INIT_FUNC_TRACE();
 155
 156         if (frame_size > NIC_HW_MAX_FRS)
 157                 return -EINVAL;
 158
 159         if (frame_size < NIC_HW_MIN_FRS)
 160                 return -EINVAL;
 161
 162         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 163
 164         /*
 165          * Refuse mtu that requires the support of scattered packets
 166          * when this feature has not been enabled before.
 167          */
 168         if (!dev->data->scattered_rx &&
 169                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 170                 return -EINVAL;
 171
 172         /* check <seg size> * <max_seg>  >= max_frame */
 173         if (dev->data->scattered_rx &&
 174                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 175                 return -EINVAL;
 176
 177         if (frame_size > ETHER_MAX_LEN)
 178                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 179         else
 180                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 181
 182         if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
 183                 return -EINVAL;
 184
 185         /* Update max frame size */
 186         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
 187         nic->mtu = mtu;
 188         return 0;
 189 }
 190
 191 static int
 192 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 193 {
 194         uint64_t *data = regs->data;
 195         struct nicvf *nic = nicvf_pmd_priv(dev);
 196
 197         if (data == NULL) {
 198                 regs->length = nicvf_reg_get_count();
 199                 regs->width = THUNDERX_REG_BYTES;
 200                 return 0;
 201         }
 202
 203         /* Support only full register dump */
 204         if ((regs->length == 0) ||
 205                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 206                 regs->version = nic->vendor_id << 16 | nic->device_id;
 207                 nicvf_reg_dump(nic, data);
 208                 return 0;
 209         }
 210         return -ENOTSUP;
 211 }
 212
 213 static void
 214 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 215 {
 216         uint16_t qidx;
 217         struct nicvf_hw_rx_qstats rx_qstats;
 218         struct nicvf_hw_tx_qstats tx_qstats;
 219         struct nicvf_hw_stats port_stats;
 220         struct nicvf *nic = nicvf_pmd_priv(dev);
 221
 222         /* Reading per RX ring stats */
 223         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
 224                 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 225                         break;
 226
 227                 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
 228                 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 229                 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 230         }
 231
 232         /* Reading per TX ring stats */
 233         for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++) {
 234                 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 235                         break;
 236
 237                 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
 238                 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 239                 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 240         }
 241
 242         nicvf_hw_get_stats(nic, &port_stats);
 243         stats->ibytes = port_stats.rx_bytes;
 244         stats->ipackets = port_stats.rx_ucast_frames;
 245         stats->ipackets += port_stats.rx_bcast_frames;
 246         stats->ipackets += port_stats.rx_mcast_frames;
 247         stats->ierrors = port_stats.rx_l2_errors;
 248         stats->imissed = port_stats.rx_drop_red;
 249         stats->imissed += port_stats.rx_drop_overrun;
 250         stats->imissed += port_stats.rx_drop_bcast;
 251         stats->imissed += port_stats.rx_drop_mcast;
 252         stats->imissed += port_stats.rx_drop_l3_bcast;
 253         stats->imissed += port_stats.rx_drop_l3_mcast;
 254
 255         stats->obytes = port_stats.tx_bytes_ok;
 256         stats->opackets = port_stats.tx_ucast_frames_ok;
 257         stats->opackets += port_stats.tx_bcast_frames_ok;
 258         stats->opackets += port_stats.tx_mcast_frames_ok;
 259         stats->oerrors = port_stats.tx_drops;
 260 }
 261
 262 static const uint32_t *
 263 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 264 {
 265         size_t copied;
 266         static uint32_t ptypes[32];
 267         struct nicvf *nic = nicvf_pmd_priv(dev);
 268         static const uint32_t ptypes_common[] = {
 269                 RTE_PTYPE_L3_IPV4,
 270                 RTE_PTYPE_L3_IPV4_EXT,
 271                 RTE_PTYPE_L3_IPV6,
 272                 RTE_PTYPE_L3_IPV6_EXT,
 273                 RTE_PTYPE_L4_TCP,
 274                 RTE_PTYPE_L4_UDP,
 275                 RTE_PTYPE_L4_FRAG,
 276         };
 277         static const uint32_t ptypes_tunnel[] = {
 278                 RTE_PTYPE_TUNNEL_GRE,
 279                 RTE_PTYPE_TUNNEL_GENEVE,
 280                 RTE_PTYPE_TUNNEL_VXLAN,
 281                 RTE_PTYPE_TUNNEL_NVGRE,
 282         };
 283         static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
 284
 285         copied = sizeof(ptypes_common);
 286         memcpy(ptypes, ptypes_common, copied);
 287         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 288                 memcpy((char *)ptypes + copied, ptypes_tunnel,
 289                         sizeof(ptypes_tunnel));
 290                 copied += sizeof(ptypes_tunnel);
 291         }
 292
 293         memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
 294         if (dev->rx_pkt_burst == nicvf_recv_pkts ||
 295                 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
 296                 return ptypes;
 297
 298         return NULL;
 299 }
 300
 301 static void
 302 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
 303 {
 304         int i;
 305         uint16_t rxqs = 0, txqs = 0;
 306         struct nicvf *nic = nicvf_pmd_priv(dev);
 307
 308         for (i = 0; i < dev->data->nb_rx_queues; i++)
 309                 rxqs |= (0x3 << (i * 2));
 310         for (i = 0; i < dev->data->nb_tx_queues; i++)
 311                 txqs |= (0x3 << (i * 2));
 312
 313         nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
 314 }
 315
 316 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 317 static void
 318 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 319 {
 320 }
 321
 322 static inline uint64_t
 323 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 324 {
 325         uint64_t nic_rss = 0;
 326
 327         if (ethdev_rss & ETH_RSS_IPV4)
 328                 nic_rss |= RSS_IP_ENA;
 329
 330         if (ethdev_rss & ETH_RSS_IPV6)
 331                 nic_rss |= RSS_IP_ENA;
 332
 333         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 334                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 335
 336         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 337                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 338
 339         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 340                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 341
 342         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 343                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 344
 345         if (ethdev_rss & ETH_RSS_PORT)
 346                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 347
 348         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 349                 if (ethdev_rss & ETH_RSS_VXLAN)
 350                         nic_rss |= RSS_TUN_VXLAN_ENA;
 351
 352                 if (ethdev_rss & ETH_RSS_GENEVE)
 353                         nic_rss |= RSS_TUN_GENEVE_ENA;
 354
 355                 if (ethdev_rss & ETH_RSS_NVGRE)
 356                         nic_rss |= RSS_TUN_NVGRE_ENA;
 357         }
 358
 359         return nic_rss;
 360 }
 361
 362 static inline uint64_t
 363 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 364 {
 365         uint64_t ethdev_rss = 0;
 366
 367         if (nic_rss & RSS_IP_ENA)
 368                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 369
 370         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 371                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 372                                 ETH_RSS_NONFRAG_IPV6_TCP);
 373
 374         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 375                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 376                                 ETH_RSS_NONFRAG_IPV6_UDP);
 377
 378         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 379                 ethdev_rss |= ETH_RSS_PORT;
 380
 381         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 382                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 383                         ethdev_rss |= ETH_RSS_VXLAN;
 384
 385                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 386                         ethdev_rss |= ETH_RSS_GENEVE;
 387
 388                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 389                         ethdev_rss |= ETH_RSS_NVGRE;
 390         }
 391         return ethdev_rss;
 392 }
 393
 394 static int
 395 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 396                      struct rte_eth_rss_reta_entry64 *reta_conf,
 397                      uint16_t reta_size)
 398 {
 399         struct nicvf *nic = nicvf_pmd_priv(dev);
 400         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 401         int ret, i, j;
 402
 403         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 404                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 405                         "(%d) doesn't match the number hardware can supported "
 406                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 407                 return -EINVAL;
 408         }
 409
 410         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 411         if (ret)
 412                 return ret;
 413
 414         /* Copy RETA table */
 415         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 416                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 417                         if ((reta_conf[i].mask >> j) & 0x01)
 418                                 reta_conf[i].reta[j] = tbl[j];
 419         }
 420
 421         return 0;
 422 }
 423
 424 static int
 425 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 426                       struct rte_eth_rss_reta_entry64 *reta_conf,
 427                       uint16_t reta_size)
 428 {
 429         struct nicvf *nic = nicvf_pmd_priv(dev);
 430         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 431         int ret, i, j;
 432
 433         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 434                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 435                         "(%d) doesn't match the number hardware can supported "
 436                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 437                 return -EINVAL;
 438         }
 439
 440         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 441         if (ret)
 442                 return ret;
 443
 444         /* Copy RETA table */
 445         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 446                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 447                         if ((reta_conf[i].mask >> j) & 0x01)
 448                                 tbl[j] = reta_conf[i].reta[j];
 449         }
 450
 451         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 452 }
 453
 454 static int
 455 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 456                             struct rte_eth_rss_conf *rss_conf)
 457 {
 458         struct nicvf *nic = nicvf_pmd_priv(dev);
 459
 460         if (rss_conf->rss_key)
 461                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 462
 463         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 464         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 465         return 0;
 466 }
 467
 468 static int
 469 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 470                           struct rte_eth_rss_conf *rss_conf)
 471 {
 472         struct nicvf *nic = nicvf_pmd_priv(dev);
 473         uint64_t nic_rss;
 474
 475         if (rss_conf->rss_key &&
 476                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 477                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 478                                 rss_conf->rss_key_len);
 479                 return -EINVAL;
 480         }
 481
 482         if (rss_conf->rss_key)
 483                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 484
 485         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 486         nicvf_rss_set_cfg(nic, nic_rss);
 487         return 0;
 488 }
 489
 490 static int
 491 nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,
 492                     uint32_t desc_cnt)
 493 {
 494         const struct rte_memzone *rz;
 495         uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
 496
 497         rz = rte_eth_dma_zone_reserve(nic->eth_dev, "cq_ring", qidx, ring_size,
 498                                         NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 499         if (rz == NULL) {
 500                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 501                 return -ENOMEM;
 502         }
 503
 504         memset(rz->addr, 0, ring_size);
 505
 506         rxq->phys = rz->phys_addr;
 507         rxq->desc = rz->addr;
 508         rxq->qlen_mask = desc_cnt - 1;
 509
 510         return 0;
 511 }
 512
 513 static int
 514 nicvf_qset_sq_alloc(struct nicvf *nic,  struct nicvf_txq *sq, uint16_t qidx,
 515                     uint32_t desc_cnt)
 516 {
 517         const struct rte_memzone *rz;
 518         uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
 519
 520         rz = rte_eth_dma_zone_reserve(nic->eth_dev, "sq", qidx, ring_size,
 521                                 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 522         if (rz == NULL) {
 523                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 524                 return -ENOMEM;
 525         }
 526
 527         memset(rz->addr, 0, ring_size);
 528
 529         sq->phys = rz->phys_addr;
 530         sq->desc = rz->addr;
 531         sq->qlen_mask = desc_cnt - 1;
 532
 533         return 0;
 534 }
 535
 536 static int
 537 nicvf_qset_rbdr_alloc(struct nicvf *nic, uint32_t desc_cnt, uint32_t buffsz)
 538 {
 539         struct nicvf_rbdr *rbdr;
 540         const struct rte_memzone *rz;
 541         uint32_t ring_size;
 542
 543         assert(nic->rbdr == NULL);
 544         rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
 545                                   RTE_CACHE_LINE_SIZE, nic->node);
 546         if (rbdr == NULL) {
 547                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
 548                 return -ENOMEM;
 549         }
 550
 551         ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
 552         rz = rte_eth_dma_zone_reserve(nic->eth_dev, "rbdr", 0, ring_size,
 553                                    NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
 554         if (rz == NULL) {
 555                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
 556                 return -ENOMEM;
 557         }
 558
 559         memset(rz->addr, 0, ring_size);
 560
 561         rbdr->phys = rz->phys_addr;
 562         rbdr->tail = 0;
 563         rbdr->next_tail = 0;
 564         rbdr->desc = rz->addr;
 565         rbdr->buffsz = buffsz;
 566         rbdr->qlen_mask = desc_cnt - 1;
 567         rbdr->rbdr_status =
 568                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
 569         rbdr->rbdr_door =
 570                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
 571
 572         nic->rbdr = rbdr;
 573         return 0;
 574 }
 575
 576 static void
 577 nicvf_rbdr_release_mbuf(struct nicvf *nic, nicvf_phys_addr_t phy)
 578 {
 579         uint16_t qidx;
 580         void *obj;
 581         struct nicvf_rxq *rxq;
 582
 583         for (qidx = 0; qidx < nic->eth_dev->data->nb_rx_queues; qidx++) {
 584                 rxq = nic->eth_dev->data->rx_queues[qidx];
 585                 if (rxq->precharge_cnt) {
 586                         obj = (void *)nicvf_mbuff_phy2virt(phy,
 587                                                            rxq->mbuf_phys_off);
 588                         rte_mempool_put(rxq->pool, obj);
 589                         rxq->precharge_cnt--;
 590                         break;
 591                 }
 592         }
 593 }
 594
 595 static inline void
 596 nicvf_rbdr_release_mbufs(struct nicvf *nic)
 597 {
 598         uint32_t qlen_mask, head;
 599         struct rbdr_entry_t *entry;
 600         struct nicvf_rbdr *rbdr = nic->rbdr;
 601
 602         qlen_mask = rbdr->qlen_mask;
 603         head = rbdr->head;
 604         while (head != rbdr->tail) {
 605                 entry = rbdr->desc + head;
 606                 nicvf_rbdr_release_mbuf(nic, entry->full_addr);
 607                 head++;
 608                 head = head & qlen_mask;
 609         }
 610 }
 611
 612 static inline void
 613 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 614 {
 615         uint32_t head;
 616
 617         head = txq->head;
 618         while (head != txq->tail) {
 619                 if (txq->txbuffs[head]) {
 620                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 621                         txq->txbuffs[head] = NULL;
 622                 }
 623                 head++;
 624                 head = head & txq->qlen_mask;
 625         }
 626 }
 627
 628 static void
 629 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 630 {
 631         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 632
 633         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 634         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 635         txq->tail = 0;
 636         txq->head = 0;
 637         txq->xmit_bufs = 0;
 638 }
 639
 640 static inline int
 641 nicvf_start_tx_queue(struct rte_eth_dev *dev, uint16_t qidx)
 642 {
 643         struct nicvf_txq *txq;
 644         int ret;
 645
 646         if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
 647                 return 0;
 648
 649         txq = dev->data->tx_queues[qidx];
 650         txq->pool = NULL;
 651         ret = nicvf_qset_sq_config(nicvf_pmd_priv(dev), qidx, txq);
 652         if (ret) {
 653                 PMD_INIT_LOG(ERR, "Failed to configure sq %d %d", qidx, ret);
 654                 goto config_sq_error;
 655         }
 656
 657         dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
 658         return ret;
 659
 660 config_sq_error:
 661         nicvf_qset_sq_reclaim(nicvf_pmd_priv(dev), qidx);
 662         return ret;
 663 }
 664
 665 static inline int
 666 nicvf_stop_tx_queue(struct rte_eth_dev *dev, uint16_t qidx)
 667 {
 668         struct nicvf_txq *txq;
 669         int ret;
 670
 671         if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
 672                 return 0;
 673
 674         ret = nicvf_qset_sq_reclaim(nicvf_pmd_priv(dev), qidx);
 675         if (ret)
 676                 PMD_INIT_LOG(ERR, "Failed to reclaim sq %d %d", qidx, ret);
 677
 678         txq = dev->data->tx_queues[qidx];
 679         nicvf_tx_queue_release_mbufs(txq);
 680         nicvf_tx_queue_reset(txq);
 681
 682         dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 683         return ret;
 684 }
 685
 686 static inline int
 687 nicvf_configure_cpi(struct rte_eth_dev *dev)
 688 {
 689         struct nicvf *nic = nicvf_pmd_priv(dev);
 690         uint16_t qidx, qcnt;
 691         int ret;
 692
 693         /* Count started rx queues */
 694         for (qidx = qcnt = 0; qidx < nic->eth_dev->data->nb_rx_queues; qidx++)
 695                 if (dev->data->rx_queue_state[qidx] ==
 696                     RTE_ETH_QUEUE_STATE_STARTED)
 697                         qcnt++;
 698
 699         nic->cpi_alg = CPI_ALG_NONE;
 700         ret = nicvf_mbox_config_cpi(nic, qcnt);
 701         if (ret)
 702                 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
 703
 704         return ret;
 705 }
 706
 707 static inline int
 708 nicvf_configure_rss(struct rte_eth_dev *dev)
 709 {
 710         struct nicvf *nic = nicvf_pmd_priv(dev);
 711         uint64_t rsshf;
 712         int ret = -EINVAL;
 713
 714         rsshf = nicvf_rss_ethdev_to_nic(nic,
 715                         dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
 716         PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
 717                     dev->data->dev_conf.rxmode.mq_mode,
 718                     nic->eth_dev->data->nb_rx_queues,
 719                     nic->eth_dev->data->dev_conf.lpbk_mode, rsshf);
 720
 721         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 722                 ret = nicvf_rss_term(nic);
 723         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 724                 ret = nicvf_rss_config(nic,
 725                                        nic->eth_dev->data->nb_rx_queues, rsshf);
 726         if (ret)
 727                 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
 728
 729         return ret;
 730 }
 731
 732 static int
 733 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
 734 {
 735         struct nicvf *nic = nicvf_pmd_priv(dev);
 736         unsigned int idx, qmap_size;
 737         uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
 738         uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
 739
 740         if (nic->cpi_alg != CPI_ALG_NONE)
 741                 return -EINVAL;
 742
 743         /* Prepare queue map */
 744         for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
 745                 if (dev->data->rx_queue_state[idx] ==
 746                                 RTE_ETH_QUEUE_STATE_STARTED)
 747                         qmap[qmap_size++] = idx;
 748         }
 749
 750         /* Update default RSS RETA */
 751         for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
 752                 default_reta[idx] = qmap[idx % qmap_size];
 753
 754         return nicvf_rss_reta_update(nic, default_reta,
 755                                      NIC_MAX_RSS_IDR_TBL_SIZE);
 756 }
 757
 758 static void
 759 nicvf_dev_tx_queue_release(void *sq)
 760 {
 761         struct nicvf_txq *txq;
 762
 763         PMD_INIT_FUNC_TRACE();
 764
 765         txq = (struct nicvf_txq *)sq;
 766         if (txq) {
 767                 if (txq->txbuffs != NULL) {
 768                         nicvf_tx_queue_release_mbufs(txq);
 769                         rte_free(txq->txbuffs);
 770                         txq->txbuffs = NULL;
 771                 }
 772                 rte_free(txq);
 773         }
 774 }
 775
 776 static void
 777 nicvf_set_tx_function(struct rte_eth_dev *dev)
 778 {
 779         struct nicvf_txq *txq;
 780         size_t i;
 781         bool multiseg = false;
 782
 783         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 784                 txq = dev->data->tx_queues[i];
 785                 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
 786                         multiseg = true;
 787                         break;
 788                 }
 789         }
 790
 791         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 792         if (multiseg) {
 793                 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
 794                 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
 795         } else {
 796                 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
 797                 dev->tx_pkt_burst = nicvf_xmit_pkts;
 798         }
 799
 800         if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
 801                 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
 802         else
 803                 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
 804 }
 805
 806 static void
 807 nicvf_set_rx_function(struct rte_eth_dev *dev)
 808 {
 809         if (dev->data->scattered_rx) {
 810                 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
 811                 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
 812         } else {
 813                 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
 814                 dev->rx_pkt_burst = nicvf_recv_pkts;
 815         }
 816 }
 817
 818 static int
 819 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 820                          uint16_t nb_desc, unsigned int socket_id,
 821                          const struct rte_eth_txconf *tx_conf)
 822 {
 823         uint16_t tx_free_thresh;
 824         uint8_t is_single_pool;
 825         struct nicvf_txq *txq;
 826         struct nicvf *nic = nicvf_pmd_priv(dev);
 827
 828         PMD_INIT_FUNC_TRACE();
 829
 830         /* Socket id check */
 831         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 832                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 833                 socket_id, nic->node);
 834
 835         /* Tx deferred start is not supported */
 836         if (tx_conf->tx_deferred_start) {
 837                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 838                 return -EINVAL;
 839         }
 840
 841         /* Roundup nb_desc to available qsize and validate max number of desc */
 842         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 843         if (nb_desc == 0) {
 844                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 845                 return -EINVAL;
 846         }
 847
 848         /* Validate tx_free_thresh */
 849         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 850                                 tx_conf->tx_free_thresh :
 851                                 NICVF_DEFAULT_TX_FREE_THRESH);
 852
 853         if (tx_free_thresh > (nb_desc) ||
 854                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 855                 PMD_INIT_LOG(ERR,
 856                         "tx_free_thresh must be less than the number of TX "
 857                         "descriptors. (tx_free_thresh=%u port=%d "
 858                         "queue=%d)", (unsigned int)tx_free_thresh,
 859                         (int)dev->data->port_id, (int)qidx);
 860                 return -EINVAL;
 861         }
 862
 863         /* Free memory prior to re-allocation if needed. */
 864         if (dev->data->tx_queues[qidx] != NULL) {
 865                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 866                                 qidx);
 867                 nicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);
 868                 dev->data->tx_queues[qidx] = NULL;
 869         }
 870
 871         /* Allocating tx queue data structure */
 872         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
 873                                         RTE_CACHE_LINE_SIZE, nic->node);
 874         if (txq == NULL) {
 875                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", qidx);
 876                 return -ENOMEM;
 877         }
 878
 879         txq->nic = nic;
 880         txq->queue_id = qidx;
 881         txq->tx_free_thresh = tx_free_thresh;
 882         txq->txq_flags = tx_conf->txq_flags;
 883         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
 884         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
 885         is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
 886                                 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
 887
 888         /* Choose optimum free threshold value for multipool case */
 889         if (!is_single_pool) {
 890                 txq->tx_free_thresh = (uint16_t)
 891                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
 892                                 NICVF_TX_FREE_MPOOL_THRESH :
 893                                 tx_conf->tx_free_thresh);
 894                 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
 895         } else {
 896                 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
 897         }
 898
 899         /* Allocate software ring */
 900         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
 901                                 nb_desc * sizeof(struct rte_mbuf *),
 902                                 RTE_CACHE_LINE_SIZE, nic->node);
 903
 904         if (txq->txbuffs == NULL) {
 905                 nicvf_dev_tx_queue_release(txq);
 906                 return -ENOMEM;
 907         }
 908
 909         if (nicvf_qset_sq_alloc(nic, txq, qidx, nb_desc)) {
 910                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
 911                 nicvf_dev_tx_queue_release(txq);
 912                 return -ENOMEM;
 913         }
 914
 915         nicvf_tx_queue_reset(txq);
 916
 917         PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
 918                         qidx, txq, nb_desc, txq->desc, txq->phys);
 919
 920         dev->data->tx_queues[qidx] = txq;
 921         dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 922         return 0;
 923 }
 924
 925 static inline void
 926 nicvf_rx_queue_release_mbufs(struct nicvf_rxq *rxq)
 927 {
 928         uint32_t rxq_cnt;
 929         uint32_t nb_pkts, released_pkts = 0;
 930         uint32_t refill_cnt = 0;
 931         struct rte_eth_dev *dev = rxq->nic->eth_dev;
 932         struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
 933
 934         if (dev->rx_pkt_burst == NULL)
 935                 return;
 936
 937         while ((rxq_cnt = nicvf_dev_rx_queue_count(dev, rxq->queue_id))) {
 938                 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
 939                                         NICVF_MAX_RX_FREE_THRESH);
 940                 PMD_DRV_LOG(INFO, "nb_pkts=%d  rxq_cnt=%d", nb_pkts, rxq_cnt);
 941                 while (nb_pkts) {
 942                         rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
 943                         released_pkts++;
 944                 }
 945         }
 946
 947         refill_cnt += nicvf_dev_rbdr_refill(dev, rxq->queue_id);
 948         PMD_DRV_LOG(INFO, "free_cnt=%d  refill_cnt=%d",
 949                     released_pkts, refill_cnt);
 950 }
 951
 952 static void
 953 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
 954 {
 955         rxq->head = 0;
 956         rxq->available_space = 0;
 957         rxq->recv_buffers = 0;
 958 }
 959
 960 static inline int
 961 nicvf_start_rx_queue(struct rte_eth_dev *dev, uint16_t qidx)
 962 {
 963         struct nicvf *nic = nicvf_pmd_priv(dev);
 964         struct nicvf_rxq *rxq;
 965         int ret;
 966
 967         if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
 968                 return 0;
 969
 970         /* Update rbdr pointer to all rxq */
 971         rxq = dev->data->rx_queues[qidx];
 972         rxq->shared_rbdr = nic->rbdr;
 973
 974         ret = nicvf_qset_rq_config(nic, qidx, rxq);
 975         if (ret) {
 976                 PMD_INIT_LOG(ERR, "Failed to configure rq %d %d", qidx, ret);
 977                 goto config_rq_error;
 978         }
 979         ret = nicvf_qset_cq_config(nic, qidx, rxq);
 980         if (ret) {
 981                 PMD_INIT_LOG(ERR, "Failed to configure cq %d %d", qidx, ret);
 982                 goto config_cq_error;
 983         }
 984
 985         dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
 986         return 0;
 987
 988 config_cq_error:
 989         nicvf_qset_cq_reclaim(nic, qidx);
 990 config_rq_error:
 991         nicvf_qset_rq_reclaim(nic, qidx);
 992         return ret;
 993 }
 994
 995 static inline int
 996 nicvf_stop_rx_queue(struct rte_eth_dev *dev, uint16_t qidx)
 997 {
 998         struct nicvf *nic = nicvf_pmd_priv(dev);
 999         struct nicvf_rxq *rxq;
1000         int ret, other_error;
1001
1002         if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1003                 return 0;
1004
1005         ret = nicvf_qset_rq_reclaim(nic, qidx);
1006         if (ret)
1007                 PMD_INIT_LOG(ERR, "Failed to reclaim rq %d %d", qidx, ret);
1008
1009         other_error = ret;
1010         rxq = dev->data->rx_queues[qidx];
1011         nicvf_rx_queue_release_mbufs(rxq);
1012         nicvf_rx_queue_reset(rxq);
1013
1014         ret = nicvf_qset_cq_reclaim(nic, qidx);
1015         if (ret)
1016                 PMD_INIT_LOG(ERR, "Failed to reclaim cq %d %d", qidx, ret);
1017
1018         other_error |= ret;
1019         dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1020         return other_error;
1021 }
1022
1023 static void
1024 nicvf_dev_rx_queue_release(void *rx_queue)
1025 {
1026         struct nicvf_rxq *rxq = rx_queue;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         if (rxq)
1031                 rte_free(rxq);
1032 }
1033
1034 static int
1035 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1036 {
1037         int ret;
1038
1039         ret = nicvf_start_rx_queue(dev, qidx);
1040         if (ret)
1041                 return ret;
1042
1043         ret = nicvf_configure_cpi(dev);
1044         if (ret)
1045                 return ret;
1046
1047         return nicvf_configure_rss_reta(dev);
1048 }
1049
1050 static int
1051 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1052 {
1053         int ret;
1054
1055         ret = nicvf_stop_rx_queue(dev, qidx);
1056         ret |= nicvf_configure_cpi(dev);
1057         ret |= nicvf_configure_rss_reta(dev);
1058         return ret;
1059 }
1060
1061 static int
1062 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1063 {
1064         return nicvf_start_tx_queue(dev, qidx);
1065 }
1066
1067 static int
1068 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1069 {
1070         return nicvf_stop_tx_queue(dev, qidx);
1071 }
1072
1073 static int
1074 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1075                          uint16_t nb_desc, unsigned int socket_id,
1076                          const struct rte_eth_rxconf *rx_conf,
1077                          struct rte_mempool *mp)
1078 {
1079         uint16_t rx_free_thresh;
1080         struct nicvf_rxq *rxq;
1081         struct nicvf *nic = nicvf_pmd_priv(dev);
1082
1083         PMD_INIT_FUNC_TRACE();
1084
1085         /* Socket id check */
1086         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1087                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1088                 socket_id, nic->node);
1089
1090         /* Mempool memory should be contiguous */
1091         if (mp->nb_mem_chunks != 1) {
1092                 PMD_INIT_LOG(ERR, "Non contiguous mempool, check huge page sz");
1093                 return -EINVAL;
1094         }
1095
1096         /* Rx deferred start is not supported */
1097         if (rx_conf->rx_deferred_start) {
1098                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1099                 return -EINVAL;
1100         }
1101
1102         /* Roundup nb_desc to available qsize and validate max number of desc */
1103         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1104         if (nb_desc == 0) {
1105                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1106                 return -EINVAL;
1107         }
1108
1109         /* Check rx_free_thresh upper bound */
1110         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1111                                 rx_conf->rx_free_thresh :
1112                                 NICVF_DEFAULT_RX_FREE_THRESH);
1113         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1114                 rx_free_thresh >= nb_desc * .75) {
1115                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1116                                 rx_free_thresh);
1117                 return -EINVAL;
1118         }
1119
1120         /* Free memory prior to re-allocation if needed */
1121         if (dev->data->rx_queues[qidx] != NULL) {
1122                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1123                                 qidx);
1124                 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]);
1125                 dev->data->rx_queues[qidx] = NULL;
1126         }
1127
1128         /* Allocate rxq memory */
1129         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1130                                         RTE_CACHE_LINE_SIZE, nic->node);
1131         if (rxq == NULL) {
1132                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx);
1133                 return -ENOMEM;
1134         }
1135
1136         rxq->nic = nic;
1137         rxq->pool = mp;
1138         rxq->queue_id = qidx;
1139         rxq->port_id = dev->data->port_id;
1140         rxq->rx_free_thresh = rx_free_thresh;
1141         rxq->rx_drop_en = rx_conf->rx_drop_en;
1142         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1143         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1144         rxq->precharge_cnt = 0;
1145
1146         if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1147                 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1148         else
1149                 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1150
1151
1152         /* Alloc completion queue */
1153         if (nicvf_qset_cq_alloc(nic, rxq, rxq->queue_id, nb_desc)) {
1154                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1155                 nicvf_dev_rx_queue_release(rxq);
1156                 return -ENOMEM;
1157         }
1158
1159         nicvf_rx_queue_reset(rxq);
1160
1161         PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1162                         qidx, rxq, mp->name, nb_desc,
1163                         rte_mempool_avail_count(mp), rxq->phys);
1164
1165         dev->data->rx_queues[qidx] = rxq;
1166         dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1167         return 0;
1168 }
1169
1170 static void
1171 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1172 {
1173         struct nicvf *nic = nicvf_pmd_priv(dev);
1174
1175         PMD_INIT_FUNC_TRACE();
1176
1177         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1178         dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1179         dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
1180         dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
1181         dev_info->max_mac_addrs = 1;
1182         dev_info->max_vfs = dev->pci_dev->max_vfs;
1183
1184         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1185         dev_info->tx_offload_capa =
1186                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1187                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1188                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1189                 DEV_TX_OFFLOAD_TCP_TSO     |
1190                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1191
1192         dev_info->reta_size = nic->rss_info.rss_size;
1193         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1194         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1195         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1196                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1197
1198         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1199                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1200                 .rx_drop_en = 0,
1201         };
1202
1203         dev_info->default_txconf = (struct rte_eth_txconf) {
1204                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1205                 .txq_flags =
1206                         ETH_TXQ_FLAGS_NOMULTSEGS  |
1207                         ETH_TXQ_FLAGS_NOREFCOUNT  |
1208                         ETH_TXQ_FLAGS_NOMULTMEMP  |
1209                         ETH_TXQ_FLAGS_NOVLANOFFL  |
1210                         ETH_TXQ_FLAGS_NOXSUMSCTP,
1211         };
1212 }
1213
1214 static nicvf_phys_addr_t
1215 rbdr_rte_mempool_get(void *opaque)
1216 {
1217         uint16_t qidx;
1218         uintptr_t mbuf;
1219         struct nicvf_rxq *rxq;
1220         struct nicvf *nic = nicvf_pmd_priv((struct rte_eth_dev *)opaque);
1221
1222         for (qidx = 0; qidx < nic->eth_dev->data->nb_rx_queues; qidx++) {
1223                 rxq = nic->eth_dev->data->rx_queues[qidx];
1224                 /* Maintain equal buffer count across all pools */
1225                 if (rxq->precharge_cnt >= rxq->qlen_mask)
1226                         continue;
1227                 rxq->precharge_cnt++;
1228                 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1229                 if (mbuf)
1230                         return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1231         }
1232         return 0;
1233 }
1234
1235 static int
1236 nicvf_dev_start(struct rte_eth_dev *dev)
1237 {
1238         int ret;
1239         uint16_t qidx;
1240         uint32_t buffsz = 0, rbdrsz = 0;
1241         uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1242         uint64_t mbuf_phys_off = 0;
1243         struct nicvf_rxq *rxq;
1244         struct rte_pktmbuf_pool_private *mbp_priv;
1245         struct rte_mbuf *mbuf;
1246         struct nicvf *nic = nicvf_pmd_priv(dev);
1247         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1248         uint16_t mtu;
1249
1250         PMD_INIT_FUNC_TRACE();
1251
1252         /* Userspace process exited without proper shutdown in last run */
1253         if (nicvf_qset_rbdr_active(nic, 0))
1254                 nicvf_dev_stop(dev);
1255
1256         /*
1257          * Thunderx nicvf PMD can support more than one pool per port only when
1258          * 1) Data payload size is same across all the pools in given port
1259          * AND
1260          * 2) All mbuffs in the pools are from the same hugepage
1261          * AND
1262          * 3) Mbuff metadata size is same across all the pools in given port
1263          *
1264          * This is to support existing application that uses multiple pool/port.
1265          * But, the purpose of using multipool for QoS will not be addressed.
1266          *
1267          */
1268
1269         /* Validate RBDR buff size */
1270         for (qidx = 0; qidx < nic->eth_dev->data->nb_rx_queues; qidx++) {
1271                 rxq = dev->data->rx_queues[qidx];
1272                 mbp_priv = rte_mempool_get_priv(rxq->pool);
1273                 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1274                 if (buffsz % 128) {
1275                         PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1276                         return -EINVAL;
1277                 }
1278                 if (rbdrsz == 0)
1279                         rbdrsz = buffsz;
1280                 if (rbdrsz != buffsz) {
1281                         PMD_INIT_LOG(ERR, "buffsz not same, qid=%d (%d/%d)",
1282                                      qidx, rbdrsz, buffsz);
1283                         return -EINVAL;
1284                 }
1285         }
1286
1287         /* Validate mempool attributes */
1288         for (qidx = 0; qidx < nic->eth_dev->data->nb_rx_queues; qidx++) {
1289                 rxq = dev->data->rx_queues[qidx];
1290                 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1291                 mbuf = rte_pktmbuf_alloc(rxq->pool);
1292                 if (mbuf == NULL) {
1293                         PMD_INIT_LOG(ERR, "Failed allocate mbuf qid=%d pool=%s",
1294                                      qidx, rxq->pool->name);
1295                         return -ENOMEM;
1296                 }
1297                 rxq->mbuf_phys_off -= nicvf_mbuff_meta_length(mbuf);
1298                 rxq->mbuf_phys_off -= RTE_PKTMBUF_HEADROOM;
1299                 rte_pktmbuf_free(mbuf);
1300
1301                 if (mbuf_phys_off == 0)
1302                         mbuf_phys_off = rxq->mbuf_phys_off;
1303                 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1304                         PMD_INIT_LOG(ERR, "pool params not same,%s %" PRIx64,
1305                                      rxq->pool->name, mbuf_phys_off);
1306                         return -EINVAL;
1307                 }
1308         }
1309
1310         /* Check the level of buffers in the pool */
1311         total_rxq_desc = 0;
1312         for (qidx = 0; qidx < nic->eth_dev->data->nb_rx_queues; qidx++) {
1313                 rxq = dev->data->rx_queues[qidx];
1314                 /* Count total numbers of rxq descs */
1315                 total_rxq_desc += rxq->qlen_mask + 1;
1316                 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1317                 exp_buffs *= nic->eth_dev->data->nb_rx_queues;
1318                 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1319                         PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1320                                      rxq->pool->name,
1321                                      rte_mempool_avail_count(rxq->pool),
1322                                      exp_buffs);
1323                         return -ENOENT;
1324                 }
1325         }
1326
1327         /* Check RBDR desc overflow */
1328         ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1329         if (ret == 0) {
1330                 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc");
1331                 return -ENOMEM;
1332         }
1333
1334         /* Enable qset */
1335         ret = nicvf_qset_config(nic);
1336         if (ret) {
1337                 PMD_INIT_LOG(ERR, "Failed to enable qset %d", ret);
1338                 return ret;
1339         }
1340
1341         /* Allocate RBDR and RBDR ring desc */
1342         nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1343         ret = nicvf_qset_rbdr_alloc(nic, nb_rbdr_desc, rbdrsz);
1344         if (ret) {
1345                 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc");
1346                 goto qset_reclaim;
1347         }
1348
1349         /* Enable and configure RBDR registers */
1350         ret = nicvf_qset_rbdr_config(nic, 0);
1351         if (ret) {
1352                 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d", ret);
1353                 goto qset_rbdr_free;
1354         }
1355
1356         /* Fill rte_mempool buffers in RBDR pool and precharge it */
1357         ret = nicvf_qset_rbdr_precharge(nic, 0, rbdr_rte_mempool_get,
1358                                         dev, total_rxq_desc);
1359         if (ret) {
1360                 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d", ret);
1361                 goto qset_rbdr_reclaim;
1362         }
1363
1364         PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR",
1365                      nic->rbdr->tail, nb_rbdr_desc);
1366
1367         /* Configure RX queues */
1368         for (qidx = 0; qidx < nic->eth_dev->data->nb_rx_queues; qidx++) {
1369                 ret = nicvf_start_rx_queue(dev, qidx);
1370                 if (ret)
1371                         goto start_rxq_error;
1372         }
1373
1374         /* Configure VLAN Strip */
1375         nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1376
1377         /* Configure TX queues */
1378         for (qidx = 0; qidx < nic->eth_dev->data->nb_tx_queues; qidx++) {
1379                 ret = nicvf_start_tx_queue(dev, qidx);
1380                 if (ret)
1381                         goto start_txq_error;
1382         }
1383
1384         /* Configure CPI algorithm */
1385         ret = nicvf_configure_cpi(dev);
1386         if (ret)
1387                 goto start_txq_error;
1388
1389         /* Configure RSS */
1390         ret = nicvf_configure_rss(dev);
1391         if (ret)
1392                 goto qset_rss_error;
1393
1394         /* Configure loopback */
1395         ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1396         if (ret) {
1397                 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1398                 goto qset_rss_error;
1399         }
1400
1401         /* Reset all statistics counters attached to this port */
1402         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1403         if (ret) {
1404                 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1405                 goto qset_rss_error;
1406         }
1407
1408         /* Setup scatter mode if needed by jumbo */
1409         if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1410                                             2 * VLAN_TAG_SIZE > buffsz)
1411                 dev->data->scattered_rx = 1;
1412         if (rx_conf->enable_scatter)
1413                 dev->data->scattered_rx = 1;
1414
1415         /* Setup MTU based on max_rx_pkt_len or default */
1416         mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1417                 dev->data->dev_conf.rxmode.max_rx_pkt_len
1418                         -  ETHER_HDR_LEN - ETHER_CRC_LEN
1419                 : ETHER_MTU;
1420
1421         if (nicvf_dev_set_mtu(dev, mtu)) {
1422                 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1423                 return -EBUSY;
1424         }
1425
1426         /* Configure callbacks based on scatter mode */
1427         nicvf_set_tx_function(dev);
1428         nicvf_set_rx_function(dev);
1429
1430         /* Done; Let PF make the BGX's RX and TX switches to ON position */
1431         nicvf_mbox_cfg_done(nic);
1432         return 0;
1433
1434 qset_rss_error:
1435         nicvf_rss_term(nic);
1436 start_txq_error:
1437         for (qidx = 0; qidx < nic->eth_dev->data->nb_tx_queues; qidx++)
1438                 nicvf_stop_tx_queue(dev, qidx);
1439 start_rxq_error:
1440         for (qidx = 0; qidx < nic->eth_dev->data->nb_rx_queues; qidx++)
1441                 nicvf_stop_rx_queue(dev, qidx);
1442 qset_rbdr_reclaim:
1443         nicvf_qset_rbdr_reclaim(nic, 0);
1444         nicvf_rbdr_release_mbufs(nic);
1445 qset_rbdr_free:
1446         if (nic->rbdr) {
1447                 rte_free(nic->rbdr);
1448                 nic->rbdr = NULL;
1449         }
1450 qset_reclaim:
1451         nicvf_qset_reclaim(nic);
1452         return ret;
1453 }
1454
1455 static void
1456 nicvf_dev_stop(struct rte_eth_dev *dev)
1457 {
1458         int ret;
1459         uint16_t qidx;
1460         struct nicvf *nic = nicvf_pmd_priv(dev);
1461
1462         PMD_INIT_FUNC_TRACE();
1463
1464         /* Let PF make the BGX's RX and TX switches to OFF position */
1465         nicvf_mbox_shutdown(nic);
1466
1467         /* Disable loopback */
1468         ret = nicvf_loopback_config(nic, 0);
1469         if (ret)
1470                 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1471
1472         /* Disable VLAN Strip */
1473         nicvf_vlan_hw_strip(nic, 0);
1474
1475         /* Reclaim sq */
1476         for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++)
1477                 nicvf_stop_tx_queue(dev, qidx);
1478
1479         /* Reclaim rq */
1480         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++)
1481                 nicvf_stop_rx_queue(dev, qidx);
1482
1483         /* Reclaim RBDR */
1484         ret = nicvf_qset_rbdr_reclaim(nic, 0);
1485         if (ret)
1486                 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1487
1488         /* Move all charged buffers in RBDR back to pool */
1489         if (nic->rbdr != NULL)
1490                 nicvf_rbdr_release_mbufs(nic);
1491
1492         /* Reclaim CPI configuration */
1493         if (!nic->sqs_mode) {
1494                 ret = nicvf_mbox_config_cpi(nic, 0);
1495                 if (ret)
1496                         PMD_INIT_LOG(ERR, "Failed to reclaim CPI config");
1497         }
1498
1499         /* Disable qset */
1500         ret = nicvf_qset_config(nic);
1501         if (ret)
1502                 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1503
1504         /* Disable all interrupts */
1505         nicvf_disable_all_interrupts(nic);
1506
1507         /* Free RBDR SW structure */
1508         if (nic->rbdr) {
1509                 rte_free(nic->rbdr);
1510                 nic->rbdr = NULL;
1511         }
1512 }
1513
1514 static void
1515 nicvf_dev_close(struct rte_eth_dev *dev)
1516 {
1517         struct nicvf *nic = nicvf_pmd_priv(dev);
1518
1519         PMD_INIT_FUNC_TRACE();
1520
1521         nicvf_dev_stop(dev);
1522         nicvf_periodic_alarm_stop(nic);
1523 }
1524
1525 static int
1526 nicvf_dev_configure(struct rte_eth_dev *dev)
1527 {
1528         struct rte_eth_conf *conf = &dev->data->dev_conf;
1529         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1530         struct rte_eth_txmode *txmode = &conf->txmode;
1531         struct nicvf *nic = nicvf_pmd_priv(dev);
1532
1533         PMD_INIT_FUNC_TRACE();
1534
1535         if (!rte_eal_has_hugepages()) {
1536                 PMD_INIT_LOG(INFO, "Huge page is not configured");
1537                 return -EINVAL;
1538         }
1539
1540         if (txmode->mq_mode) {
1541                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1542                 return -EINVAL;
1543         }
1544
1545         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1546                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1547                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1548                 return -EINVAL;
1549         }
1550
1551         if (!rxmode->hw_strip_crc) {
1552                 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1553                 rxmode->hw_strip_crc = 1;
1554         }
1555
1556         if (rxmode->hw_ip_checksum) {
1557                 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1558                 rxmode->hw_ip_checksum = 0;
1559         }
1560
1561         if (rxmode->split_hdr_size) {
1562                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1563                 return -EINVAL;
1564         }
1565
1566         if (rxmode->hw_vlan_filter) {
1567                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1568                 return -EINVAL;
1569         }
1570
1571         if (rxmode->hw_vlan_extend) {
1572                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1573                 return -EINVAL;
1574         }
1575
1576         if (rxmode->enable_lro) {
1577                 PMD_INIT_LOG(INFO, "LRO not supported");
1578                 return -EINVAL;
1579         }
1580
1581         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1582                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1583                 return -EINVAL;
1584         }
1585
1586         if (conf->dcb_capability_en) {
1587                 PMD_INIT_LOG(INFO, "DCB enable not supported");
1588                 return -EINVAL;
1589         }
1590
1591         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1592                 PMD_INIT_LOG(INFO, "Flow director not supported");
1593                 return -EINVAL;
1594         }
1595
1596         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1597                 dev->data->port_id, nicvf_hw_cap(nic));
1598
1599         return 0;
1600 }
1601
1602 /* Initialize and register driver with DPDK Application */
1603 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1604         .dev_configure            = nicvf_dev_configure,
1605         .dev_start                = nicvf_dev_start,
1606         .dev_stop                 = nicvf_dev_stop,
1607         .link_update              = nicvf_dev_link_update,
1608         .dev_close                = nicvf_dev_close,
1609         .stats_get                = nicvf_dev_stats_get,
1610         .stats_reset              = nicvf_dev_stats_reset,
1611         .promiscuous_enable       = nicvf_dev_promisc_enable,
1612         .dev_infos_get            = nicvf_dev_info_get,
1613         .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1614         .mtu_set                  = nicvf_dev_set_mtu,
1615         .reta_update              = nicvf_dev_reta_update,
1616         .reta_query               = nicvf_dev_reta_query,
1617         .rss_hash_update          = nicvf_dev_rss_hash_update,
1618         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
1619         .rx_queue_start           = nicvf_dev_rx_queue_start,
1620         .rx_queue_stop            = nicvf_dev_rx_queue_stop,
1621         .tx_queue_start           = nicvf_dev_tx_queue_start,
1622         .tx_queue_stop            = nicvf_dev_tx_queue_stop,
1623         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
1624         .rx_queue_release         = nicvf_dev_rx_queue_release,
1625         .rx_queue_count           = nicvf_dev_rx_queue_count,
1626         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
1627         .tx_queue_release         = nicvf_dev_tx_queue_release,
1628         .get_reg                  = nicvf_dev_get_regs,
1629 };
1630
1631 static int
1632 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
1633 {
1634         int ret;
1635         struct rte_pci_device *pci_dev;
1636         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
1637
1638         PMD_INIT_FUNC_TRACE();
1639
1640         eth_dev->dev_ops = &nicvf_eth_dev_ops;
1641
1642         /* For secondary processes, the primary has done all the work */
1643         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1644                 /* Setup callbacks for secondary process */
1645                 nicvf_set_tx_function(eth_dev);
1646                 nicvf_set_rx_function(eth_dev);
1647                 return 0;
1648         }
1649
1650         pci_dev = eth_dev->pci_dev;
1651         rte_eth_copy_pci_info(eth_dev, pci_dev);
1652
1653         nic->device_id = pci_dev->id.device_id;
1654         nic->vendor_id = pci_dev->id.vendor_id;
1655         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
1656         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1657         nic->eth_dev = eth_dev;
1658
1659         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
1660                         pci_dev->id.vendor_id, pci_dev->id.device_id,
1661                         pci_dev->addr.domain, pci_dev->addr.bus,
1662                         pci_dev->addr.devid, pci_dev->addr.function);
1663
1664         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
1665         if (!nic->reg_base) {
1666                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
1667                 ret = -ENODEV;
1668                 goto fail;
1669         }
1670
1671         nicvf_disable_all_interrupts(nic);
1672
1673         ret = nicvf_periodic_alarm_start(nic);
1674         if (ret) {
1675                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
1676                 goto fail;
1677         }
1678
1679         ret = nicvf_mbox_check_pf_ready(nic);
1680         if (ret) {
1681                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
1682                 goto alarm_fail;
1683         } else {
1684                 PMD_INIT_LOG(INFO,
1685                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
1686                         nic->node, nic->vf_id,
1687                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
1688                         nic->sqs_mode ? "true" : "false",
1689                         nic->loopback_supported ? "true" : "false"
1690                         );
1691         }
1692
1693         if (nic->sqs_mode) {
1694                 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
1695                 /* Detach port by returning Positive error number */
1696                 ret = ENOTSUP;
1697                 goto alarm_fail;
1698         }
1699
1700         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
1701         if (eth_dev->data->mac_addrs == NULL) {
1702                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
1703                 ret = -ENOMEM;
1704                 goto alarm_fail;
1705         }
1706         if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
1707                 eth_random_addr(&nic->mac_addr[0]);
1708
1709         ether_addr_copy((struct ether_addr *)nic->mac_addr,
1710                         &eth_dev->data->mac_addrs[0]);
1711
1712         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
1713         if (ret) {
1714                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
1715                 goto malloc_fail;
1716         }
1717
1718         ret = nicvf_base_init(nic);
1719         if (ret) {
1720                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
1721                 goto malloc_fail;
1722         }
1723
1724         ret = nicvf_mbox_get_rss_size(nic);
1725         if (ret) {
1726                 PMD_INIT_LOG(ERR, "Failed to get rss table size");
1727                 goto malloc_fail;
1728         }
1729
1730         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
1731                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
1732                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
1733                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
1734
1735         return 0;
1736
1737 malloc_fail:
1738         rte_free(eth_dev->data->mac_addrs);
1739 alarm_fail:
1740         nicvf_periodic_alarm_stop(nic);
1741 fail:
1742         return ret;
1743 }
1744
1745 static const struct rte_pci_id pci_id_nicvf_map[] = {
1746         {
1747                 .class_id = RTE_CLASS_ANY_ID,
1748                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
1749                 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
1750                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
1751                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
1752         },
1753         {
1754                 .class_id = RTE_CLASS_ANY_ID,
1755                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
1756                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
1757                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
1758                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
1759         },
1760         {
1761                 .class_id = RTE_CLASS_ANY_ID,
1762                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
1763                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
1764                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
1765                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
1766         },
1767         {
1768                 .vendor_id = 0,
1769         },
1770 };
1771
1772 static struct eth_driver rte_nicvf_pmd = {
1773         .pci_drv = {
1774                 .id_table = pci_id_nicvf_map,
1775                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1776                 .probe = rte_eth_dev_pci_probe,
1777                 .remove = rte_eth_dev_pci_remove,
1778         },
1779         .eth_dev_init = nicvf_eth_dev_init,
1780         .dev_private_size = sizeof(struct nicvf),
1781 };
1782
1783 DRIVER_REGISTER_PCI(net_thunderx, rte_nicvf_pmd.pci_drv);
1784 DRIVER_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);