1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016 Cavium, Inc
14 #include <netinet/in.h>
15 #include <sys/queue.h>
17 #include <rte_alarm.h>
18 #include <rte_branch_prediction.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_cycles.h>
22 #include <rte_debug.h>
25 #include <rte_ether.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_ethdev_pci.h>
28 #include <rte_interrupts.h>
30 #include <rte_memory.h>
31 #include <rte_memzone.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_bus_pci.h>
36 #include <rte_tailq.h>
37 #include <rte_devargs.h>
38 #include <rte_kvargs.h>
40 #include "base/nicvf_plat.h"
42 #include "nicvf_ethdev.h"
43 #include "nicvf_rxtx.h"
44 #include "nicvf_svf.h"
45 #include "nicvf_logs.h"
47 int nicvf_logtype_mbox;
48 int nicvf_logtype_init;
49 int nicvf_logtype_driver;
51 static void nicvf_dev_stop(struct rte_eth_dev *dev);
52 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
53 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
56 RTE_INIT(nicvf_init_log)
58 nicvf_logtype_mbox = rte_log_register("pmd.net.thunderx.mbox");
59 if (nicvf_logtype_mbox >= 0)
60 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE);
62 nicvf_logtype_init = rte_log_register("pmd.net.thunderx.init");
63 if (nicvf_logtype_init >= 0)
64 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE);
66 nicvf_logtype_driver = rte_log_register("pmd.net.thunderx.driver");
67 if (nicvf_logtype_driver >= 0)
68 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE);
72 nicvf_link_status_update(struct nicvf *nic,
73 struct rte_eth_link *link)
75 memset(link, 0, sizeof(*link));
77 link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
79 if (nic->duplex == NICVF_HALF_DUPLEX)
80 link->link_duplex = ETH_LINK_HALF_DUPLEX;
81 else if (nic->duplex == NICVF_FULL_DUPLEX)
82 link->link_duplex = ETH_LINK_FULL_DUPLEX;
83 link->link_speed = nic->speed;
84 link->link_autoneg = ETH_LINK_AUTONEG;
88 nicvf_interrupt(void *arg)
90 struct rte_eth_dev *dev = arg;
91 struct nicvf *nic = nicvf_pmd_priv(dev);
92 struct rte_eth_link link;
94 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
95 if (dev->data->dev_conf.intr_conf.lsc) {
96 nicvf_link_status_update(nic, &link);
97 rte_eth_linkstatus_set(dev, &link);
99 _rte_eth_dev_callback_process(dev,
100 RTE_ETH_EVENT_INTR_LSC,
105 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
106 nicvf_interrupt, dev);
110 nicvf_vf_interrupt(void *arg)
112 struct nicvf *nic = arg;
114 nicvf_reg_poll_interrupts(nic);
116 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
117 nicvf_vf_interrupt, nic);
121 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
123 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
127 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
129 return rte_eal_alarm_cancel(fn, arg);
133 * Return 0 means link status changed, -1 means not changed
136 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
138 #define CHECK_INTERVAL 100 /* 100ms */
139 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
140 struct rte_eth_link link;
141 struct nicvf *nic = nicvf_pmd_priv(dev);
144 PMD_INIT_FUNC_TRACE();
146 if (wait_to_complete) {
147 /* rte_eth_link_get() might need to wait up to 9 seconds */
148 for (i = 0; i < MAX_CHECK_TIME; i++) {
149 nicvf_link_status_update(nic, &link);
150 if (link.link_status == ETH_LINK_UP)
152 rte_delay_ms(CHECK_INTERVAL);
155 nicvf_link_status_update(nic, &link);
158 return rte_eth_linkstatus_set(dev, &link);
162 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
164 struct nicvf *nic = nicvf_pmd_priv(dev);
165 uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD;
167 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
169 PMD_INIT_FUNC_TRACE();
171 if (frame_size > NIC_HW_MAX_FRS)
174 if (frame_size < NIC_HW_MIN_FRS)
177 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
180 * Refuse mtu that requires the support of scattered packets
181 * when this feature has not been enabled before.
183 if (dev->data->dev_started && !dev->data->scattered_rx &&
184 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
187 /* check <seg size> * <max_seg> >= max_frame */
188 if (dev->data->scattered_rx &&
189 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
192 if (frame_size > ETHER_MAX_LEN)
193 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
195 rxmode->offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
197 if (nicvf_mbox_update_hw_max_frs(nic, mtu))
200 /* Update max_rx_pkt_len */
201 rxmode->max_rx_pkt_len = mtu + ETHER_HDR_LEN;
204 for (i = 0; i < nic->sqs_count; i++)
205 nic->snicvf[i]->mtu = mtu;
211 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
213 uint64_t *data = regs->data;
214 struct nicvf *nic = nicvf_pmd_priv(dev);
217 regs->length = nicvf_reg_get_count();
218 regs->width = THUNDERX_REG_BYTES;
222 /* Support only full register dump */
223 if ((regs->length == 0) ||
224 (regs->length == (uint32_t)nicvf_reg_get_count())) {
225 regs->version = nic->vendor_id << 16 | nic->device_id;
226 nicvf_reg_dump(nic, data);
233 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
236 struct nicvf_hw_rx_qstats rx_qstats;
237 struct nicvf_hw_tx_qstats tx_qstats;
238 struct nicvf_hw_stats port_stats;
239 struct nicvf *nic = nicvf_pmd_priv(dev);
240 uint16_t rx_start, rx_end;
241 uint16_t tx_start, tx_end;
244 /* RX queue indices for the first VF */
245 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
247 /* Reading per RX ring stats */
248 for (qidx = rx_start; qidx <= rx_end; qidx++) {
249 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
252 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
253 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
254 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
257 /* TX queue indices for the first VF */
258 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
260 /* Reading per TX ring stats */
261 for (qidx = tx_start; qidx <= tx_end; qidx++) {
262 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
265 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
266 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
267 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
270 for (i = 0; i < nic->sqs_count; i++) {
271 struct nicvf *snic = nic->snicvf[i];
276 /* RX queue indices for a secondary VF */
277 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
279 /* Reading per RX ring stats */
280 for (qidx = rx_start; qidx <= rx_end; qidx++) {
281 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
284 nicvf_hw_get_rx_qstats(snic, &rx_qstats,
285 qidx % MAX_RCV_QUEUES_PER_QS);
286 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
287 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
290 /* TX queue indices for a secondary VF */
291 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
292 /* Reading per TX ring stats */
293 for (qidx = tx_start; qidx <= tx_end; qidx++) {
294 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
297 nicvf_hw_get_tx_qstats(snic, &tx_qstats,
298 qidx % MAX_SND_QUEUES_PER_QS);
299 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
300 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
304 nicvf_hw_get_stats(nic, &port_stats);
305 stats->ibytes = port_stats.rx_bytes;
306 stats->ipackets = port_stats.rx_ucast_frames;
307 stats->ipackets += port_stats.rx_bcast_frames;
308 stats->ipackets += port_stats.rx_mcast_frames;
309 stats->ierrors = port_stats.rx_l2_errors;
310 stats->imissed = port_stats.rx_drop_red;
311 stats->imissed += port_stats.rx_drop_overrun;
312 stats->imissed += port_stats.rx_drop_bcast;
313 stats->imissed += port_stats.rx_drop_mcast;
314 stats->imissed += port_stats.rx_drop_l3_bcast;
315 stats->imissed += port_stats.rx_drop_l3_mcast;
317 stats->obytes = port_stats.tx_bytes_ok;
318 stats->opackets = port_stats.tx_ucast_frames_ok;
319 stats->opackets += port_stats.tx_bcast_frames_ok;
320 stats->opackets += port_stats.tx_mcast_frames_ok;
321 stats->oerrors = port_stats.tx_drops;
326 static const uint32_t *
327 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
330 static uint32_t ptypes[32];
331 struct nicvf *nic = nicvf_pmd_priv(dev);
332 static const uint32_t ptypes_common[] = {
334 RTE_PTYPE_L3_IPV4_EXT,
336 RTE_PTYPE_L3_IPV6_EXT,
341 static const uint32_t ptypes_tunnel[] = {
342 RTE_PTYPE_TUNNEL_GRE,
343 RTE_PTYPE_TUNNEL_GENEVE,
344 RTE_PTYPE_TUNNEL_VXLAN,
345 RTE_PTYPE_TUNNEL_NVGRE,
347 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
349 copied = sizeof(ptypes_common);
350 memcpy(ptypes, ptypes_common, copied);
351 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
352 memcpy((char *)ptypes + copied, ptypes_tunnel,
353 sizeof(ptypes_tunnel));
354 copied += sizeof(ptypes_tunnel);
357 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
359 /* All Ptypes are supported in all Rx functions. */
364 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
367 uint16_t rxqs = 0, txqs = 0;
368 struct nicvf *nic = nicvf_pmd_priv(dev);
369 uint16_t rx_start, rx_end;
370 uint16_t tx_start, tx_end;
372 /* Reset all primary nic counters */
373 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
374 for (i = rx_start; i <= rx_end; i++)
375 rxqs |= (0x3 << (i * 2));
377 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
378 for (i = tx_start; i <= tx_end; i++)
379 txqs |= (0x3 << (i * 2));
381 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
383 /* Reset secondary nic queue counters */
384 for (i = 0; i < nic->sqs_count; i++) {
385 struct nicvf *snic = nic->snicvf[i];
389 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
390 for (i = rx_start; i <= rx_end; i++)
391 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
393 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
394 for (i = tx_start; i <= tx_end; i++)
395 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
397 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
401 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
403 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
407 static inline uint64_t
408 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
410 uint64_t nic_rss = 0;
412 if (ethdev_rss & ETH_RSS_IPV4)
413 nic_rss |= RSS_IP_ENA;
415 if (ethdev_rss & ETH_RSS_IPV6)
416 nic_rss |= RSS_IP_ENA;
418 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
419 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
421 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
422 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
424 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
425 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
427 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
428 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
430 if (ethdev_rss & ETH_RSS_PORT)
431 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
433 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
434 if (ethdev_rss & ETH_RSS_VXLAN)
435 nic_rss |= RSS_TUN_VXLAN_ENA;
437 if (ethdev_rss & ETH_RSS_GENEVE)
438 nic_rss |= RSS_TUN_GENEVE_ENA;
440 if (ethdev_rss & ETH_RSS_NVGRE)
441 nic_rss |= RSS_TUN_NVGRE_ENA;
447 static inline uint64_t
448 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
450 uint64_t ethdev_rss = 0;
452 if (nic_rss & RSS_IP_ENA)
453 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
455 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
456 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
457 ETH_RSS_NONFRAG_IPV6_TCP);
459 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
460 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
461 ETH_RSS_NONFRAG_IPV6_UDP);
463 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
464 ethdev_rss |= ETH_RSS_PORT;
466 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
467 if (nic_rss & RSS_TUN_VXLAN_ENA)
468 ethdev_rss |= ETH_RSS_VXLAN;
470 if (nic_rss & RSS_TUN_GENEVE_ENA)
471 ethdev_rss |= ETH_RSS_GENEVE;
473 if (nic_rss & RSS_TUN_NVGRE_ENA)
474 ethdev_rss |= ETH_RSS_NVGRE;
480 nicvf_dev_reta_query(struct rte_eth_dev *dev,
481 struct rte_eth_rss_reta_entry64 *reta_conf,
484 struct nicvf *nic = nicvf_pmd_priv(dev);
485 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
488 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
489 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
490 "(%d) doesn't match the number hardware can supported "
491 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
495 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
499 /* Copy RETA table */
500 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
501 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
502 if ((reta_conf[i].mask >> j) & 0x01)
503 reta_conf[i].reta[j] = tbl[j];
510 nicvf_dev_reta_update(struct rte_eth_dev *dev,
511 struct rte_eth_rss_reta_entry64 *reta_conf,
514 struct nicvf *nic = nicvf_pmd_priv(dev);
515 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
518 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
519 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
520 "(%d) doesn't match the number hardware can supported "
521 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
525 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
529 /* Copy RETA table */
530 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
531 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
532 if ((reta_conf[i].mask >> j) & 0x01)
533 tbl[j] = reta_conf[i].reta[j];
536 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
540 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
541 struct rte_eth_rss_conf *rss_conf)
543 struct nicvf *nic = nicvf_pmd_priv(dev);
545 if (rss_conf->rss_key)
546 nicvf_rss_get_key(nic, rss_conf->rss_key);
548 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
549 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
554 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
555 struct rte_eth_rss_conf *rss_conf)
557 struct nicvf *nic = nicvf_pmd_priv(dev);
560 if (rss_conf->rss_key &&
561 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
562 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
563 rss_conf->rss_key_len);
567 if (rss_conf->rss_key)
568 nicvf_rss_set_key(nic, rss_conf->rss_key);
570 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
571 nicvf_rss_set_cfg(nic, nic_rss);
576 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
577 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
579 const struct rte_memzone *rz;
580 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
582 rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
583 nicvf_netdev_qidx(nic, qidx), ring_size,
584 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
586 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
590 memset(rz->addr, 0, ring_size);
592 rxq->phys = rz->iova;
593 rxq->desc = rz->addr;
594 rxq->qlen_mask = desc_cnt - 1;
600 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
601 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
603 const struct rte_memzone *rz;
604 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
606 rz = rte_eth_dma_zone_reserve(dev, "sq",
607 nicvf_netdev_qidx(nic, qidx), ring_size,
608 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
610 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
614 memset(rz->addr, 0, ring_size);
618 sq->qlen_mask = desc_cnt - 1;
624 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
625 uint32_t desc_cnt, uint32_t buffsz)
627 struct nicvf_rbdr *rbdr;
628 const struct rte_memzone *rz;
631 assert(nic->rbdr == NULL);
632 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
633 RTE_CACHE_LINE_SIZE, nic->node);
635 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
639 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
640 rz = rte_eth_dma_zone_reserve(dev, "rbdr",
641 nicvf_netdev_qidx(nic, 0), ring_size,
642 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
644 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
648 memset(rz->addr, 0, ring_size);
650 rbdr->phys = rz->iova;
653 rbdr->desc = rz->addr;
654 rbdr->buffsz = buffsz;
655 rbdr->qlen_mask = desc_cnt - 1;
657 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
659 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
666 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
667 nicvf_iova_addr_t phy)
671 struct nicvf_rxq *rxq;
672 uint16_t rx_start, rx_end;
674 /* Get queue ranges for this VF */
675 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
677 for (qidx = rx_start; qidx <= rx_end; qidx++) {
678 rxq = dev->data->rx_queues[qidx];
679 if (rxq->precharge_cnt) {
680 obj = (void *)nicvf_mbuff_phy2virt(phy,
682 rte_mempool_put(rxq->pool, obj);
683 rxq->precharge_cnt--;
690 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
692 uint32_t qlen_mask, head;
693 struct rbdr_entry_t *entry;
694 struct nicvf_rbdr *rbdr = nic->rbdr;
696 qlen_mask = rbdr->qlen_mask;
698 while (head != rbdr->tail) {
699 entry = rbdr->desc + head;
700 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
702 head = head & qlen_mask;
707 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
712 while (head != txq->tail) {
713 if (txq->txbuffs[head]) {
714 rte_pktmbuf_free_seg(txq->txbuffs[head]);
715 txq->txbuffs[head] = NULL;
718 head = head & txq->qlen_mask;
723 nicvf_tx_queue_reset(struct nicvf_txq *txq)
725 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
727 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
728 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
735 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
738 struct nicvf_txq *txq;
741 assert(qidx < MAX_SND_QUEUES_PER_QS);
743 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
744 RTE_ETH_QUEUE_STATE_STARTED)
747 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
749 ret = nicvf_qset_sq_config(nic, qidx, txq);
751 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
752 nic->vf_id, qidx, ret);
753 goto config_sq_error;
756 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
757 RTE_ETH_QUEUE_STATE_STARTED;
761 nicvf_qset_sq_reclaim(nic, qidx);
766 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
769 struct nicvf_txq *txq;
772 assert(qidx < MAX_SND_QUEUES_PER_QS);
774 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
775 RTE_ETH_QUEUE_STATE_STOPPED)
778 ret = nicvf_qset_sq_reclaim(nic, qidx);
780 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
781 nic->vf_id, qidx, ret);
783 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
784 nicvf_tx_queue_release_mbufs(txq);
785 nicvf_tx_queue_reset(txq);
787 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
788 RTE_ETH_QUEUE_STATE_STOPPED;
793 nicvf_configure_cpi(struct rte_eth_dev *dev)
795 struct nicvf *nic = nicvf_pmd_priv(dev);
799 /* Count started rx queues */
800 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
801 if (dev->data->rx_queue_state[qidx] ==
802 RTE_ETH_QUEUE_STATE_STARTED)
805 nic->cpi_alg = CPI_ALG_NONE;
806 ret = nicvf_mbox_config_cpi(nic, qcnt);
808 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
814 nicvf_configure_rss(struct rte_eth_dev *dev)
816 struct nicvf *nic = nicvf_pmd_priv(dev);
820 rsshf = nicvf_rss_ethdev_to_nic(nic,
821 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
822 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
823 dev->data->dev_conf.rxmode.mq_mode,
824 dev->data->nb_rx_queues,
825 dev->data->dev_conf.lpbk_mode, rsshf);
827 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
828 ret = nicvf_rss_term(nic);
829 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
830 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
832 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
838 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
840 struct nicvf *nic = nicvf_pmd_priv(dev);
841 unsigned int idx, qmap_size;
842 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
843 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
845 if (nic->cpi_alg != CPI_ALG_NONE)
848 /* Prepare queue map */
849 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
850 if (dev->data->rx_queue_state[idx] ==
851 RTE_ETH_QUEUE_STATE_STARTED)
852 qmap[qmap_size++] = idx;
855 /* Update default RSS RETA */
856 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
857 default_reta[idx] = qmap[idx % qmap_size];
859 return nicvf_rss_reta_update(nic, default_reta,
860 NIC_MAX_RSS_IDR_TBL_SIZE);
864 nicvf_dev_tx_queue_release(void *sq)
866 struct nicvf_txq *txq;
868 PMD_INIT_FUNC_TRACE();
870 txq = (struct nicvf_txq *)sq;
872 if (txq->txbuffs != NULL) {
873 nicvf_tx_queue_release_mbufs(txq);
874 rte_free(txq->txbuffs);
882 nicvf_set_tx_function(struct rte_eth_dev *dev)
884 struct nicvf_txq *txq = NULL;
886 bool multiseg = false;
888 for (i = 0; i < dev->data->nb_tx_queues; i++) {
889 txq = dev->data->tx_queues[i];
890 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
896 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
898 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
899 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
901 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
902 dev->tx_pkt_burst = nicvf_xmit_pkts;
908 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
909 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
911 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
915 nicvf_set_rx_function(struct rte_eth_dev *dev)
917 struct nicvf *nic = nicvf_pmd_priv(dev);
919 const eth_rx_burst_t rx_burst_func[2][2] = {
920 /* [NORMAL/SCATTER] [NO_CKSUM/CKSUM] */
921 [0][0] = nicvf_recv_pkts_no_offload,
922 [0][1] = nicvf_recv_pkts_cksum,
923 [1][0] = nicvf_recv_pkts_multiseg_no_offload,
924 [1][1] = nicvf_recv_pkts_multiseg_cksum,
928 rx_burst_func[dev->data->scattered_rx][nic->offload_cksum];
932 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
933 uint16_t nb_desc, unsigned int socket_id,
934 const struct rte_eth_txconf *tx_conf)
936 uint16_t tx_free_thresh;
938 struct nicvf_txq *txq;
939 struct nicvf *nic = nicvf_pmd_priv(dev);
942 PMD_INIT_FUNC_TRACE();
944 if (qidx >= MAX_SND_QUEUES_PER_QS)
945 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
947 qidx = qidx % MAX_SND_QUEUES_PER_QS;
949 /* Socket id check */
950 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
951 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
952 socket_id, nic->node);
954 /* Tx deferred start is not supported */
955 if (tx_conf->tx_deferred_start) {
956 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
960 /* Roundup nb_desc to available qsize and validate max number of desc */
961 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
963 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
967 /* Validate tx_free_thresh */
968 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
969 tx_conf->tx_free_thresh :
970 NICVF_DEFAULT_TX_FREE_THRESH);
972 if (tx_free_thresh > (nb_desc) ||
973 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
975 "tx_free_thresh must be less than the number of TX "
976 "descriptors. (tx_free_thresh=%u port=%d "
977 "queue=%d)", (unsigned int)tx_free_thresh,
978 (int)dev->data->port_id, (int)qidx);
982 /* Free memory prior to re-allocation if needed. */
983 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
984 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
985 nicvf_netdev_qidx(nic, qidx));
986 nicvf_dev_tx_queue_release(
987 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
988 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
991 /* Allocating tx queue data structure */
992 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
993 RTE_CACHE_LINE_SIZE, nic->node);
995 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
996 nicvf_netdev_qidx(nic, qidx));
1001 txq->queue_id = qidx;
1002 txq->tx_free_thresh = tx_free_thresh;
1003 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1004 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1005 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1006 txq->offloads = offloads;
1008 is_single_pool = !!(offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE);
1010 /* Choose optimum free threshold value for multipool case */
1011 if (!is_single_pool) {
1012 txq->tx_free_thresh = (uint16_t)
1013 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1014 NICVF_TX_FREE_MPOOL_THRESH :
1015 tx_conf->tx_free_thresh);
1016 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1018 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1021 /* Allocate software ring */
1022 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1023 nb_desc * sizeof(struct rte_mbuf *),
1024 RTE_CACHE_LINE_SIZE, nic->node);
1026 if (txq->txbuffs == NULL) {
1027 nicvf_dev_tx_queue_release(txq);
1031 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1032 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1033 nicvf_dev_tx_queue_release(txq);
1037 nicvf_tx_queue_reset(txq);
1039 PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p"
1040 " phys=0x%" PRIx64 " offloads=0x%" PRIx64,
1041 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1042 txq->phys, txq->offloads);
1044 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1045 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1046 RTE_ETH_QUEUE_STATE_STOPPED;
1051 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1054 uint32_t nb_pkts, released_pkts = 0;
1055 uint32_t refill_cnt = 0;
1056 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1058 if (dev->rx_pkt_burst == NULL)
1061 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1062 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1063 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1064 NICVF_MAX_RX_FREE_THRESH);
1065 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt);
1067 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1073 refill_cnt += nicvf_dev_rbdr_refill(dev,
1074 nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1076 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d",
1077 released_pkts, refill_cnt);
1081 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1084 rxq->available_space = 0;
1085 rxq->recv_buffers = 0;
1089 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1092 struct nicvf_rxq *rxq;
1095 assert(qidx < MAX_RCV_QUEUES_PER_QS);
1097 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1098 RTE_ETH_QUEUE_STATE_STARTED)
1101 /* Update rbdr pointer to all rxq */
1102 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1103 rxq->shared_rbdr = nic->rbdr;
1105 ret = nicvf_qset_rq_config(nic, qidx, rxq);
1107 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1108 nic->vf_id, qidx, ret);
1109 goto config_rq_error;
1111 ret = nicvf_qset_cq_config(nic, qidx, rxq);
1113 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1114 nic->vf_id, qidx, ret);
1115 goto config_cq_error;
1118 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1119 RTE_ETH_QUEUE_STATE_STARTED;
1123 nicvf_qset_cq_reclaim(nic, qidx);
1125 nicvf_qset_rq_reclaim(nic, qidx);
1130 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1133 struct nicvf_rxq *rxq;
1134 int ret, other_error;
1136 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1137 RTE_ETH_QUEUE_STATE_STOPPED)
1140 ret = nicvf_qset_rq_reclaim(nic, qidx);
1142 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1143 nic->vf_id, qidx, ret);
1146 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1147 nicvf_rx_queue_release_mbufs(dev, rxq);
1148 nicvf_rx_queue_reset(rxq);
1150 ret = nicvf_qset_cq_reclaim(nic, qidx);
1152 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1153 nic->vf_id, qidx, ret);
1156 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1157 RTE_ETH_QUEUE_STATE_STOPPED;
1162 nicvf_dev_rx_queue_release(void *rx_queue)
1164 PMD_INIT_FUNC_TRACE();
1170 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1172 struct nicvf *nic = nicvf_pmd_priv(dev);
1175 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1176 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1178 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1180 ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1184 ret = nicvf_configure_cpi(dev);
1188 return nicvf_configure_rss_reta(dev);
1192 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1195 struct nicvf *nic = nicvf_pmd_priv(dev);
1197 if (qidx >= MAX_SND_QUEUES_PER_QS)
1198 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1200 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1202 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1203 ret |= nicvf_configure_cpi(dev);
1204 ret |= nicvf_configure_rss_reta(dev);
1209 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1211 struct nicvf *nic = nicvf_pmd_priv(dev);
1213 if (qidx >= MAX_SND_QUEUES_PER_QS)
1214 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1216 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1218 return nicvf_vf_start_tx_queue(dev, nic, qidx);
1222 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1224 struct nicvf *nic = nicvf_pmd_priv(dev);
1226 if (qidx >= MAX_SND_QUEUES_PER_QS)
1227 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1229 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1231 return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1235 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1238 struct rte_mbuf mb_def;
1239 struct nicvf *nic = rxq->nic;
1241 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1242 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1243 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1244 offsetof(struct rte_mbuf, data_off) != 2);
1245 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1246 offsetof(struct rte_mbuf, data_off) != 4);
1247 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1248 offsetof(struct rte_mbuf, data_off) != 6);
1249 RTE_BUILD_BUG_ON(offsetof(struct nicvf_rxq, rxq_fastpath_data_end) -
1250 offsetof(struct nicvf_rxq,
1251 rxq_fastpath_data_start) > 128);
1253 mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes);
1254 mb_def.port = rxq->port_id;
1255 rte_mbuf_refcnt_set(&mb_def, 1);
1257 /* Prevent compiler reordering: rearm_data covers previous fields */
1258 rte_compiler_barrier();
1259 p = (uintptr_t)&mb_def.rearm_data;
1260 rxq->mbuf_initializer.value = *(uint64_t *)p;
1264 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1265 uint16_t nb_desc, unsigned int socket_id,
1266 const struct rte_eth_rxconf *rx_conf,
1267 struct rte_mempool *mp)
1269 uint16_t rx_free_thresh;
1270 struct nicvf_rxq *rxq;
1271 struct nicvf *nic = nicvf_pmd_priv(dev);
1274 struct rte_pktmbuf_pool_private *mbp_priv;
1276 PMD_INIT_FUNC_TRACE();
1278 /* First skip check */
1279 mbp_priv = rte_mempool_get_priv(mp);
1280 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1281 if (buffsz < (uint32_t)(nic->skip_bytes)) {
1282 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size");
1286 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1287 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1289 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1291 /* Socket id check */
1292 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1293 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1294 socket_id, nic->node);
1296 /* Mempool memory must be contiguous, so must be one memory segment*/
1297 if (mp->nb_mem_chunks != 1) {
1298 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1302 /* Mempool memory must be physically contiguous */
1303 if (mp->flags & MEMPOOL_F_NO_IOVA_CONTIG) {
1304 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1308 /* Rx deferred start is not supported */
1309 if (rx_conf->rx_deferred_start) {
1310 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1314 /* Roundup nb_desc to available qsize and validate max number of desc */
1315 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1317 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1322 /* Check rx_free_thresh upper bound */
1323 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1324 rx_conf->rx_free_thresh :
1325 NICVF_DEFAULT_RX_FREE_THRESH);
1326 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1327 rx_free_thresh >= nb_desc * .75) {
1328 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1333 /* Free memory prior to re-allocation if needed */
1334 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1335 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1336 nicvf_netdev_qidx(nic, qidx));
1337 nicvf_dev_rx_queue_release(
1338 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1339 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1342 /* Allocate rxq memory */
1343 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1344 RTE_CACHE_LINE_SIZE, nic->node);
1346 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1347 nicvf_netdev_qidx(nic, qidx));
1353 rxq->queue_id = qidx;
1354 rxq->port_id = dev->data->port_id;
1355 rxq->rx_free_thresh = rx_free_thresh;
1356 rxq->rx_drop_en = rx_conf->rx_drop_en;
1357 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1358 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1359 rxq->precharge_cnt = 0;
1361 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1362 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1364 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1366 nicvf_rxq_mbuf_setup(rxq);
1368 /* Alloc completion queue */
1369 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1370 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1371 nicvf_dev_rx_queue_release(rxq);
1375 nicvf_rx_queue_reset(rxq);
1377 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1378 PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)"
1379 " phy=0x%" PRIx64 " offloads=0x%" PRIx64,
1380 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1381 rte_mempool_avail_count(mp), rxq->phys, offloads);
1383 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1384 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1385 RTE_ETH_QUEUE_STATE_STOPPED;
1390 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1392 struct nicvf *nic = nicvf_pmd_priv(dev);
1393 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1395 PMD_INIT_FUNC_TRACE();
1397 /* Autonegotiation may be disabled */
1398 dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
1399 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M |
1400 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
1401 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF)
1402 dev_info->speed_capa |= ETH_LINK_SPEED_40G;
1404 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1405 dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + ETHER_HDR_LEN;
1406 dev_info->max_rx_queues =
1407 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1408 dev_info->max_tx_queues =
1409 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1410 dev_info->max_mac_addrs = 1;
1411 dev_info->max_vfs = pci_dev->max_vfs;
1413 dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1414 dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1415 dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1416 dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1418 dev_info->reta_size = nic->rss_info.rss_size;
1419 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1420 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1421 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1422 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1424 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1425 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1427 .offloads = DEV_RX_OFFLOAD_CRC_STRIP,
1430 dev_info->default_txconf = (struct rte_eth_txconf) {
1431 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1432 .offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE |
1433 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1434 DEV_TX_OFFLOAD_UDP_CKSUM |
1435 DEV_TX_OFFLOAD_TCP_CKSUM,
1439 static nicvf_iova_addr_t
1440 rbdr_rte_mempool_get(void *dev, void *opaque)
1444 struct nicvf_rxq *rxq;
1445 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1446 struct nicvf *nic = (struct nicvf *)opaque;
1447 uint16_t rx_start, rx_end;
1449 /* Get queue ranges for this VF */
1450 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1452 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1453 rxq = eth_dev->data->rx_queues[qidx];
1454 /* Maintain equal buffer count across all pools */
1455 if (rxq->precharge_cnt >= rxq->qlen_mask)
1457 rxq->precharge_cnt++;
1458 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1460 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1466 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1469 uint16_t qidx, data_off;
1470 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1471 uint64_t mbuf_phys_off = 0;
1472 struct nicvf_rxq *rxq;
1473 struct rte_mbuf *mbuf;
1474 uint16_t rx_start, rx_end;
1475 uint16_t tx_start, tx_end;
1478 PMD_INIT_FUNC_TRACE();
1480 /* Userspace process exited without proper shutdown in last run */
1481 if (nicvf_qset_rbdr_active(nic, 0))
1482 nicvf_vf_stop(dev, nic, false);
1484 /* Get queue ranges for this VF */
1485 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1488 * Thunderx nicvf PMD can support more than one pool per port only when
1489 * 1) Data payload size is same across all the pools in given port
1491 * 2) All mbuffs in the pools are from the same hugepage
1493 * 3) Mbuff metadata size is same across all the pools in given port
1495 * This is to support existing application that uses multiple pool/port.
1496 * But, the purpose of using multipool for QoS will not be addressed.
1500 /* Validate mempool attributes */
1501 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1502 rxq = dev->data->rx_queues[qidx];
1503 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1504 mbuf = rte_pktmbuf_alloc(rxq->pool);
1506 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1508 nic->vf_id, qidx, rxq->pool->name);
1511 data_off = nicvf_mbuff_meta_length(mbuf);
1512 data_off += RTE_PKTMBUF_HEADROOM;
1513 rte_pktmbuf_free(mbuf);
1515 if (data_off % RTE_CACHE_LINE_SIZE) {
1516 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1517 rxq->pool->name, data_off,
1518 data_off % RTE_CACHE_LINE_SIZE);
1521 rxq->mbuf_phys_off -= data_off;
1522 rxq->mbuf_phys_off -= nic->skip_bytes;
1524 if (mbuf_phys_off == 0)
1525 mbuf_phys_off = rxq->mbuf_phys_off;
1526 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1527 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1528 PRIx64, rxq->pool->name, nic->vf_id,
1534 /* Check the level of buffers in the pool */
1536 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1537 rxq = dev->data->rx_queues[qidx];
1538 /* Count total numbers of rxq descs */
1539 total_rxq_desc += rxq->qlen_mask + 1;
1540 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1541 exp_buffs *= dev->data->nb_rx_queues;
1542 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1543 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1545 rte_mempool_avail_count(rxq->pool),
1551 /* Check RBDR desc overflow */
1552 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1554 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1555 "VF%d", nic->vf_id);
1560 ret = nicvf_qset_config(nic);
1562 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1567 /* Allocate RBDR and RBDR ring desc */
1568 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1569 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1571 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1572 "VF%d", nic->vf_id);
1576 /* Enable and configure RBDR registers */
1577 ret = nicvf_qset_rbdr_config(nic, 0);
1579 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1581 goto qset_rbdr_free;
1584 /* Fill rte_mempool buffers in RBDR pool and precharge it */
1585 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1588 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1590 goto qset_rbdr_reclaim;
1593 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1594 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1596 /* Configure VLAN Strip */
1597 vlan_strip = !!(dev->data->dev_conf.rxmode.offloads &
1598 DEV_RX_OFFLOAD_VLAN_STRIP);
1599 nicvf_vlan_hw_strip(nic, vlan_strip);
1601 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1602 * to the 64bit memory address.
1603 * The alignment creates a hole in mbuf(between the end of headroom and
1604 * packet data start). The new revision of the HW provides an option to
1605 * disable the L3 alignment feature and make mbuf layout looks
1606 * more like other NICs. For better application compatibility, disabling
1607 * l3 alignment feature on the hardware revisions it supports
1609 nicvf_apad_config(nic, false);
1611 /* Get queue ranges for this VF */
1612 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1614 /* Configure TX queues */
1615 for (qidx = tx_start; qidx <= tx_end; qidx++) {
1616 ret = nicvf_vf_start_tx_queue(dev, nic,
1617 qidx % MAX_SND_QUEUES_PER_QS);
1619 goto start_txq_error;
1622 /* Configure RX queues */
1623 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1624 ret = nicvf_vf_start_rx_queue(dev, nic,
1625 qidx % MAX_RCV_QUEUES_PER_QS);
1627 goto start_rxq_error;
1630 if (!nic->sqs_mode) {
1631 /* Configure CPI algorithm */
1632 ret = nicvf_configure_cpi(dev);
1634 goto start_txq_error;
1636 ret = nicvf_mbox_get_rss_size(nic);
1638 PMD_INIT_LOG(ERR, "Failed to get rss table size");
1639 goto qset_rss_error;
1643 ret = nicvf_configure_rss(dev);
1645 goto qset_rss_error;
1648 /* Done; Let PF make the BGX's RX and TX switches to ON position */
1649 nicvf_mbox_cfg_done(nic);
1653 nicvf_rss_term(nic);
1655 for (qidx = rx_start; qidx <= rx_end; qidx++)
1656 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1658 for (qidx = tx_start; qidx <= tx_end; qidx++)
1659 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1661 nicvf_qset_rbdr_reclaim(nic, 0);
1662 nicvf_rbdr_release_mbufs(dev, nic);
1665 rte_free(nic->rbdr);
1669 nicvf_qset_reclaim(nic);
1674 nicvf_dev_start(struct rte_eth_dev *dev)
1679 struct nicvf *nic = nicvf_pmd_priv(dev);
1680 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1682 uint32_t buffsz = 0, rbdrsz = 0;
1683 struct rte_pktmbuf_pool_private *mbp_priv;
1684 struct nicvf_rxq *rxq;
1686 PMD_INIT_FUNC_TRACE();
1688 /* This function must be called for a primary device */
1689 assert_primary(nic);
1691 /* Validate RBDR buff size */
1692 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1693 rxq = dev->data->rx_queues[qidx];
1694 mbp_priv = rte_mempool_get_priv(rxq->pool);
1695 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1697 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1702 if (rbdrsz != buffsz) {
1703 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1704 qidx, rbdrsz, buffsz);
1709 /* Configure loopback */
1710 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1712 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1716 /* Reset all statistics counters attached to this port */
1717 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1719 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1723 /* Setup scatter mode if needed by jumbo */
1724 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1725 2 * VLAN_TAG_SIZE > buffsz)
1726 dev->data->scattered_rx = 1;
1727 if ((rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) != 0)
1728 dev->data->scattered_rx = 1;
1730 /* Setup MTU based on max_rx_pkt_len or default */
1731 mtu = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ?
1732 dev->data->dev_conf.rxmode.max_rx_pkt_len
1733 - ETHER_HDR_LEN : ETHER_MTU;
1735 if (nicvf_dev_set_mtu(dev, mtu)) {
1736 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1740 ret = nicvf_vf_start(dev, nic, rbdrsz);
1744 for (i = 0; i < nic->sqs_count; i++) {
1745 assert(nic->snicvf[i]);
1747 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1752 /* Configure callbacks based on offloads */
1753 nicvf_set_tx_function(dev);
1754 nicvf_set_rx_function(dev);
1760 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1764 struct nicvf *nic = nicvf_pmd_priv(dev);
1766 PMD_INIT_FUNC_TRACE();
1768 /* Teardown secondary vf first */
1769 for (i = 0; i < nic->sqs_count; i++) {
1770 if (!nic->snicvf[i])
1773 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1776 /* Stop the primary VF now */
1777 nicvf_vf_stop(dev, nic, cleanup);
1779 /* Disable loopback */
1780 ret = nicvf_loopback_config(nic, 0);
1782 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1784 /* Reclaim CPI configuration */
1785 ret = nicvf_mbox_config_cpi(nic, 0);
1787 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1791 nicvf_dev_stop(struct rte_eth_dev *dev)
1793 PMD_INIT_FUNC_TRACE();
1795 nicvf_dev_stop_cleanup(dev, false);
1799 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1803 uint16_t tx_start, tx_end;
1804 uint16_t rx_start, rx_end;
1806 PMD_INIT_FUNC_TRACE();
1809 /* Let PF make the BGX's RX and TX switches to OFF position */
1810 nicvf_mbox_shutdown(nic);
1813 /* Disable VLAN Strip */
1814 nicvf_vlan_hw_strip(nic, 0);
1816 /* Get queue ranges for this VF */
1817 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1819 for (qidx = tx_start; qidx <= tx_end; qidx++)
1820 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1822 /* Get queue ranges for this VF */
1823 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1826 for (qidx = rx_start; qidx <= rx_end; qidx++)
1827 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1830 ret = nicvf_qset_rbdr_reclaim(nic, 0);
1832 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1834 /* Move all charged buffers in RBDR back to pool */
1835 if (nic->rbdr != NULL)
1836 nicvf_rbdr_release_mbufs(dev, nic);
1839 ret = nicvf_qset_reclaim(nic);
1841 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1843 /* Disable all interrupts */
1844 nicvf_disable_all_interrupts(nic);
1846 /* Free RBDR SW structure */
1848 rte_free(nic->rbdr);
1854 nicvf_dev_close(struct rte_eth_dev *dev)
1857 struct nicvf *nic = nicvf_pmd_priv(dev);
1859 PMD_INIT_FUNC_TRACE();
1861 nicvf_dev_stop_cleanup(dev, true);
1862 nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1864 for (i = 0; i < nic->sqs_count; i++) {
1865 if (!nic->snicvf[i])
1868 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1873 nicvf_request_sqs(struct nicvf *nic)
1877 assert_primary(nic);
1878 assert(nic->sqs_count > 0);
1879 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1881 /* Set no of Rx/Tx queues in each of the SQsets */
1882 for (i = 0; i < nic->sqs_count; i++) {
1883 if (nicvf_svf_empty())
1884 rte_panic("Cannot assign sufficient number of "
1885 "secondary queues to primary VF%" PRIu8 "\n",
1888 nic->snicvf[i] = nicvf_svf_pop();
1889 nic->snicvf[i]->sqs_id = i;
1892 return nicvf_mbox_request_sqs(nic);
1896 nicvf_dev_configure(struct rte_eth_dev *dev)
1898 struct rte_eth_dev_data *data = dev->data;
1899 struct rte_eth_conf *conf = &data->dev_conf;
1900 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1901 struct rte_eth_txmode *txmode = &conf->txmode;
1902 struct nicvf *nic = nicvf_pmd_priv(dev);
1905 PMD_INIT_FUNC_TRACE();
1907 if (!rte_eal_has_hugepages()) {
1908 PMD_INIT_LOG(INFO, "Huge page is not configured");
1912 /* KEEP_CRC offload flag is not supported by PMD
1913 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
1915 if (rte_eth_dev_must_keep_crc(rxmode->offloads)) {
1916 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1917 rxmode->offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
1920 if (txmode->mq_mode) {
1921 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1925 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1926 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1927 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1931 if (rxmode->split_hdr_size) {
1932 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1936 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1937 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1941 if (conf->dcb_capability_en) {
1942 PMD_INIT_LOG(INFO, "DCB enable not supported");
1946 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1947 PMD_INIT_LOG(INFO, "Flow director not supported");
1951 assert_primary(nic);
1952 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1953 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1954 if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1955 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1956 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1961 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1963 if (nic->sqs_count > 0) {
1964 if (nicvf_request_sqs(nic)) {
1965 rte_panic("Cannot assign sufficient number of "
1966 "secondary queues to PORT%d VF%" PRIu8 "\n",
1967 dev->data->port_id, nic->vf_id);
1971 if (rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM)
1972 nic->offload_cksum = 1;
1974 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1975 dev->data->port_id, nicvf_hw_cap(nic));
1980 /* Initialize and register driver with DPDK Application */
1981 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1982 .dev_configure = nicvf_dev_configure,
1983 .dev_start = nicvf_dev_start,
1984 .dev_stop = nicvf_dev_stop,
1985 .link_update = nicvf_dev_link_update,
1986 .dev_close = nicvf_dev_close,
1987 .stats_get = nicvf_dev_stats_get,
1988 .stats_reset = nicvf_dev_stats_reset,
1989 .promiscuous_enable = nicvf_dev_promisc_enable,
1990 .dev_infos_get = nicvf_dev_info_get,
1991 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1992 .mtu_set = nicvf_dev_set_mtu,
1993 .reta_update = nicvf_dev_reta_update,
1994 .reta_query = nicvf_dev_reta_query,
1995 .rss_hash_update = nicvf_dev_rss_hash_update,
1996 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
1997 .rx_queue_start = nicvf_dev_rx_queue_start,
1998 .rx_queue_stop = nicvf_dev_rx_queue_stop,
1999 .tx_queue_start = nicvf_dev_tx_queue_start,
2000 .tx_queue_stop = nicvf_dev_tx_queue_stop,
2001 .rx_queue_setup = nicvf_dev_rx_queue_setup,
2002 .rx_queue_release = nicvf_dev_rx_queue_release,
2003 .rx_queue_count = nicvf_dev_rx_queue_count,
2004 .tx_queue_setup = nicvf_dev_tx_queue_setup,
2005 .tx_queue_release = nicvf_dev_tx_queue_release,
2006 .get_reg = nicvf_dev_get_regs,
2010 nicvf_set_first_skip(struct rte_eth_dev *dev)
2012 int bytes_to_skip = 0;
2015 struct rte_kvargs *kvlist;
2016 static const char *const skip[] = {
2019 struct nicvf *nic = nicvf_pmd_priv(dev);
2021 if (!dev->device->devargs) {
2022 nicvf_first_skip_config(nic, 0);
2026 kvlist = rte_kvargs_parse(dev->device->devargs->args, skip);
2030 if (kvlist->count == 0)
2033 for (i = 0; i != kvlist->count; ++i) {
2034 const struct rte_kvargs_pair *pair = &kvlist->pairs[i];
2036 if (!strcmp(pair->key, SKIP_DATA_BYTES))
2037 bytes_to_skip = atoi(pair->value);
2040 /*128 bytes amounts to one cache line*/
2041 if (bytes_to_skip >= 0 && bytes_to_skip < 128) {
2042 if (!(bytes_to_skip % 8)) {
2043 nicvf_first_skip_config(nic, (bytes_to_skip / 8));
2044 nic->skip_bytes = bytes_to_skip;
2047 PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8");
2052 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128");
2057 nicvf_first_skip_config(nic, 0);
2059 rte_kvargs_free(kvlist);
2063 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2066 struct rte_pci_device *pci_dev;
2067 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2069 PMD_INIT_FUNC_TRACE();
2071 eth_dev->dev_ops = &nicvf_eth_dev_ops;
2073 /* For secondary processes, the primary has done all the work */
2074 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2076 /* Setup callbacks for secondary process */
2077 nicvf_set_tx_function(eth_dev);
2078 nicvf_set_rx_function(eth_dev);
2081 /* If nic == NULL than it is secondary function
2082 * so ethdev need to be released by caller */
2087 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2088 rte_eth_copy_pci_info(eth_dev, pci_dev);
2090 nic->device_id = pci_dev->id.device_id;
2091 nic->vendor_id = pci_dev->id.vendor_id;
2092 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2093 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2095 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2096 pci_dev->id.vendor_id, pci_dev->id.device_id,
2097 pci_dev->addr.domain, pci_dev->addr.bus,
2098 pci_dev->addr.devid, pci_dev->addr.function);
2100 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2101 if (!nic->reg_base) {
2102 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2107 nicvf_disable_all_interrupts(nic);
2109 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2111 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2115 ret = nicvf_mbox_check_pf_ready(nic);
2117 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2121 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2122 nic->node, nic->vf_id,
2123 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2124 nic->sqs_mode ? "true" : "false",
2125 nic->loopback_supported ? "true" : "false"
2129 ret = nicvf_base_init(nic);
2131 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2135 if (nic->sqs_mode) {
2136 /* Push nic to stack of secondary vfs */
2137 nicvf_svf_push(nic);
2139 /* Steal nic pointer from the device for further reuse */
2140 eth_dev->data->dev_private = NULL;
2142 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2143 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2145 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2149 /* Detach port by returning positive error number */
2153 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2154 if (eth_dev->data->mac_addrs == NULL) {
2155 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2159 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2160 eth_random_addr(&nic->mac_addr[0]);
2162 ether_addr_copy((struct ether_addr *)nic->mac_addr,
2163 ð_dev->data->mac_addrs[0]);
2165 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2167 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2171 ret = nicvf_set_first_skip(eth_dev);
2173 PMD_INIT_LOG(ERR, "Failed to configure first skip");
2176 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2177 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2178 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2179 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2184 rte_free(eth_dev->data->mac_addrs);
2186 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2191 static const struct rte_pci_id pci_id_nicvf_map[] = {
2193 .class_id = RTE_CLASS_ANY_ID,
2194 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2195 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2196 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2197 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2200 .class_id = RTE_CLASS_ANY_ID,
2201 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2202 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2203 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2204 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2207 .class_id = RTE_CLASS_ANY_ID,
2208 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2209 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2210 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2211 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2214 .class_id = RTE_CLASS_ANY_ID,
2215 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2216 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2217 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2218 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2225 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2226 struct rte_pci_device *pci_dev)
2228 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2229 nicvf_eth_dev_init);
2232 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2234 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2237 static struct rte_pci_driver rte_nicvf_pmd = {
2238 .id_table = pci_id_nicvf_map,
2239 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2240 RTE_PCI_DRV_INTR_LSC,
2241 .probe = nicvf_eth_pci_probe,
2242 .remove = nicvf_eth_pci_remove,
2245 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2246 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2247 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");
2248 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>");